JP3294330B2 - Character display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a character display device, and more particularly to a character display device useful for a video camera or the like.

[0002]

2. Description of the Related Art Conventionally, in a video camera, a variety of characters such as a time counter, a battery remaining amount, and "recording" are superimposed on a video in addition to a video in order to inform a photographer of an operation state of the camera and a shooting environment. Many are displayed. In order to perform such display, a character stored in a ROM (character generator) for storing character information is read out and superimposed on a video signal when necessary.

In recent years, with the increase in the capacity of a semiconductor memory, a video camera using an image memory has attracted attention. For example, image data once written in the memory is read out by thinning out pixels, or the same pixel is read out. An electronic zoom function is known in which an image is read several times to obtain an image reduction / enlargement effect. Therefore, the applicant of the present application further digitizes a video signal input from, for example, an imaging unit, temporarily writes the video signal into a memory, and cancels the readout axis with the tilt of the camera by angle information from an angle sensor provided in the camera. By scanning and reading in the matching direction, and returning the read video data to an analog video signal again, the one that obtains substantially the same effect as shooting with the camera always kept horizontal is proposed and filed first. ing.

[0004]

However, in the above-described tilt correction apparatus, the photographer can know how much the tilt-corrected image has been corrected and whether the image has been kept horizontal without correction. There is a disadvantage that there is no. Therefore, it is conceivable to store a 360-degree character in the character generator in advance, superimpose the character selected based on the angle information on the video signal, and display the correction amount. However, there is a problem that the capacity of the character generator increases. is there. Furthermore, regarding the reduction and enlargement of the image, the character to be displayed on the reduction / enlargement screen must be prepared in advance in the character generator according to the reduction / enlargement ratio, and the capacity of the character generator is further increased. Problem.

Therefore, an object of the present invention is to allow a user to use a character.
An object of the present invention is to provide a character display device which is excellent in convenience, can appropriately select a character display, and greatly reduces the required capacity of a character generator.

[0006]

In order to solve the above-mentioned problems, a character display device according to the present invention has a predetermined image processing device.
In the character display device configured to display the processed video data together with a character which is information indicating another aspect different from the video, the image data before the image processing is performed.
The first character corresponding to the first character is superimposed on the video data.
1 superimposing means, and video data after performing the image processing.
Second superimposing means for superimposing a signal corresponding to the second character on
And superimpose only the signal corresponding to the first character.
First display mode to be displayed, corresponding to the second character
A second display mode in which only the signals are superimposed and displayed, and
The signal corresponding to the first character and the second character
Of the third display mode in which the signal corresponding to the
Of which at least two display modes
Display mode selecting means for selecting a mode.
It is . Here, the display mode selecting means is a character
Fourth table not displaying characters without superimposing the corresponding signal
Display mode, and these display modes can be selected.
Is done. Further, the image processing corrects a tilt at the time of shooting.
The first character is tilted.
This is a character indicating the amount of correction by the correction processing.

[0007]

According to the present invention, the video data read from the memory storing the digital video data corresponding to the video signal is
When displayed together with character data, the character data signal is rotated, reduced, reduced by means for superimposing the character data signal on the input video signal or the video data stored in the memory.
This eliminates the need to prepare characters corresponding to the respective processing amounts such as the enlargement processing, thereby reducing the capacity of the character generator. In particular, with regard to the inclination correction, it is possible to display and display a character whose inclination always corresponds to the amount of inclination correction of the video.

[0008]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing an embodiment of a character display device according to the present invention, and is a block diagram having a tilt correction function. For easy understanding of the drawings, illustration of clock signal lines to each circuit and a clock signal generation circuit is omitted. A video signal (FIG. 2B) captured by a video camera (FIG. 2A) inclined at an angle θ with respect to the horizontal line is input to an input terminal IN. The input video signal is digitized by the A / D converter 1. The switch circuit 2 is connected to the terminal 2a side when writing a video signal, while the first is output from a character generator (character generator) 9.
When writing the character (rotation amount display character: upward arrow in FIG. 2), the character is switched to the side 2b. That is, a video (FIG. 2C) in which the first character is mixed is output from the switch circuit 2 and supplied to the memory 3. The writing of the video signal in which the first character is mixed into the memory 3 is performed in the scanning direction as shown in FIG. 3A based on the address signal from the writing control circuit 7.

The video signal is read from the memory 3 based on the address signal of the read control circuit 8 controlled by the microcomputer 11 to which the tilt angle information (θ) of the camera is input from the angle sensor 10 as shown in FIG. ) Is performed on an axis inclined by θ with respect to the axis of writing. Also, here, the horizontal correction of the image (correction that obtains the same effect as holding the camera horizontally regardless of the tilt of the camera) is performed, and at the same time, the first character is rotated by the angle θ. (FIG. 2D).
The video signal read from the memory 3 is supplied to an interpolation processing circuit 4
Is interpolated.

The switch circuit 5 is connected to the terminal 5a side when outputting a video signal, and a second character (general character: "00:00" in the figure) such as a time counter display output from the character generator 9. : 00 ")
Is output and connected to the terminal 5b. That is, a video signal in which the second character is mixed is output from the switch circuit 5 and supplied to the D / A converter 6. The D / A converter 6 converts the input video signal into an analog signal. As a result, the horizontally corrected video signal and the angle θ
The first character rotated by only one rotation and the second character not affected by the angle correction are output from the output terminal OUT. The microcomputer 11 performs various controls according to an instruction signal from the operation unit 12.

Next, the reading of the memory in the oblique direction will be described. Reading pixels in the memory obliquely means that pixels stored at the intersection of the xy coordinate grid are read at the intersection of the mn coordinate inclined at an angle θ as shown in FIG. It is considered that. At this time, as can be seen from FIG. 4A, it cannot be said that a point on the mn coordinate necessarily overlaps a pixel on the xy coordinate. Assuming that a point on the xy coordinate is a real pixel and a point on the mn coordinate is a virtual pixel, virtual pixel data is generally derived by taking a weighted average of four neighboring real pixel data.

Now, in the positional relationship as shown in FIG. 4B, the virtual pixel Q is changed to the real pixels P (x, y), P (x + 1, y), P (x, y + 1), P (x, y + 1).
When surrounded by (x + 1, y + 1), the data of the virtual pixel Q is: Q = (1−KY) × X1 + KY × X2 = (1−KX) × (1−KY) × P (x , y) + KY × (1-KY) × P (x + 1, y) + KY × (1-KX) × P (x, y + 1) + KX × KY × P (x + 1, y + 1) ... (Equation 1) KX and KY are interpolation coefficients, and KX is the actual pixel P (x,
y), the distance between the straight line connecting P (x, y + 1) and the virtual pixel Q, KY
Is a straight line connecting the real pixel P (x, y) and P (x + 1, y) and the virtual pixel Q
Represents the distance of Also, since the distance between adjacent pixels is 1, K
X and KY satisfy 0 ≦ KX <1 and 0 ≦ KY <1.

Here, xy coordinates are set as shown in FIG.
When the mn coordinate is inclined at an angle θ in the clockwise direction with respect to the xy coordinate, the x− of an arbitrary virtual pixel Q (m ₀ , n ₀ )
Consider the y coordinate [xm ₀ , yn ₀ ]. The xy coordinates of the read start address Q (0,0) are represented by [xst, ys
t], the read start address of each row is, for example, the read start address Q of the first row (n = 1).
(0,1) = [xst-sin θ, yst + cos
θ], the read start address Q of the second row (n = 2)
(0,1) = [xst−2 × sin θ, yst + 2 × c
os θ], and focusing on x, X _{n = 0} = xst, x _{n = 1} = xst−sin θ, X _{n = 2} = xst−2 × cos θ, and the first term = xst and the tolerance (xo) = − sin θ It turns out that it is an arithmetic progression. The y-axis is the same as the x-axis, the first term =
This is an arithmetic progression of ys, tolerance (yo) = cos θ. Accordingly, the read start address Q of n ₀ th row _{(n = n 0) (0} , n 0) is _{[xst-n 0 × sinθ,} y
st + n ₀ × cos θ].

[0014] In addition, the address of each row of the pixels from the read-out start address of n ₀ line will read the order is,
For example, for the first column (m = 1), Q (1, n ₀ ) = [xs
t−n ₀ × sin θ + cos θ, yst + n ₀ × cos
θ + sin θ], Q (2, n) in the second column (m = 2)
₀ ) = [xst−n ₀ × sin θ + 2 × cos θ, ys
t + n ₀ × cos θ + 2 × sin θ] and the x-axis is the first term =
It can be seen that an arithmetic progression of xst−n ₀ × sin θ, tolerance (xw) = cos θ, and a y-axis is an arithmetic progression of first term = yst + n ₀ × cos θ, tolerance (yw) = sin θ.

Therefore, any virtual pixel Q (m ₀ , n
X-y-axis coordinate of _{0), xm 0 = xst + n 0} × xo + m 0 × xw = xst + n 0 × (-sinθ) + m 0 × cosθ ·· ( Equation _{2) yn 0 = yst + n} 0 × yo + m 0 × YW = yst + n ₀ × cos θ + m ₀ × sin θ (Expression 3)

For example, as shown in FIG.
= 0, ys = 0, θ = 30 °, Q (2,1) can be calculated by the following equations (Equation 2) and (Equation 3). X2 = 0−sin30 ° + 2 × cos30 ° = 1.23 y1 = 0 + cos30 ° + 2 × sin 30 ° = 1.87. P (1,1), P (2,1), P (1,2), P
(2,2) is converted to P (x, y), P (x + 1, y), P (x, y +) in FIG.
1) and P (x + 1, y + 1), x, KX,
y and KY are respectively x = 1 (an integer part of 1.23) KX = 0.23 (a decimal part of 1.23) y = 1 (an integer part of 1.87) KY = 0.87 (an integer part of 1.87) Decimal part). That is, the integer part and the decimal part of the solution of (Equation 2) correspond to x and KX of (Equation 1), respectively, and the integer part and the decimal part of the solution of (Equation 3) correspond to y and KY of (Equation 1), respectively. Equivalent to.

Therefore, as an example, the virtual pixel Q (m, n) data can be read by the circuit 100 shown in FIG. In the figure, 100 corresponds to 100 in FIG. 1, 21 to 24 are memories, 29 is an operation block for performing (Equation 1), 27 is an operation block for performing (Equation 2) and (Equation 3), and 25 is Write control circuit, 26 is a read control circuit, 28 is a microcomputer, IN is an input terminal,
OUT indicates an output terminal. To read out the virtual pixel Q only needs to be able to calculate (Equation 1). To realize this, four pixels P (x, y), P (x + 1, y), P (x, y)
+1) and P (x + 1, y + 1) must be read simultaneously.

Then, the video signal input from the input terminal 23 is written into four memories 21 to 24 and the data of the even columns and the even rows are written based on the address signals of the control circuit 25 as shown in FIG. In the memory 21, data of even columns and odd columns are written to the memory 22, data of odd columns and even rows are written to the memory 23, and data of odd columns and odd rows are written to the memory 24.

According to such a memory configuration, P (x, y), P (x, y)
(x + 1, y), P (x, y + 1), P (x + 1, y + 1) are stored in the memories 21 to 2
4 and can be read simultaneously.
The four memories are read based on the address signals determined by the integer parts x and y of the solutions of (Equation 2) and (Equation 3) calculated by the operation block 27.

The operation block 27 is realized by, for example, a configuration as shown in FIG. Since (Equation 2) and (Equation 3) are the same operation with different coefficients, the explanation will be made with (Equation 2) using the configuration of (a).
Xs of xst register 30, xw register 31, and xo register 32 at the start of reading for each field
t, xw, and xo are determined by the gradient θ (xst
θ, xw = cos θ, xo = −sin θ). In the first first clock (m = 0), xw from the xw register 31 is added to the delay element 35 (one clock delay) via the adder 33.
, Xo from the xo register 32 is input to the delay element 36 (one-line delay) via the adder 34,
No output from 6.

At the second clock (m = 1), xw supplied to the delay element 35 at the first clock is output.
7 and the terminal b of the adder 33. The xw supplied from the delay element 35 to the terminal b of the adder 33 is the xw supplied from the xw register 31 to the terminal a of the adder 33.
w, and is added to the delay element 35 as xw + xw, that is, 2 × xw.

Similarly, at the third clock (m = 2), 2 × xw supplied to the delay element 35 at the second clock is output and supplied to the terminal b of the adder 37 and the terminal b of the adder 33. In other words, based on the same idea, m ₀ × xw is supplied to the terminal b of the adder 37 at an arbitrary m ₀ +1 clock (m = m ₀ ). Since xw is reset once each time one line is read, m ₀ +
Also for the first clock, the terminal of the adder 37 is m ₀ × x
w will be supplied.

The delay element 36 is a line delay element, and there is no output until the first clock of the second line.
= 0) is the terminal b of the adder 38 and the terminal b of the adder 34
No signal is input to the terminal a of the adder 38 and every clock x
The wo supplied from the o register 32 is supplied to the delay element 36 as it is.

[0024] m ₀ clock of the second line (n = 1) is, xo is supplied to the delay element 36 to m ₀ clock of the first line is output, the terminal b of the adder 38, the adder 34
Is supplied to the terminal b. The xo supplied from the delay element 36 to the terminal b of the adder 34 is added to the xo supplied from the xo register to the a of the adder 33, and becomes xo + xo, that is, 2 × xo, and is supplied to the delay element 36.

Similarly, at the m ₀ clock of the third line (n = 2), 2 × xo supplied to the delay element 36 is output at the m ₀ clock of the second line, and the terminal b of the adder 38 Is supplied to the terminal b of the container 34. In other words, with the same idea,
At the m ₀ clock of the arbitrary n ₀ +1 line (n = n ₀ ), n ₀ × xo is supplied to the terminal b of the adder 38. Therefore, when m = m ₀ and n = n ₀ , the terminals a and b of the adder 37 are xst and m ₀ × xw, respectively.
However, the terminals a and b of the adder 38 are supplied with the output of the adder 37, n ₀ × xo, respectively, and the output terminal is xst + m
₀ × xw + n ₀ × xo is output, which means that (Equation 2) has been calculated.

(Equation 3) has a similar configuration with the YST register 40, YW register 41, YO register 42, adders 43, 44, 47, 48 and delay elements 45, 46 as shown in FIG. Is calculated.

As described above, the integer parts of the solutions of (Equation 2) and (Equation 3) become the read addresses x and y, and the decimal parts become the interpolation coefficients KX and KY. Must be converted to addresses suitable for each memory. Address translation is
Since the principle of columns and rows is the same, only the column addresses will be described below.

When the column address x is an even number, for example, xa = 2M as shown at point a in FIG. 8, the column address of the even-numbered column memory and the column address of the odd-numbered column memory are both quotients obtained by dividing the column address 2M by 2. It becomes M. Also, when the column address x is an odd number, for example, when xb = 2M + 1 as shown at point b in FIG. 8, the column address of the memory for the odd number column is the same as the column address 2M + 1 when x is an even number.
Is divided by 2 (rounded down below the decimal point), and the column address of the even-numbered column memory is M + 1.

Therefore, as shown in FIG. 10A, the column address x is shifted by one bit by the one-bit shift circuit 50, divided by two, and this quotient is output as the column address of the odd-numbered column memory. The least significant bits of the quotient and the column address are added by the adder 51, and the sum is output as the column address of the even-number column memory. When the column address is even, the least significant bit becomes 0 and the quotient is output as it is. When the column address is odd, 1 is added to the quotient and output.
The above description is realized.

As for the row address, as shown in FIG. 10B, the 1-bit shift circuit 60 and the adder 61 simultaneously obtain the row address of the odd-numbered memory and the row address of the even-numbered memory.

P (x, y), P (x + 1, y), P (x, y + 1), P (x + 1, y + 1) read simultaneously from the memory in this manner.
And (Equation 2) and (Equation 3) calculated by the operation block 29
The interpolation coefficients KX and KY, which are decimal numbers of the solution of
9 can be used to calculate (Equation 1).

The operation block 29 is realized, for example, by a configuration as shown in FIG. The switch circuits 72 and 82 switch the output data of the even-numbered column memory and the odd-numbered column memory 72 and 81 and supply the data to the multipliers 74 and 84 for multiplying by the interpolation coefficient 1-KX. Multiplier 7 that switches between the two data items and multiplies by the interpolation coefficient KX
5, 85.

Now, as shown in FIG. 4B, the interpolation coefficients KX, 1
Since -KX is defined so as to be multiplied by x + 1 column data and x column data, respectively, that is, when x is an even number, KX is multiplied by x + 1 column data which is an odd number column, and 1-K
X is multiplied by x column data which is an even column. When x is odd, KX is multiplied by x + 1 column data which is an even column and 1-KX is multiplied by x column data which is an odd column.
Therefore, the switch circuits 72, 73, 82, and 83 are connected to the terminal a when x is an even number, and connected to the b side when x is an odd number, so that x column data is always supplied to the multipliers 74 and 84. , Multipliers 75 and 85 are supplied with x + 1 column data. The switching of the switch may be performed with the least significant bit of the column address as in FIG. In the adder 76, the multiplier 7
Xx (1-KX) of even-numbered rows output from 4, 75;
(X + 1) × KX is added, and X1 is output. The multipliers 84 and 85 multiply x supplied from the switch circuits 82 and 83 by 1−Kx. In the adder 86, the multiplier 8
Xx (1-KX), (x + 1) output from 4, 85
× KX is added, and × 2 is output. It is considered that X1 output from the adder 76 is even-numbered row data, and X2 output from the adder 86 is odd-numbered row data. This means that Q (m, n) has been read.

Further, xst and yst in the equations (2) and (3)
Varies depending on the setting of the center of rotation, but is represented by a function of θ. X1 and X selected by the switch circuit 91 are selected.
2 is multiplied by 1-KY in a multiplier 92 and KY in a multiplier 93, and the multiplication result is added by an adder 94 to obtain Q (m,
n) is obtained.

Although the present embodiment has described in detail the display of a character at the time of tilt correction, in particular, in this case, the amount of correction can be transmitted to the photographer by displaying a character that tilts in accordance with the tilt of the camera itself. Is preferred. Similarly, when the character is weighed in the image signal before being stored in the memory at the time of the reduction processing, the character itself receives the reduction processing similar to the video. In particular, if the reduced images are used in a multi-screen or the like that simultaneously displays the reduced images, the characters of each reduced screen can be displayed at the same position and size without independently setting addresses. The same applies to the enlargement, and when the memory is read as it is, that is, when the image processing is not performed, the character can be displayed by superimposing the character on the video signal before being stored in the memory. In this case, the first character can also serve as the second character.

Further, in FIG. 1, the operation unit 12 displays only the first character whose character mode changes in accordance with image processing such as rotation, reduction, enlargement, and the like.
Display mode, a second mode for displaying only the second character having no relation to the image processing, a third display mode for using the first character display mode and the second character display mode in combination, and a character display mode. No display at all 4
It is also possible to set four types of modes and selectively use these as appropriate.

[0037]

As described above, according to the present invention,
The user can select the character display as appropriate to improve convenience
Can be Further, the characters to be displayed in the image-processed video signal do not require the number of image processing
Thus, the capacity of the character generator can be significantly reduced, and the degree of image processing (for example, the rotation angle of the rotation processing) can be displayed.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram showing one embodiment of the present invention.

FIG. 2 is a diagram illustrating a state of a camera inclined by an angle θ with respect to a horizontal line, and states of a subject and an image.

FIG. 3 is a conceptual diagram of oblique reading of a memory according to an embodiment of the present invention.

FIG. 4 is a diagram illustrating the state and positional relationship of pixels at the time of reading the memory in an oblique direction according to the embodiment of the present invention.

FIG. 5 is a diagram illustrating calculation of a positional relationship between a real pixel and a virtual pixel according to the embodiment of the present invention.

FIG. 6 is a diagram illustrating an example of calculating a positional relationship between a real pixel and a virtual pixel according to the embodiment of the present invention.

FIG. 7 is a diagram illustrating an example of a configuration block diagram of oblique reading from a memory according to the embodiment of the present invention.

FIG. 8 is an explanatory diagram of a memory configuration in an embodiment of the present invention.

FIG. 9 is a diagram showing an example of a read address and interpolation coefficient generation circuit in the embodiment of the present invention.

FIG. 10 is a diagram showing another example of a read address in the embodiment of the present invention.

FIG. 11 is a diagram illustrating an example of an interpolation processing circuit according to an embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 A / D converter 2 Switch circuit 3 Memory 4 Interpolation circuit 6 D / A converter 7 Write control circuit 8 Read control circuit 9 Character generator 10 Angle sensor 11 Microcomputer 12 Operation part

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5/225 H04N 5/278

Claims (3)

(57) [Claims] (1)Predetermined image processing has been performedVideo data,
A character that is information indicating another aspect different from the video
In the character display device that is displayed together
hand,The first character is added to the video data before performing the image processing.
First superimposing means for superimposing the corresponding signal; ,A second character is added to the video data after the image processing.
Second superimposing means for superimposing a signal corresponding to the data, Only the signal corresponding to the first character is superimposed and displayed.
A first display mode, a signal corresponding to the second character
A second display mode in which only the
The signal corresponding to the first character and the signal corresponding to the second character
Of the third display mode in which the signal of
At least two display modes, these display modes
Display mode selection means for selecting  A character display device comprising: 2. The display mode selection means according to claim 1, wherein
4th display that does not display characters without superimposing the corresponding signal
Mode, and these display modes can be selected.
The character display according to claim 1, wherein the character is displayed.
apparatus. 3. The image processing device according to claim 1, wherein the image processing corrects a tilt at the time of photographing.
This is a tilt correction process, in which the first character sets a correction amount by the tilt correction process.
2. The character according to claim 1, wherein
3. The character display device according to 2.