JPS63147244A - Picture memory circuit - Google Patents

Abstract

PURPOSE:To simply and quickly perform a special display by giving serial accesses to column direction address in an increase or decrease direction via an address transfer means in response to a direction indication signal. CONSTITUTION:A column address decoder 15 which receives supply of column addresses produces the column selecting signal of 1 with only the column corresponding to a column address together with the column selecting signal of 0 produced with other columns respectively. These column selecting signal are loaded to a bidirectional shift register 16 on an address transfer means. Then the register 16 shifts 1 of the column selecting signals to the right or the left for each clock received from a terminal 17 in response to the direction indicating signal applied to a terminal 18 and controls a selector 19 while increasing or decreasing the column addresses. Thus the data read out of a row buffer 14 to be tempoporarily stored and given from a memory cell array 13 is read out to simply and quickly perform a special display of a right-left inverted picture, etc.

Description

[Detailed Description of the Invention] [Summary] The present invention is an image memory circuit, which comprises a transfer means,
By performing bidirectional serial access, it is possible to easily perform inverted display of images, etc.

[Industrial application field]

The present invention relates to an image memory circuit, and more particularly to an image memory circuit that performs serial access.

Recently, it has become common to use a memory having a serial access port as an image memory.

[Conventional technology]

A conventional image memory having a serial access port specifies a row address, transfers pixel data of that row from the memory to a shift register, and outputs it serially from the shift register. Further, pixel data is serially supplied to the shift register, and after the pixel data for one row is latched by the shift register, it is output to the mail.

[Problem that the invention seeks to solve]

In conventional image memories, the pixel data of the shift regime is shifted only in one direction, that is, the increasing direction of column addresses of the memory.

Therefore, when performing a special display such as displaying a horizontally reversed image, it is necessary to specify the memory row address and column address for each pixel and write or read pixel data using a random access board. However, there are problems in that the time required for CPLI to specify an address is longer and the processing is more labor-intensive.

The present invention has been made in view of the above points, and it is an object of the present invention to provide an image memory circuit that can easily perform special displays.

[Means for solving problems]

The image memory circuit of the present invention has transport means (16, 30 , 31), and performs bidirectional serial access in the increasing or decreasing direction of the column address of the specified row.

[Effect] In the present invention, column address, column selection signal.

Bidirectional serial access is performed on a designated row of the memory cell array (13) in the column address increasing or decreasing direction by transferring any of the pixel data in the column address increasing or decreasing direction according to the direction indication signal. Do this.

〔Example〕

FIG. 1 shows a block system diagram of a first embodiment of an image memory circuit according to the present invention. In the figure, a row address is input to a terminal 10, and a column address is input to a terminal 11. This column address indicates the starting position for reading or writing.

The row address is supplied to a row address decoder 12, where it is supplied to a memory cell array 13 as a row selection signal instructing selection of the row corresponding to the row address.

The memory cell array 13 stores pixel data for one screen, and at the time of reading, for example, m pixel data for one row selected by the row selection signal are stored in parallel in an m-stage row buffer? Transferred to 14.

The column address is also supplied to a column address decoder 15, where only the column corresponding to the column address is Mv and the other columns are W.
Bidirectional shift register 1 as column selection signal of QV
6 and loaded.

The bidirectional shift register 16 has the number of stages (m stages) equal to the number of pixels in one row, and is supplied with a clock signal from a terminal 17 and a direction instruction signal from a terminal 18. Also,
The left end input terminal Ll of the bidirectional shift register 16 is connected to the right end output terminal RO, and the right end input terminal R1 is connected to the left end output terminal LO. For this reason, the direction signal is e.g. 17, when instructing a shift in the right direction (column address increasing direction), the Vi? of the bidirectional shift register 16 is input. The stages that output the output are sequentially shifted to the right by the clock signal, and the stage at the right end is shifted to the stage at the left end, and then the stage at the right end is shifted sequentially to the right. When the direction indication signal is v Ov, the stage outputting vlv is similarly moved to the left (in the direction of column address decrease). The column selection signal output from the bidirectional shift register 16 is supplied to the selector 19.

The selector 19 has m stages, each stage is connected one-to-one to each stage of the row buffer 14, and the bidirectional shift register 16
Only the stage to which the column selection signal of vlv is supplied becomes conductive.

Therefore, the selector 19 serially outputs one row of pixel data pixel by pixel from the readout terminal 20 in synchronization with the clock signal. The order in which the pixel data is read out at this time can be arbitrarily set in the increasing or decreasing direction of the column address of the memory cell array 13 according to the direction instruction signal.

During writing, pixel data for each pixel that comes in from the terminal 20 is transferred from the stage where the selector 19 is conductive to the row buffer? 1
4 and is latched to the corresponding stage of row buffer 1.
After one row of pixel data is latched in all stages of the memory cell array 13, this one row of pixel data is transferred and written to the row designated by the row selection signal of the row address decoder 12 of the memory cell array 13. It will be done.

Therefore, by writing pixel data in each row of the memory cell array 13 in the column address decreasing direction (increasing direction) and reading out the column address in the increasing direction (increasing direction) or decreasing direction), a horizontally inverted image is created. can be easily displayed.

Further, for example, by reading pixel data in the direction of increasing column addresses in the odd rows of the memory cell array 13 and reading pixel data in the direction of decreasing column addresses in the even rows, it is possible to perform reciprocating scan display on the CRT. . It should be noted that the CRT's reciprocating scan display is known to reduce the load on the CRT's horizontal deflection circuit and reduce power consumption by scanning odd lines from the left edge of the screen to the right edge and scanning even lines from the right edge of the screen to the left edge of the screen. ing.

FIG. 2 shows a block diagram of a modified example of the circuit of the invention.

In the figure, the same parts as in FIG. 1 are designated by the same reference numerals, and their explanations will be omitted.

In FIG. 2, the column address coming in from terminal 11 is supplied to up/down counter 30 and preset.

The up/down counter 30 receives the direction instruction signal supplied from the terminal 18? When the direction indication signal is 1V, the clock signal from the terminal 17 is counted up, and when the direction indication signal is vOv, the clock signal is counted down.

The output count value of the up/down counter 30 is supplied to the column address decoder 15, and the column selection signal output from the column address decoder is supplied to the selector 19.

In this modification, as well as the circuit shown in the first diagram, it is possible to easily display a horizontally inverted image, and also to perform reciprocating scan display on a CRT.

FIG. 3 shows a block system diagram of a second 1M example of the circuit of the present invention. In the figure, the same parts as in FIG.

In FIG. 3, one row of pixel data read from the memory cell array 13 is supplied in parallel to a bidirectional shift register 31 and preset. Conversely, one row of pixel data output in parallel by the bidirectional shift register 31 is written into the selected row of the memory cell array 13.

The bidirectional shift register 31 has terminals LI and RO.

R1 and LO are connected, and a clock signal and a direction instruction signal are supplied from terminals 17 and 18, respectively, to perform a shift operation similar to the bidirectional shift register 16, but it is connected to the memory cell array 13 and selector 19, respectively. It is possible to perform bidirectional input/output with these devices.

Further, the column selection signal output from the column address decoder 15 is supplied to the selector 19, and during the period when the selector 19 inputs and outputs one row of pixel data, only the stage where the column selection signal is set to vll is conductive. .

Therefore, the bidirectional shift register 31 sequentially shifts one row of pixel data to the right or left to the selector 1.
Serial output is performed for each pixel from the conductive stage 9. Furthermore, after one row of pixel data is received by sequentially shifting the pixel data that comes in from the stage where the selector 19 is conductive to the right or left, this one row of pixel data is transferred to the memory cells in parallel. - Transfer and write to array 13.

Similarly to the circuit shown in the first diagram, in this second embodiment, it is possible to easily display a horizontally inverted image and also to perform reciprocating scan display on a CRT.

Furthermore, the row buffer 14 is not required, simplifying the circuit configuration.

Note that a row address decoder and a column address decoder for random access may be added to the circuits of FIGS. 1, 2, and 3, and the present invention is not limited to the above embodiments.

〔Effect of the invention〕

As described above, according to the image memory circuit of the present invention, each row of the memory cell array can be serially accessed not only in the direction of increasing column addresses but also in the direction of decreasing column addresses, and it is possible to easily display horizontally reversed images. CR
It is possible to display the T reciprocating scan.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a first embodiment of the image memory circuit of the present invention, FIG. 2 is a block diagram of a modification of the circuit of the present invention shown in FIG. 1, and FIG. 3 is a block diagram of a second embodiment of the circuit of the present invention. It is a block system diagram of an example. In the figure, 12 is a row address decoder, 13 is a memory cell array, 14 is a row buffer, 15 is a column address decoder, 16.31 is a bidirectional shift register, 19 is a selector, and 30 is an up-down counter. Agent Patent Attorney Sada Igata - Figure 1 Figure 2 Figure 2 Oq Blind Fl-7 2nd Large Zero Hishij's Floor 2 Kei Takuen @ Figure 3

Claims (1)

[Scope of Claims] An image memory circuit in which a memory cell array (13) is designated by a row address and a column address, and serial access of a designated row is performed using the designated column as a starting position, comprising: or a transfer means (1) for transferring either the column selection signal or the pixel data generated from the column address in the column address increasing direction or decreasing direction according to the direction indicating signal.
6, 30, 31), and performs bidirectional serial access in the direction of increasing or decreasing the column address of the specified row.