JP2001195570A - Device and method for processing image and data stream converting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image processor that can suitably and efficiently perform two-dimensional image processing and macro image processing at a high speed. SOLUTION: After horizontal processing is performed by a first signal processor 110, a horizontal line scan data stream inputted to an image processor 100 is converted in to a vertical line scan data stream, in which horizontal and vertical directions are exchanged, by a first data stream converter 120. This vertical line scan data stream is inputted to a second signal processor 130 for performing the same processing as the first signal processor 110 and original image data are vertically processed. The vertical line scan data stream of the processing result is inputted to a second data stream converter, converted to the original horizontal line scan data stream and outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus and method capable of performing two-dimensional image processing and global image processing at high speed, appropriately and efficiently, and performing such image processing. The present invention relates to a data stream conversion device suitable for

[0002]

2. Description of the Related Art In recent years, digitization has been rapidly promoted in an image processing system. However, an image pickup system on the input side of an image and a display system on the output side are often processed by analog signals. In such an analog portion, it is inevitable that errors and noises such as distortion of a lens of an imaging system, image distortion of a display system, and misconvergence occur. Conventionally, attempts have been made to correct these problems mainly with analog systems, but in many cases, a sufficiently satisfactory processing device has not been realized. On the other hand, many attempts have been made to correct these analog errors and reduce noises by digital systems. Increasing the resolution of a television or ghost reduction can be said to be typical processing supported by digital processing.

[0003]

However, among the errors of the analog system, it is difficult to solve the above-described lens and CRT distortion correction by digital processing.
There is no digital system that can correct moving images with high accuracy in real time. This is due to the enormous amount of calculation involved in correction, but the distortion itself is a planar two-dimensional phenomenon that covers a wide area. Another major reason is that the architecture of this signal processing device is suitable for sequential processing of data, that is, one-dimensional processing and relatively local data processing. Therefore, it is conceivable to newly design a signal processing device having an architecture suitable for a wide range of two-dimensional data processing and to perform a correction process. However, it is actually very difficult in terms of circuit scale and cost.

Accordingly, it is an object of the present invention to provide an image processing apparatus and method capable of performing two-dimensional image processing and global image processing at high speed, appropriately and efficiently. Another object of the present invention is to enable two-dimensional data processing and global data processing for an arbitrary data stream to be performed at high speed and appropriately efficiently even using an existing image processing apparatus. Another object of the present invention is to provide a data stream conversion device for converting a data stream.

[0005]

Therefore, an image processing apparatus according to the present invention has a storage unit for storing arbitrary image data and an image processing unit for writing image data sequentially scanned in a predetermined direction to the storage unit. Write address generation means for sequentially generating write addresses, writing means for writing the input image data to the storage means based on the generated write address, and image data written to the storage means. Read address generating means for sequentially generating read addresses for reading as image data scanned in a desired direction different from the predetermined order; and reading the image data written in the storage means into the generated read data. Image data converting means having reading means for sequentially reading based on an address The relative read image data, and an image processing unit for performing desired processing.

Further, according to the image processing method of the present invention, image data sequentially scanned in a predetermined direction is stored in storage means based on a predetermined write address sequentially generated, and the stored image data is stored in the storage means. Data, sequentially generate a read address for reading as image data scanned in a desired direction different from the predetermined direction, sequentially read the stored image data based on the generated read address, Desired image processing is performed on the read image data.

Further, the data stream conversion apparatus of the present invention has a storage means for storing arbitrary data, and a writing means for sequentially generating a write address for writing a sequence of data sequentially input in a predetermined order to the storage means. Address generating means, writing means for sequentially writing the sequence of data to be sequentially input to the storage means based on the generated write address, and writing the data string written in the storage means to the predetermined position. Read address generation means for sequentially generating a read address for reading in a desired order different from the order of, the sequence of the data written in the storage means, sequentially read based on the generated read address, Reading means for outputting the data sequence in the desired order.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment A first embodiment of the present invention will be described with reference to FIGS. In the first embodiment, the present invention will be described by exemplifying an image processing apparatus that performs predetermined filtering on each pixel of two-dimensional image data with reference to data of pixels adjacent in the horizontal and vertical directions. explain. In each of the following embodiments including this embodiment, one frame is image data of a two-dimensional square image composed of 256 pixels × 256 pixels, and this pixel is subjected to horizontal non-interlaced scanning. Assume that the resulting data stream is to be processed.

FIG. 1 is a block diagram showing the configuration of the image processing apparatus 100. The image processing device 100 includes a first signal processing device 110, a first data stream conversion device 120, a second signal processing device 130, and a second data stream conversion device 140. FIG. 2 is a diagram showing a configuration of the first data stream converter 120. FIG. 3 is a diagram for explaining an image data stream input to the image processing device 100, and FIG. 4 is a diagram for explaining an image data stream converted by the first data stream conversion device 120. FIG.
FIG. 5 is a diagram for describing an image data stream converted by the second data stream conversion device 140. The configuration of each unit of the image processing apparatus 100 will be described with reference to these drawings.

The first signal processing device 110 performs desired signal processing on the sequentially input horizontal line scan data stream of a two-dimensional image as shown in FIG. 3, for example, and processes the resulting data stream. Output to the first data stream converter 120. In the present embodiment, filtering is performed on each pixel using continuous pixel data of a sequentially input data stream, that is, a process of performing filtering with reference to values of horizontally adjacent pixels is performed. Shall be. The first signal processing device 110 is an image DSP having a linear array structure, and performs the above processing according to a program stored in a built-in ROM.

First data stream converter 120
Generates, for a two-dimensional image signal input as a horizontal line scan data stream from the first signal processing device 110, a video signal of a vertical line scan data stream obtained by exchanging the horizontal direction and the vertical direction, and To the signal processing device 130.

The configuration of the first data stream converter 120 will be described in detail with reference to FIG. The first data stream converter 120 includes a write address generator 121, a read address generator 122, a first dual-port RAM 123, and a second dual-port RAM 123.
It has an AM 124 and a timing controller 125.

The write address generator 121 converts the sequentially input horizontal line scan data stream into a first
Generates an address to be stored in the dual port RAM 123 or the second dual port RAM 124,
Output to the first dual port RAM 123 and the second dual port RAM 124. As described above, since the image data of one frame of 256 × 256 pixels is input to the image processing apparatus 100 as shown in FIG. 3, the write address generation unit 121 converts the image data of one frame into the first image data. 0 from address 0x0000 of dual port RAM 123 or second dual port RAM 124
0x0000 to be sequentially recorded at the address xffff
Addresses of 0xffff are sequentially generated. Note that 0x is
Indicates that the value is in hexadecimal notation.

The read address generator 122 outputs the image data stored in the first dual-port RAM 123 or the second dual-port RAM 124 such that the image data is output as a predetermined data stream different from the input data. A read address is generated, and the first dual port RAM 123 and the second dual port RA
M124. In the present embodiment, as shown in FIG. 4, the read address generation unit 122 generates a data stream corresponding to a horizontal line scan data stream of image data obtained by rotating a two-dimensional image by 90 ° clockwise, in other words, an original data stream. Line scan of 2D image
An address for generating a data stream corresponding to the data stream is generated and applied to the memory. That is,
The read address generation unit 122 outputs 0xff00, 0x
fe00 to 0x0000, 0ff01, 0xfe01 to
0x0001, 0xff02 to 0x0002 ... 0x
Addresses ffff to 0x00ff are sequentially generated.

The first dual-port RAM 123 and the second dual-port RAM 124 are memories capable of storing at least one frame of image data. The first dual-port RAM 123 and the second dual-port RAM 124 receive a write address from the write address generator 121 and a read address from the read address generator 122, respectively. Since control signals such as CS, write enable WE, and output enable OE are input, based on the control signals, the sequentially input image data is stored, and the stored image data is sequentially reproduced and output.

At this time, under the control of the timing controller 125, the input image data for each frame is alternately written to the first dual port RAM 123 and the second dual port RAM 124. The image data is read from the first dual-port RAM 123 or the second dual-port RAM 124 to which the input image data has not been written. In addition,
In the present embodiment, the first dual port RAM 1
23 and the first dual-port RAM 123 each have a bit width that allows one word to store one pixel of data, and have an address space of at least 64k.

The timing controller 125 controls each section of the first data stream converter 120 so that the first data stream converter 120 can appropriately convert the image data stream. In particular,
The timing controller 125 converts the clock signal CLK, which is the timing signal of the image data obtained from the input image signal, the horizontal synchronization signal H-SYNC, the vertical synchronization signal V-SYNC, and the like into the write address generation unit 12.
1 and output to the read address generation unit 122. When the image data to be processed is a square image having the same number of input pixels and the same number of output pixels as in the present embodiment, the horizontal synchronization signal H-SYNC and the vertical synchronization signal V-SY for output are used.
The NC may use the horizontal synchronization signal H-SYNC and the vertical synchronization signal V-SYNC of the input image data as they are. However, when the number of input pixels and the number of output pixels of the image data to be processed are different, the timing controller 125
, The horizontal synchronizing signal H-SYN of the input image data
The horizontal synchronization signal H-SYNC and the vertical synchronization signal V-SYNC of the output image data are newly generated based on C and the vertical synchronization signal V-SYNC.

Further, the timing controller 125
Control signals such as a chip select CS, a write enable WE, and an output enable OE are output to the first dual port RAM 123 and the second dual port RAM 124 to control writing and reading of data. Since the first dual-port RAM 123 and the second dual-port RAM 124 have a double buffer configuration as shown in the drawing, the timing controller 125 switches between active / negative of the two systems of RAMs for each V-SYNC of image data. The image data for each frame is alternately written to the two memories, and the image data is read from the memory in which no data is stored.

The second signal processing device 130 is substantially the same as the first signal processing device 110, and is sequentially input from the first data stream conversion device 120, for example, as shown in FIG. Desired signal processing is performed on the vertical line scan data stream of the two-dimensional image, and the data stream resulting from the processing is output to the second data stream converter 140. In the present embodiment, filtering is performed on each pixel using continuous pixel data of a sequentially input data stream, that is, a process of performing filtering with reference to values of adjacent pixels in the vertical direction is performed. Shall be.

Second data stream converter 140
For the two-dimensional image signal input as a vertical line scan data stream from the second signal processing device 130, swaps the vertical direction and the horizontal direction to generate a video signal of the original horizontal line scan data stream; It is output from the image processing apparatus 100 as an image signal as a processing result. This second data stream converter 140
Is almost the same as the configuration of the first data stream converter 120 described above with reference to FIG. 2, and only the configuration of the read address generation unit is different. Therefore, only the read address generator will be described here. In the following description, the reference numerals of the respective components inside the second data stream converter 140 are the same as those of the first data stream converter 140 shown in FIG.
It is assumed that the codes of the respective components inside the data stream converter 120 are used as they are.

The read address generator 122 of the second data stream converter 140 is provided with a first dual port RAM 123 or a second dual port RAM 12
The first dual port generates a read address so that the vertical line scan data stream of the original input image data stored in 4 is output as the same horizontal line scan data stream as when it was input. RAM 123 and second dual-port RAM 1
24.

That is, the first dual port RAM 1
23 and the second dual-port RAM 124 store a data stream corresponding to a horizontal line scan data stream of image data obtained by rotating a two-dimensional image 90 ° clockwise as shown in FIG. On the other hand, as shown in FIG.
Horizontal line scan of image data as if rotated right
An address for generating a data stream corresponding to the data stream is generated and output. For this purpose, the read address generation unit 122 outputs 0x00ff, 0x01
ff to 0xffff, 0x00fe, 0x01fe to 0
xfffe, 0x00fd to 0xffffd ... 0x0
Addresses 000 to 0xff00 are generated in order.

When the read address generation unit 122 generates such an address, the second data stream converter 140 outputs a data stream obtained by converting a vertical line scan data stream into a horizontal line scan data stream. That is, a data stream having the same form as the original data stream input to the image processing apparatus 100 is output, and is output from the image processing apparatus 100 as a processing result signal.

The operation of the image processing apparatus 100 having such a configuration will be described together. The horizontal line scan data stream input to the image processing apparatus 100 is subjected to horizontal processing by a first signal processing apparatus 110, and then processed by a first data stream conversion apparatus 120.
The image data is converted into image data in which the horizontal direction and the vertical direction are exchanged, that is, a vertical line scan data stream. Then, by inputting this vertical line scan data stream to the second signal processing device 130 which performs the same processing as the first signal processing device 110, the vertical processing is performed on the original image data. Then, by inputting this vertical line scan data stream to the second data stream converter 140,
Convert to the original horizontal line scan data stream,
Output.

As described above, according to the image processing apparatus 100 of the first embodiment, a two-dimensional data stream is processed by using a signal processing apparatus such as a DSP specialized for processing a one-dimensional data stream. Can be efficiently performed. That is, since the normal video signal is a horizontal line scan video signal, the horizontal processing can be performed effectively so far, but the vertical processing can be performed efficiently at the same rate as the signal rate. could not. However, the image processing apparatus 10
0, the first data stream converter 120
Since the video signal of the horizontal line scan is converted into the video signal of the vertical line scan, the second signal processing device 130
In the same manner as described above, it is only necessary to perform processing on sequentially input data strings, and real-time processing at the same rate as the signal rate can be performed.

Further, the first data stream converter 120 and the second data stream converter 14
In the case of 0, a dual-port RAM is used as the buffer memories 123 and 124, and the write address and the read address are separately generated by the write address generation unit 121 and the read address generation unit 122. Thus, the conversion of the data stream can be performed substantially simultaneously in real time.

Second Embodiment A second embodiment of the present invention will be described with reference to FIGS. When such conversion of the data stream is performed, if the original data stream and the data stream to be generated, in other words, the write address and the read address have a relatively simple relationship, as in the first embodiment described above. Preferably, the write address and the read address are logically generated. However, for example, local processing or special 2
When performing dimensional filtering or the like, the data stream required for efficient processing is a very complicated data stream in terms of the original data structure, and is a data stream arranged at random. it can. So, efficiently generate such a data stream,
An image processing apparatus capable of performing such image processing efficiently will be described as a second embodiment.
Here, the present invention will be described by exemplifying a case where fisheye correction is performed on input image data.

FIG. 6 is a block diagram showing the configuration of such an image processing apparatus 200. The image processing device 200
Data stream converter 220 and signal processor 2
30. The data stream converter 220 generates a data stream suitable for image processing performed in the subsequent signal processor 230 based on the input horizontal line scan data stream of the two-dimensional image data, and outputs the data stream to the signal processor 230. I do.

The configuration of the data stream converter 220 will be described in detail with reference to FIG. FIG. 7 is a diagram illustrating components related to address generation of the data stream conversion device 220. Data stream converter 220
Are write address generation unit 221 and read address generation unit 22 as components related to the address generation.
2. Timing controller 225 and ROM 226
Having. The configuration and operation of the write address generator 221 and the timing controller 225 are the same as those of the write address generator 121 and the timing controller 125 of the first data stream converter 120 described above.
The configuration and operation are the same.

The read address generator 222 sequentially reads out read address data recorded in the ROM 226 based on a control signal input from the timing controller 225, applies the read address data to a memory (not shown), and sequentially reads data.

The ROM 226 is a ROM in which addresses of pixel data to be read from the memory are stored in the reading order in advance. The address data stored in the ROM 226 is read by the read address generation unit 222 and applied to a memory (not shown) as it is. As described above, in the present embodiment, the signal processing device 23
At 0, fisheye correction is performed. Therefore, the ROM 22
6 stores an address for extracting and reading out a data stream from the input image data of 256 pixels × 256 pixels by a scan line as shown in FIG. Note that the ROM 226 does not store the address itself, but may store a difference from the immediately preceding address, a coefficient of a function for calculating the address, and the like. By doing so, the capacity of the ROM can be reduced, which is effective.

The signal processing device 230 performs desired signal processing on the scan data stream of a two-dimensional image, for example, as shown in FIG. The data stream is output as output data of the image processing device 200. Since the above-described data stream converter 220 obtains roughly fish-eye corrected image data, the signal processor 230 performs processing for correcting the image with higher accuracy. For example, processing such as correcting the pixel value of the interpolated pixel from the pixel values of the four neighboring pixels or calculating the pixel value of a pixel that does not correspond one-to-one with the original image based on the phase information is performed.

The operation of the image processing apparatus 200 having such a configuration will be described together. The horizontal line scan data stream input to the image processing apparatus 200 is converted into rough fish-eye corrected data by extracting data of a specific scan line as shown in FIG. Is done. Then, the converted data stream is input to the signal processing device 230, and further high-precision correction is performed to obtain final fish-eye corrected image data.

As described above, in the image processing device 200 according to the second embodiment, the data stream conversion device 22
By using the ROM 226 at 0, the read address can be generated completely randomly. Therefore, even when a data stream whose relationship with the write data stream is not simple is generated, or when a desired data stream is generated by extracting pixels substantially at random, appropriate processing can be performed, and more flexibility can be obtained. A simple data stream conversion device can be realized. Further, in the image processing device 200 according to the second embodiment, it can be said that the data stream conversion device 220 performs global correction processing and the signal processing device 230 performs local correction processing. . In other words, with such a configuration, it is possible to provide an image processing apparatus that can perform appropriate processing globally and locally and perform desired image processing efficiently.

In this embodiment, the ROM 2
Although 26 is provided for the read address generation unit 222, it may be provided for the write address generation unit 221 so that the write address is determined based on data stored in the ROM 226.

Third Embodiment A third embodiment of the present invention will be described with reference to FIGS. The configuration of the write address generation unit and the read address generation unit of the data stream conversion device is the same as that described in the second embodiment when the correspondence between the read address and the write address is very complicated and close to random. Is preferable, but in other normal cases, the configuration shown in the first embodiment may be used. However, in the embodiment shown in the first embodiment, the write address generator and the read address generator are completely independent. When the correspondence between the write address and the read address is relatively simple, a part of the generation unit may be shared, and one of the addresses may be used to generate the other address. Such a data stream converter is shown as a third embodiment.

FIG. 9 shows the data stream converter 3
FIG. 10 is a diagram illustrating components related to address generation of the address 20; The data stream converter 320 has a write address generator 321, a read address generator 322, and a timing controller 325. The configuration and operation of the write address generator 421 and the timing controller 325 are the same as the configuration and operation of the write address generator 121 and the timing controller 125 of the first data stream converter 120 described above.

Then, the read address generator 322
Generates a read address based on the write address output from the write address generator 321 and outputs the read address to a memory (not shown).

For example, when reading image data stored as a horizontal line scan data stream as described above as a vertical line scan data stream as shown in FIG. 10, the read address generation unit 322 sets the 0x0000, 0x0100-0xff
00, 0x0001-0xff01, 0x0002-0
xff02... Addresses 0x00ff to 0xffff are generated. This address is an address obtained by exchanging the upper 8 bits and the lower 8 bits of the address generated by the write address generation unit 321 when the image data is written as described above.
That is, when generating such a data stream, the read address generation unit 322 interchanges the upper and lower output addresses of the write address generation unit 321 and outputs the same as the read address.

For generating a data stream as described with reference to FIG. 4, for example, the read address generation unit 322
The upper and lower addresses of the output address of 1 may be exchanged, and the value of the upper address may be further subtracted from 255 (0xff) and output as a read address.
For example, if the read address generation unit 322 subtracts the lower address of the output address of the write address generation unit 321 from 255 (0xff) and outputs it as a read address, the data as shown in FIG. Streams can be created.

In the data stream converter having the address generation unit as described above, the same operation as that of the data stream converter of each of the above-described embodiments can be performed, and the same effect can be obtained. With such a configuration, the circuit size of the read address generation unit 322 can be reduced. Note that the write address may be generated in the write address generator 321 based on the read address output from the read address generator 322.

Fourth Embodiment A fourth embodiment of the present invention will be described with reference to FIG. The configuration of the memory unit in the data stream conversion device according to each of the above-described embodiments includes two dual-port RAMs as specifically described with reference to FIG. 2 in the description of the first embodiment. It was intended to be a double buffer. However, dual port R
It is not necessary to use the AM, and a single port RAM may be used. Such a data stream converter is referred to as the fourth.
This is shown as an embodiment.

FIG. 12 is a diagram showing the configuration of the data stream converter 420. The data stream converter 420 includes a write address generator 421, a read address generator 422, a first single port RAM 4
23, a second single port RAM 424, a timing controller 425, a first selector 427, a second selector 428, and a third selector 429. Write address generator 421, read address generator 422, first single port RAM 423 and second
The configuration and operation of the single-port RAM 424 are based on the write address generation unit 121 and the read address generation unit 12 of the first data stream converter 120 described above.
2. The configuration and operation of the first dual-port RAM 123 and the second dual-port RAM 124 are the same.

The timing controller 425 controls each part of the write address generator 421 to the second single port RAM 424 in the same manner as the timing controller 125, and also controls the first selector 427, the second selector 428, and the third selector 429. Outputs a selection signal to each selector so that it is appropriately controlled in accordance with writing and reading of data.

The first selector 427 controls the first single-port RAM 423 and the second single-port RAM 423 based on a selection signal from the timing controller 425.
The output address of the write address generation unit 421 and the output address of the read address generation unit 422 to be applied to the AM 424 are selected.

The second selector 428 transfers the input image data to one of the data line of the first single-port RAM 423 and the data line of the second single-port RAM 424 based on the selection signal from the timing controller 425. Switch whether to output. In other words,
The input data is selected so that the input data is output to the data line of any one of the single-port RAMs to which writing is performed.

The third selector 429 outputs an output of one of the data line of the first single-port RAM 423 and the data line of the second single-port RAM 424 to a data stream converter based on a selection signal from the timing controller 425. Switch to output from 420. In other words, the output data is selected so that the data of the data line of any one of the single port RAMs to be read out is output.

In the data stream converter 420 having such a configuration, the first selector 427 to the third selector 429 are connected to the first single-port RAM.
If switching is performed in accordance with switching between writing and reading of the 423 and the second single-port RAM 424, the same operation as the data stream converter of each of the above-described embodiments using the dual-port RAM can be performed. And the same effect is obtained. The data stream converter thus has a single port R
AM may be used.

Modifications The present invention is not limited to the present embodiment.
Various modifications are possible. For example, the data stream generated by the data stream conversion device is not limited to the stream exemplified in each of the above-described embodiments, and an arbitrary data stream can be output. For example, the data is read by skipping one line at a time in the vertical direction, that is, 0x00000, 0x0001-
0x00ff, 0x0200, 0x0201 to 0x02
ff ... 0xfe00 to 0xfeff, 0x0100
0x01ff, 0x0300-0x03ff ... 0
If an address is generated and read as xff00 to 0xffff, a non-interlaced image (progressive image) can be converted into an interlaced image as shown in FIG.

Of course, by performing the reverse of this scanning,
It is also possible to convert an interlaced image to a non-interlaced image. By changing the upper and lower addresses simultaneously, scanning in an oblique direction can be performed. In addition, if an address is generated by a pseudo random number such as an M series, encoding and decoding of simple encryption of an image can be easily realized.

The image signal processing performed on the converted data stream may be any processing. For example, correction of lens distortion of an imaging system, correction of CRT distortion of a display system, correction of misconvergence (color shift phenomenon), conversion of a curved image taken by a 360 ° lens into a normal image, two-dimensional FIR filter, Arbitrary processing such as fisheye correction may be performed.

In each of the above-described embodiments, a desired data stream is generated by manipulating a read address. However, a similar process may be performed on a write address, or both may be performed. The address may be operated.

The configuration of the memory (buffer) of the data stream converter is not limited to the configuration of the first embodiment shown in FIG. 2 and the configuration of the fourth embodiment shown in FIG. Instead, any other configuration may be used. DRA
Instead of M, a faster SRAM may be used,
A synchronous DRAM may be used. In this case, the actual configuration of the memory chip may use any combination of chips having any address bus width and any data bus width.
The configuration at the time of mounting such a memory may be arbitrary as long as the configuration is adapted to the image data to be processed.

[0054]

As described above, according to the present invention, it is possible to provide an image processing apparatus and method capable of performing two-dimensional image processing and global image processing at high speed, appropriately, and efficiently. Further, data for converting a data stream so that two-dimensional data processing and global data processing for an arbitrary data stream can be performed quickly, appropriately, and efficiently even when an existing image processing apparatus is used. A stream converter can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an image processing apparatus according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating in detail a configuration of a first data stream conversion device of the image processing device illustrated in FIG. 1;

FIG. 3 is a diagram for explaining an image data stream input to the image processing apparatus shown in FIG. 1;

FIG. 4 is a diagram for explaining an image data stream converted by a first data stream conversion device of the image processing device shown in FIG. 1;

FIG. 5 is a diagram illustrating an image data stream converted by a second data stream conversion device of the image processing device illustrated in FIG. 1;

FIG. 6 is a block diagram illustrating a configuration of an image processing apparatus according to a second embodiment of the present invention.

FIG. 7 is a diagram illustrating in detail a configuration of a data stream conversion device of the image processing device illustrated in FIG. 6;

FIG. 8 is a diagram for explaining an image data stream converted by the data stream conversion device of the image processing device shown in FIG. 7;

FIG. 9 is a diagram illustrating components related to address generation of a data stream conversion device according to a third embodiment of the present invention.

FIG. 10 is a diagram illustrating a first example of an image data stream converted by the data stream conversion device illustrated in FIG. 9;

FIG. 11 is a diagram illustrating a second example of an image data stream converted by the data stream conversion device illustrated in FIG. 9;

FIG. 12 is a block diagram illustrating a configuration of an image processing apparatus according to a fourth embodiment of the present invention.

FIG. 13 is a diagram showing an example of another image data stream converted by the data stream conversion device of the present invention.

[Explanation of symbols]

100: image processing device, 110: first signal processing device,
120: first data stream converter, 121: write address generator, 122: read address generator, 123: first dual-port RAM, 124: second dual-port RAM, 125: timing controller, 130 ... 2, a signal processing device 140, a second data stream conversion device 200, an image processing device 2,
20 data stream converter, 221 write address generator, 222 read address generator, 22
5 timing controller, 226 ROM, 230
... Signal processing device, 320 ... Data stream conversion device,
321, a write address generator, 322, a read address generator, 325, a timing controller, 42
0: data stream converter, 421: write address generator, 422: read address generator, 423
... first single-port RAM, 424 ... second single-port RAM, 425 ... timing controller, 4
27 ... first selector, 428 ... second selector, 42
9: Third selector

Claims (19)

[Claims] A storage unit for storing arbitrary image data; a write address generation unit for sequentially generating a write address for writing image data sequentially scanned in a predetermined direction to be input to the storage unit; A writing unit that writes input image data to the storage unit based on the generated writing address; and the image data written to the storage unit is scanned in a desired direction different from the predetermined order. Image data conversion comprising: read address generation means for sequentially generating read addresses for reading as image data; and read means for sequentially reading the image data written in the storage means based on the generated read addresses. Means, a desired processing for the read image data. An image processing apparatus and an image processing means for performing. 2. The image data subjected to the desired processing is
The image processing apparatus according to claim 1, further comprising a second image data conversion unit that restores the original image data scanned in the predetermined direction. 3. The image processing apparatus according to claim 2, further comprising: a second image processing unit configured to perform the desired processing on the image data scanned in the original predetermined direction. The image processing apparatus according to claim 2, wherein the image processing apparatus performs a desired process. 4. The image processing means according to claim 1, wherein each of the image processing means includes at least one of distortion correction processing of a lens of an imaging system, distortion correction processing of a display system, noise reduction / removal processing, and correction of misconvergence. The image processing apparatus according to claim 3, wherein 5. An apparatus according to claim 1, wherein at least one of said read address generation means and said write address generation means has address storage means in which said sequentially generated addresses are stored in advance, and said stored addresses are sequentially stored. The image processing apparatus according to claim 1, which reads out and outputs. 6. The memory according to claim 1, wherein said address storage means is a ROM (Read).
6. An image forming apparatus comprising an only memory (only memory).
An image processing apparatus according to claim 1. 7. The image processing apparatus according to claim 1, wherein said read address generating means converts said write address generated by said write address generating means to generate said read address. 8. The image processing apparatus according to claim 4, wherein the read address generating means generates the read address by replacing an upper address and a lower address of the write address generated by the write address generating means. . 9. An image data that is sequentially scanned in a predetermined direction and stored in a storage unit based on a predetermined write address that is sequentially generated, and stores the stored image data in the predetermined direction. Sequentially generates read addresses for reading as image data scanned in different desired directions, sequentially reads out the stored image data based on the generated read address, and outputs the read image data to the read image data. An image processing method for performing desired image processing. 10. The image data having undergone the image processing,
Sequentially storing in the storage means, sequentially generating read addresses for reading out the stored image data as original image data scanned in the predetermined direction; and storing the stored image data as the generated The image processing method according to claim 9, wherein the image data is sequentially read based on the read address, and the image data is returned to the original image data scanned in the predetermined direction. 11. A storage means for storing arbitrary data; a write address generation means for sequentially generating a write address for writing a sequence of data sequentially input in a predetermined order into said storage means; Writing means for sequentially writing the data string to the storage means based on the generated write address; and writing the data string written to the storage means in a desired order different from the predetermined order. Read address generation means for sequentially generating a read address for reading; and a sequence of the data written in the storage means is sequentially read based on the generated read address, as the data sequence in the desired order. A data stream conversion device having a reading means for outputting the data; 12. The data stream conversion device according to claim 11, wherein the sequence of data sequentially input in the predetermined order is two-dimensional image data sequentially scanned in a predetermined direction. 13. The read address generation means converts the input two-dimensional image data sequentially scanned in a predetermined direction into two-dimensional image data sequentially scanned in a desired direction different from the predetermined direction. The data stream conversion device according to claim 12, wherein the read address is generated to perform the conversion. 14. At least one of said read address generation means and said write address generation means has an address storage means in which said sequentially generated addresses are stored in advance, and said stored addresses are sequentially stored. The data stream conversion device according to claim 12, which reads out and outputs. 15. The address storage means includes a ROM (Rea).
The data stream conversion device according to claim 14, wherein the data stream conversion device is configured by (d Only Memory). 16. The data stream conversion device according to claim 14, wherein said read address generation means converts said write address generated by said write address generation means to generate said read address. 17. The data stream conversion according to claim 16, wherein said read address generating means generates said read address by replacing an upper address and a lower address of a write address generated by said write address generating means. apparatus. 18. The data stream conversion device according to claim 12, wherein said storage means is constituted by a dual port memory device. 19. The address selecting means for selecting an address generated by one of the read address generating means and the write address generating means and applying the selected address to the storing means. 13. The data stream conversion device according to claim 12, further comprising: a control signal selecting unit configured to apply a control signal generated by one of the reading unit and the writing unit to the storage unit.