JPH0583189B2 - - Google Patents

Info

Publication number
JPH0583189B2
JPH0583189B2 JP62320185A JP32018587A JPH0583189B2 JP H0583189 B2 JPH0583189 B2 JP H0583189B2 JP 62320185 A JP62320185 A JP 62320185A JP 32018587 A JP32018587 A JP 32018587A JP H0583189 B2 JPH0583189 B2 JP H0583189B2
Authority
JP
Japan
Prior art keywords
line outlet
power supply
ground
power
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62320185A
Other languages
English (en)
Japanese (ja)
Other versions
JPH01161857A (ja
Inventor
Hirofumi Yashiro
Myuki Matsumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Device Solutions Corp
Original Assignee
Toshiba Corp
Toshiba Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Microelectronics Corp filed Critical Toshiba Corp
Priority to JP62320185A priority Critical patent/JPH01161857A/ja
Publication of JPH01161857A publication Critical patent/JPH01161857A/ja
Publication of JPH0583189B2 publication Critical patent/JPH0583189B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/211—Design considerations for internal polarisation

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP62320185A 1987-12-18 1987-12-18 半導体集積回路 Granted JPH01161857A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62320185A JPH01161857A (ja) 1987-12-18 1987-12-18 半導体集積回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62320185A JPH01161857A (ja) 1987-12-18 1987-12-18 半導体集積回路

Publications (2)

Publication Number Publication Date
JPH01161857A JPH01161857A (ja) 1989-06-26
JPH0583189B2 true JPH0583189B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1993-11-25

Family

ID=18118648

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62320185A Granted JPH01161857A (ja) 1987-12-18 1987-12-18 半導体集積回路

Country Status (1)

Country Link
JP (1) JPH01161857A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57111045A (en) * 1980-12-26 1982-07-10 Fujitsu Ltd Laying out method for integrated circuit cell

Also Published As

Publication number Publication date
JPH01161857A (ja) 1989-06-26

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