JPH0583124A - Programmable counter - Google Patents

Abstract

PURPOSE:To obtain the programmable counter with high function by selecting the operating mode in response to a signal from an input terminal and a carry signal and inputting a signal in response to the mode to a data input of a flip- flop. CONSTITUTION:An EOR3 and an AND/EOR4 are connected to an output of a D flip-flop 1 to generate a count-up signal of each flip-flop and the count-up signal or input data 10 are selected by a changeover device MUX1-5 and the selected signal is inputted to a D input of the flip-flop 1 to form a synchronization counter. Then a changeover device MUX2-6 is provided and switching signals 12, 13 are generated by using an operating mode switching signal 8, a start signal 9, a carry signal (count end signal) 11 and they are inputted to the MUX1-5. As a result, the changeover of the operating mode by the carry signal 11 and the input signals 8, 9 is attained and continuous frequency division by an optional setting value and only one count at a point of time when an external start signal 9 is inputted are attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing generator such as an IC tester for counting a digital signal with an arbitrary count value to obtain a frequency-divided signal or a delay signal according to the count value. The present invention relates to a programmable counter suitable for a counter circuit.

[0002]

2. Description of the Related Art A conventional programmable counter is an IJ Journal of Solid State Circuits, Vol. 23, number. 2, April 198
8A 1.5-Gigaertz Programmable Divide by Ng Arsenic Counter (IEEE JOU
RNAL OF SOLID-STATE CIRCUITS VOL.23, NO.2, APRIL 1988
"A 1.5-GHz Programmable Divide-by-NGaAs Counte
r "). Although the counter discussed in this section can perform frequency division operation at any set value, it will enter the hold state as soon as the count of the set value is completed, or the start signal from the outside. There is no function such as starting counting from the time when it is obtained, whereas a counter circuit used in a timing generator such as an IC tester requires many counting functions other than such frequency division. Conventionally, an external circuit such as a flip-flop has been added around the conventional counter to meet such a demand.

[0003]

The object of the present invention is, in contrast to the prior art, that not only the frequency can be divided by an arbitrary set value, but also the function of holding at the same time as the completion of counting and the start of the counting by an activation signal from the outside. It is to configure a counter having a function.

[0004]

In order to solve the above-mentioned problems, the present invention provides that all flip-flops are set in a basic circuit of a counter, which is composed of a circuit in which flip-flops and switching circuits are cascade-connected. A terminal for inputting a signal (carry) to be fed back and for inputting an activation signal from the outside, and a terminal for switching the count mode are provided. Further, a switching circuit for switching the operation mode is provided according to the carry signal and the signal from the input terminal,
A programmable counter is configured by inputting a signal corresponding to the mode to the data input of the flip-flop.

[0005]

The counting mode has two modes: a mode (1) in which frequency division is repeated at an arbitrary set value, and a mode (2) in which counting is started by an external start signal and the count is held when the set value is finished. Has two modes.

First, in mode (1), when a carry signal is output, the operation mode switching circuit is switched so as to switch the switching circuit paired with the flip-flop so as to preset the set value in the flip-flop which is the basic circuit of the counter. Set the state of. When the presetting of the set value is completed, the state of each switching circuit is set again so that the normal count state is reached. This allows the frequency division to be repeated with an arbitrary set value.

Next, in the mode (2), the state of the operation mode switching circuit is set so that the switching circuit paired with the flip-flop is in the state of presetting the set value until the activation signal is input. Then, the states of the respective switching circuits are set so that the count state occurs when the activation signal is input. After that, when the carry signal is output, the state of each switching circuit is set so as to be in the hold state.
As a result, it becomes possible to start counting by an activation signal from the outside and hold at the end of counting.

[0008]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram when a 3-bit synchronous counter is constructed as an embodiment of the present invention. 1 is a D-type flip-flop, 2 is a 3-input AND gate, 3
Is E0R, 4 is AND / EOR, 5 is switch 1 (M
UX1), 6 is a switch 2 (MUX2), 7 is a count clock (CLK), 8 is an operation mode switching signal (MODE), 9 is a start signal (START), and 10 is count value input data (PD0 to 2). , 11 is a count end signal (COUT), 12 is a set mode signal (SE
T) and 13 are count mode signals (CNT).

First, in the basic configuration of the counter, EOR3 and AND / EOR4 are connected to the output of the D-type flip-flop 1 to generate a count-up signal for each flip-flop. Next, the count-up signal and the input data 10
Is selected by the MUX 1-5 and input to the D input of the flip-flop 1 to form the basic circuit of the synchronous counter. Here, in order to realize the mode (1) of continuous frequency division with an arbitrary set value and the mode (2) of starting counting by the start signal and holding at the end of counting, which are the objects of the present invention,
MUX2-6 is installed, MODE8, START9, CO
Switching signal SET12, CNT1 by three signals of UT11
3 is generated and is input to MUX1-5. This, MUX2
The relationship between each input signal and the output signal of −6 is as shown in Table 1.

[0011]

[Table 1]

That is, when the MODE8 signal is "0", the mode (1) is set, and when it is "1", the mode (2) is set.

First, in the mode (1), if the count end signal COUT11 is "0", the count-up is continued, and when it becomes "1", the input data 10 is preset and the count-up is started again.

In mode (2), when the START9 signal is "0", the input data 10 is preset at the same time as the hold state. Next, when this signal becomes "1", counting is started. After this, even if the START9 signal becomes "0", the count end signal COUT11
Continues counting until becomes "1". And COU
When T11 becomes "1", the hold state is set, and the hold state is maintained until the START9 signal becomes "1" again.

In the present embodiment, for the convenience of explaining the function of the present invention, the circuits for realizing the carry input for enabling the cascade connection and the functions such as master reset, preset and hold are omitted. .. Further, in the present embodiment, the case of the 3-bit synchronous up counter has been shown, but it is possible to easily estimate from the present embodiment that the number of bits is increased or the configuration is changed to an asynchronous type, a down counter or the like.

[0016]

According to the present invention, a highly functional programmable counter can be realized. Further, by applying this counter to a timing generation circuit such as an IC tester, a rate counter or a phase counter can be easily constructed.
Further, it can be applied as a delay / delay counter of a trigger circuit such as a waveform digitizer or a logic analyzer. Further, since the circuit configuration is easy to be integrated into an IC, further miniaturization can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

[Explanation of symbols]

 1 ... D-type flip-flop, 2 ... Three-input AND, 3 ... EOR, 4 ... AND / EOR, 5 ... Switcher, 6 ... Switcher, 7 ... Count clock signal, 8 ... Operation mode switching signal, 9 ... Start-up Signal, 10 ... Input data, 11 ... Count end signal, 12 ... Set mode signal, 13 ... Count mode signal.

Claims (1)

[Claims] 1. A signal indicating that all flip-flops have been set in a counter circuit configured by cascade-connecting a basic circuit consisting of flip-flops and a data input switching circuit of the flip-flops. The input of the start signal and the operation mode switching signal from the outside at the same time, the operation mode can be switched by the carry signal and each input signal, continuous division at any set value, and the start signal from the outside. A programmable counter characterized in that counting is possible only once when is input.