GB2233132A - Synchronous frequency-dividing circuit - Google Patents

Abstract

A glitch-free frequency-divider, e.g. for dividing by 3, which avoids the delay inherent when it is reset prior to the next division, comprises a synchronous logic circuit for dividing a regular input pulse signal by a number M (integral or fractional) greater than 2, comprising a first logic circuit IC1a, IC2a, IC2b, responsive to the input pulse signal to generate N intermediate pulse signals Q2, Q2, Q'2, Q'2 separated equally in phase and each at the input frequency divided by N, where N equals 2 raised to an integral power and is greater than M. A gate circuit IC3 is responsive to the N intermediate pulse signals to generate an output pulse signal at the input frequency divided by M, and a second logic circuit IC1b, IC4, is clocked by the output signal and connected to control the sequential operation of the gate circuit IC3. <IMAGE>

Description

Synchronous Logic Dividing Circuit This invention relates to a logical dividing circuit for dividing a regular input pulse signal by a number greater than 2, for example a divide-by-three circuit, preferably using TTL (transistor-transistor logic) elements.

The purpose of the invention is to provide glitch-free division, i.e. to produce a continuous, regular output pulse signal without extraneous pulses, which does not suffer from the delay, inherent in conventional dividers, between detecting the required output pulse and resetting the divider prior to the next division.

The invention provides a synchronous logic circuit for dividing a regular input pulse signal by a number M greater than 2, comprising a first logic circuit responsive to the input pulse signal to generate N intermediate pulse signals all separated equally in phase and each at the input frequency divided by N, where N equals 2 raised to an integral power and is greater than M, a gate circuit responsive sequentially to the N intermediate pulse signals to generate an output pulse signal at the input frequency divided by M, and a second logic circuit clocked by the output pulse signal and connected to control the sequential operation of the gate circuit. M can be fractional or integral; the range of possible values is from i N + 1 to N. Preferably, M=3, N=4 and the intermediate pulse signals are accordingly in quadriphase.

This circuit does not rely on any resetting of the first logic circuit by feedback from the output, and accordingly It Is potentially much faster, possibly double the speed of conventional dividers of equivalent function.

The invention may be used in a dual modulus prescaler, in which the output is selectable e.g. between divided-by-three and divided-by-four outputs.

A divide-by-three circuit embodying the invention, and modifications of the circuit to achieve division by other numbers, will now be described by way of example, with reference to the accompanying drawings, in which : Figure 1 is a circuit diagram; Figure 2 is a representation of eight pulse signals from different parts of the circuit of Figure 1, all against the same time base, and of a further pulse signal which would be obtained with a modification of that circuit; Figure 3 is a diagram of part of a modified circuit corresponding to Figure 1 for dividing by a number between 5 and 8; and Figure 4, which comprises two halves, is a representation of pulse signals from different parts of a circuit corresponding to Figure 1 and including the part shown in Figure 3, drawn to half the scale of Figure 2.

With reference first to Figures 1 and 2, a J-K bistable or flip-flop ICla is clocked by an input pulse signal CLK in the form of a square wave, as shown in Figure 2. The bistable ICla operates as a toggle because its J input (active high) is maintained high and its K input (active low) is maintained low. Accordingly, its outputs Q1 and Q1 are square waves at half the input frequency, as shown in Figure 2.

These pulse signals Q1, Q1 are fed respectively to the J and K inputs of a second flip-flop IC2a and to the K and J inputs of a third flip-flop IC2b, both clocked by the input signal CLK. The K inputs-of both the second and third flip-flops IC2a, 2b are active low. In this configuration the J input of one flip-flop will be high (active) and the K input of the same device will be low (also active), whilst the J and K inputs of the other flip-flop will be low and high respectively (both inactive); when flip-flop ICla toggles, these states are reversed. On the rising edge of each input clock pulse, the outputs Q2, Q2 or Q2', Q2' of one flip-flop will change state while those of the other flip-flop will remain the same.In this way, as shown in Figure 2, the intermediate pulse signals constituted by outputs Q2, Q2, Q2' and Q2' are square waves in quadriphase at one quarter of the input frequency - the three flip-flops function to divide the Input signal by four.

It is the function of a gate circuit IC3 and a serial shift register IC4, together with an initializing circuit IClb, to select the appropriate portions of the four waveforms Q2, Q2, Q2', Q2' to generate the output signal at one third the input frequency. This generation process is illustrated in Figure 2, in which selected portions at A, B, C and D, shown in heavy lines, are combined sequentially. The portion of the combined output waveform in Figure 2 represents one full cycle of the circuit of Figure 1; the cycle is repeated indefinitely, with no delay.

The gate circuit IC3 comprises four NAND gates IC3a, 3b, 3c and 3d in a wire-ORed configuration, their common output providing the divided-by-three output signal. The gates IC3a, 3b, 3c and 3d have inputs connected respectively to the flip-flop outputs Q2, Q2, Q2' and Q22.

A quad D-type bistable IC4 configured as a shift register, and the shift register initializing circuit, which is a fourth J-K bistable IClb, control the operation of the gate circuit IC3.

Both IClb and IC4 are clocked by the divided output signal.

The Q1 output of the initializing flip-flop IClb is connected to the data input DO of the shift register IC4, and to the input A of gate IC3b. Outputs QO, Q1 and Q2 of the shift register are connected respectively to inputs B, C and D of gates IC3d, IC3a and IC3c. Output Q2 is also connected to the J and K inputs of the flip-flop IClb. The QO and Q1 outputs are fed back to the data inputs D1 and D2 respectively.

On power up, the IClb "set" input SD is initially held low, due to the associated capacitor C1, thereby taking the data input DO of the shift register IC4 high, resetting its outputs and opening gate IC3b : this state constitutes the initial condition, corresponding to the instant at the left-hand side of Figure 2.

On the occurrence of a rising edge on the output waveform of gate IC3b, shift register IC4 is clocked taking its B output high. This provides its own D1 input whilst simultaneously opening gate IC3d. Thus the high on the DO input is progressively shifted through the register. To restart the sequence, IC4's D output, besides opening gate IC3c, provides the J and K inputs to IClb.

Then, when clocked, the IClb output changes state so providing a high DO input to enable the sequence to restart. Operation continues in this manner causing the output waveform to be generated from elements in the required order by the gates being opened in the sequence IC3b, 3d, 3a, 3c. Since these gates are wire-ORed the output is a composite waveform. No resetting has to take place before the process can be restarted.

It will be appreciated that the invention may be implemented in circuits for dividing by a larger number, by composing the output signal in a similar manner from sequentially-selected portions of intermediate signals at an even fraction of the input frequency.

By way of example, as shown at the bottom of Figure 2, a divided-by-3.5 signal may be obtained, by appropriate modifications to the selection circuitry of Figure 1, with two output pulses for every 7 input pulses. The switching sequence is the same as before, i.e. Q2 - Q'2 - Q2 -Q'2, but now the output is changed on every other positive output edge.

A further example will now be described with reference to Figures 3 and 4. A circuit similar to that of Figure 1 has an extra four flip-flops IC2c to 2f, all flip-flops being clocked by the same input pulse signal CLK. In this three-stage circuit, the K inputs to the flip-flops are active high. The pulse signals obtained at the intermediate outputs Q1, Q1, Q2, Q 29 Q2 Q 29 Q3 Q5, Q4 Q6 Q3 Q5, Q4 and Q6 are shown, all to the same time base (starting at time to), in Figure 4; appropriately modified selection circuitry assembles the required output signal by switching between these intermediate outputs.

To obtain division by 5, the switching sequence is Q3 - Q6- Q4 - Q5-Q3 - Q4 - Q5 - Q3, and the resulting composition signal is illustrated in Figure 4B.

Division by 5.5 is achieved by the following switching sequence, which is a 16 stage cycle: Q3 - Q6-Q5-Q3-Q4-Q5- Q6 - Q4- Q3 - Q6 - Q5 - Q3 - Q4 - Q5 - Q6 - Q4 - Q3.

Division by 6 is achieved by the sequence Q3 - Q4 - Q3 Q4-Q3, or else : - Q5 - Q6 - Q5 - Q6- Q5. For division by an even number, there will always be two possible sequences, because each sequence uses only half the available outputs.

Division by 7 involves use of the sequence : Q3 - Q5 Q4- Q6 -Q3 - Q5 -Q4 - Q6- Q3.

The outputs after division by 5, 6 and 7 are shown after that for division by 5, in Figure 4. For division by 8, one output is enabled continuously and the others are disabled; there are eight different possible outputs to choose from.

Claims (7)

1. A synchronous logic circuit for dividing a regular input pulse signal by a number M greater than 2, comprising a first logic circuit responsive to the input pulse signal to generate N intermediate pulse signals all separated equally in phase and each at the input frequency divided by N, where N equals 2 raised to an integral power and is greater than M, a gate circuit responsive sequentially to the N intermediate pulse signals to generate an output pulse signal at the input frequency divided by M, and a second logic circuit clocked by the output pulse signal and connected to control the sequential operation of the gate circuit.

2. A circuit according to Claim 1, in which M=3, N=4 and the intermediate pulse signals are accordingly in quadriphase.

3. A circuit according to Claim 2, in which the first logic circuit comprises a first flip-flop operated as a toggle and clocked by the input pulse signal to divide it by two, the Q and Q divided-by-two outputs being connected to the J and K inputs of each of second and third flip-flops, also clocked by the input pulse signal, which generate the four intermediate pulse signals in quadriphase.

4. A circuit according to Claim 1, 2 or 3, in which the second logic circuit comprises a serial shift register, successive stages of which are connected as inputs to different gates of the gate circuit, the other inputs of those gates being connected to receive the respective intermediate pulse signals.

5. A circuit according to any preceding claim, in which the gate circuit comprises N OR (or NOR) gates with a common output.

6. A circuit according to any preceding claim, consisting of transistor-transistor-logic elements.

7. A synchronous logic dividing circuit substantially as described herein with reference to the accompanying drawings.