JPH0582500A - Mesa type integrated element and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce a process unevenness within a wafer, which is generated by the floe of an etching stirring solution, by a method wherein a multitude of barrier mesas, which are formed into the same form as that of an element, a triangle having a side of a degree identical with one side of the element and other plane forms, are provided in close vicinity to the peripheral; edge of a prescribed region. CONSTITUTION:An element and a photoresist mask for barrier mesas are simultaneously formed on a wafer 1 for GaAs light-emitting device use. The element is etched, an element mesa 2 is formed and such the barrier mesas 3 as to become an obstacle to an etching liquid are formed on the outside of the mesa 2. These barrier mesas 3 are formed in such a way that they are formed into the same from as that of the element, a triangle having a side of a degree identical with one side of the element and other plane forms. After that, a mask 6 consisting of a photoresist is formed and an insulating film 7 at an electrode part is etched. At this tie, as the barrier mesas exist, the floe of the etching liquid is changed and an etching unevenness is not generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mesa type integrated device having a high yield and good in-plane uniformity, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In order to apply optical elements to information processing by utilizing the parallelism of light, it is desirable to integrate elements in the plane direction. Most of the optical elements are made of compound semiconductors such as GaAs and InP. Unlike the ion implantation technique generally used for Si, the element isolation in the compound semiconductor often uses a mesa forming method using etching. Taking a 64-bit light emitting device as an example, FIG.
As shown in the example above, the standard one is 25 μm square,
The mesa-type elements 2 having a height of 5 μm are arranged at a pitch of 30 μm and have a thickness of about 0.
8 × 8 elements are integrated in a 3 mm × 0.3 mm area. A gap of about 1 mm is provided as a cleavage margin between one chip and an adjacent chip.

During a series of processes until the completion of these elements, there are some wet processes in which a wafer is immersed in an etching solution or the like. At that time, in order to increase the reaction rate, it is necessary to stir the solution. Examples of such processes include SiO ₂ and Si used as an insulating film and a passivation film.
There are N dilute hydrofluoric acid etching and a resist developing step at the time of patterning. In the photoresist process, stirring of the developing solution is necessary to prevent the resist from swelling.

[0004]

In the above-described process, there is a problem in that the flow velocity of the etching solution or the developing solution is distributed on the wafer immersed in the stirring solution, which causes uneven etching in the wafer. was there. In particular, the mesa-type element has unevenness in the element state, and the etching rate is slow because the surrounding elements form a wall against the flow of the solution inside the integrated chip, and the elements located in the peripheral area are However, since there is no element on the outside, there is a problem that the etching solution directly contacts and the etching rate becomes faster. In particular, as shown in FIG. 5, the flow 12 of the etching solution impinges on the outermost element of the chip from the side surface.
Therefore, there is a region 11 (FIG. 4) in which the etching rate increases in one chip. As a result, for example, the insulating film on the side surface is peeled off during the selective etching of the insulating film, and a short circuit occurs in the subsequent metal wiring forming process. There is a problem that the yield is reduced. Further, if uneven etching occurs, there is a problem that the uniformity of the device is deteriorated.

Therefore, an object of the present invention is to reduce the process unevenness in the wafer caused by the flow of the agitated solution in the process steps such as etching in which the agitated solution is immersed.

[0006]

The mesa type integrated device of the present invention is a mesa type integrated device in which a large number of mesa type devices are integrated in a predetermined region on a substrate, and is close to the peripheral edge of the predetermined region. In addition, a large number of barrier mesas are provided, and the barrier mesas have the same shape as the element, a triangle having a side approximately equal to one side of the element, or another planar shape.

According to the method of manufacturing a mesa type integrated device of the present invention, a barrier mesa having the same shape as the device, a triangle, or another planar shape is formed outside the chip formed of the integrated device when forming the mesa. It is characterized by

[0008]

According to the structure of the planar integrated device according to the present invention, as shown in FIG. 3, the flow of the stirring solution is caused by the barrier mesa formed around the device so that the stirring solution flows in a pattern of 9. In this way, the element is not directly contacted with the flow in the direction parallel to the surface, and the uniformity of etching in the wafer is improved.

[0009]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a plan view showing a part of a mesa type integrated device for explaining an embodiment of the present invention. Figure 2
FIG. 6B is a cross-sectional view showing a part of the chip structure in the step of etching the insulating film during the process of the mesa type integrated device. G
A photoresist mask for the device and the barrier mesa is simultaneously formed on the aAs light emitting device wafer 1 by a photoresist process. It is etched in a mixed solution of H ₃ PO ₄ , H ₂ O ₂ and H ₂ O to form a mesa 2 of the element and a barrier mesa 3 on the outside of the mesa 2 which interferes with the etching solution. After that, the silicon nitride insulating film 4 is deposited on the entire surface. Then, in order to form the electrode 5 on the mesa, a mask 6 made of photoresist is formed, and the insulating film 7 at the electrode portion is etched in a dilute hydrofluoric acid solution. At that time, in the chip structure without the barrier mesa, the shoulder portion 8 of the mesa is particularly thin in the peripheral element, and when the flow rate of the dilute hydrofluoric acid is high, the insulating film may be partially peeled off. Due to the presence of the barrier mesa 3, the flow of the etching solution is changed as shown in FIG. 3 and the etching unevenness does not occur. afterwards,
The entire surface electrode is formed on the back side of the substrate, and finally the wiring 10 is formed. When forming the wiring, the wiring is formed avoiding the barrier mesa 3 in order to prevent disconnection.

In the above embodiments, the device is a surface type optical device, but the present invention is not limited to this, and the present invention can be applied to a compound semiconductor integrated device in which mesa type devices are integrated.

[0011]

As described above, according to the present invention, it is possible to improve the etching uniformity within a chip without increasing the man-hours, and to produce an integrated device with high yield and high uniformity. You can

[Brief description of drawings]

FIG. 1 is a plan view showing a part of a mesa type integrated device for explaining an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a part of a chip structure in an insulating film etching step during a process of a mesa type integrated device.

FIG. 3 is a conceptual diagram showing a flow of an etching solution when there is a barrier mesa.

FIG. 4 is a plan view showing a part of a wafer seen immediately after formation of a mesa in a process of manufacturing a conventional mesa-type integrated device.

FIG. 5 is a conceptual diagram showing a flow of an etching solution in a conventional example.

[Explanation of symbols]

 1 Wafer for GaAs Light-Emitting Device 2 Mesa 3 Mesa for Barrier 4 Silicon Nitride Insulating Film 5 Electrode 6 Photoresist Mask 7 Insulating Film at Electrode 8 Mesher Shoulder 9 Flow of Etching Solution at Barrier Mesa 10 Wiring 11 Area where etching rate increases 12 Flow of etching solution in conventional example

Claims (2)

[Claims] 1. A mesa type integrated device in which a large number of mesa elements are integrated in a predetermined region on a substrate, and a plurality of barrier mesas are provided in the vicinity of the peripheral edge of the predetermined region. A mesa-type integrated device having the same shape as the device, a triangle having a side approximately equal to one side of the device, and other planar shapes. 2. In a method of manufacturing a mesa type integrated device, a barrier mesa having the same shape as the device, a triangle or other planar shape is formed simultaneously with the mesa of the device, on the outside of a chip composed of the integrated device. A method of manufacturing a mesa type integrated device, comprising: