JPH057788B2 - - Google Patents

Description

[Detailed Description of the Invention] Industrial Application Field The present invention is applicable to the above-mentioned high-speed video system in which a high-speed phenomenon is imaged using a television camera and the imaged output is recorded on, for example, a VTR.
The present invention relates to a video signal generator for obtaining a video signal suitable for recording on a VTR.

BACKGROUND ART AND PROBLEMS Conventionally, high-speed film cameras have been used as devices for capturing and recording high-speed phenomena, but they have had the drawback of not being able to reproduce images instantly. In order to compensate for this drawback, various research and developments have been carried out to capture images of high-speed phenomena using a television camera and record them on a VTR or the like to enable immediate reproduction.

As is well known, a typical television camera requires at least 1/60 second to convert one screen (one field) into an electrical signal. Therefore, dynamic objects that change faster than this cannot be captured.

In order to solve this problem, for example,
No. 26416 discloses that the field of view of the image pickup tube is divided into a plurality of sections, the entire subject is located in each of the divided sections, and the object image on the image pickup tube is scanned for the scanning time corresponding to each section. Techniques are disclosed that enable imaging of high velocity phenomena by scanning.

In addition, Japanese Patent Publication No. 13631/1983 discloses that optical images of a subject are sequentially applied to multiple image pickup tubes with a storage effect for a certain period of time at regular intervals, and the imaging signals from each image pickup tube are recorded in multiple pieces. Techniques are disclosed for supplying an apparatus to continuously record time images of high velocity phenomena.

However, with the technique described in Japanese Patent Publication No. 52-26416, the field of view is substantially narrowed, so that only images of the periphery of a moving object can be obtained. Furthermore, the moving range of the moving object is limited to one divided section, making it unsuitable for general use. Also,
The technique described in Japanese Patent Publication No. 55-13631 requires a plurality of image pickup elements having storage effects and a plurality of recording devices, which results in a complicated configuration and is extremely inconvenient for actual use.

Another technology that is different from the above-mentioned technology is to use an image signal captured by a television camera at a scanning speed that is N times (N is an integer of 2 or more) times that of a normal, that is, standard television signal. , it is also possible to record it as is using a VTR. However, in this case, a high-speed video signal obtained by capturing an image at a speed N times higher than normal is recorded at the same high speed, so the recording bandwidth is also required N times. For this reason, the number of rotations of the rotary head must be increased by N times the normal case, the carrier wave frequency of FM modulation for the video signal must be increased by N times the normal case, and the characteristics of the baseband processing must also be made N times higher. Furthermore, in order to ensure compatibility by adjusting the inclination angle of the recording track to the normal recording pattern, the tape running speed must also be increased by N times.

By playing back the signal recorded at N times the speed on a VTR at the normal rotating head rotation speed and tape running speed, the high-speed phenomenon can be visually captured. Correspondence between and de-emphasis during playback and de-emphasis
It becomes extremely difficult to guarantee the characteristics of the recording/reproducing circuit, such as the frequency stability of the FM modulation signal. Furthermore, even if a baseband processed at N times the baseband during recording is processed at 1/N during playback, it is extremely difficult to guarantee various characteristics. In addition, if the carrier frequency of the FM modulation of the recording signal becomes N times that of a normal VTR, problems arise with the impedance of the rotating head, the characteristics of the rotary transformer, etc.
A system with a large value of is practically impossible.

Furthermore, if the rotational speed of the rotary head is changed between recording and playback, the thickness of the air film layer interposed between the rotary head drum and the tape changes, causing a difference in the scanning state of the head on the tape. The contact pressure against the tape may also change, leading to a decrease in playback sensitivity.

On the other hand, a method is also known in which an equivalently high-speed video signal is obtained by shifting the output of a television camera whose scanning speed is a normal standard scanning speed by a predetermined timing. However, this has the disadvantage of increasing the number of video devices operating at normal speeds and requiring complex mechanisms.

OBJECT OF THE INVENTION The present invention provides a method for making signals from a television camera with a higher than normal scanning speed similar to output signals from a television camera with a normal scanning speed, without the disadvantages mentioned above. The purpose is to enable the processing of

Summary of the Invention This invention has a scanning speed of N (N
is an integer greater than or equal to 2) times a television camera, an A/D conversion circuit that converts the video signal from this television camera into A/D at a high sampling rate, and a speed conversion of the output digital signal of this A/D conversion circuit. and a memory for outputting the output signal of this memory.
and a D/A conversion circuit that converts the A/D.
The output digital signal of the conversion circuit is written to the memory at the high sampling rate, and when reading from this memory, the sampling rate is set to 1/N, and the output is read from this memory in N channels in parallel. This is a video signal generation device that can obtain N-channel parallel digital video signals at a standard scanning speed in units of fields at the output of a memory.

Therefore, according to the present invention, N channels of standard scanning speed video signals can be obtained as outputs of the D/A conversion circuit in field units, making it possible to process these output signals at normal speeds. It is.

Embodiment Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a system diagram of an example of the basic configuration of the device of the present invention. In the figure, reference numeral 1 denotes a television camera which operates at a scanning speed N times the normal scanning speed. In this example, the scanning speed is, for example, tripled. Therefore, the output video signal of this television camera 1 has a frequency band three times that of a television camera with a normal scanning speed. Since the video signal band of a normal television camera is about 6 MHz, the output video signal of this television camera 1 has a band of 18 MHz or more. In addition, since the scanning speed of the video signal output from the television camera 1 is 3x, three fields' worth of video is generated in one field period of a standard television signal, that is, in the case of an NTSC color video signal, a period of 1/60 second. You will get a signal.

The output video signal of this television camera 1 is supplied to an A/D conversion circuit 3 through a low pass filter 2. The low-pass filter 2 is used to limit the signal band, and in this example has a characteristic that allows signals of 20 MHz or less to pass. Further, the A/D conversion circuit 3 samples the video signal at a rate three times faster than when sampling an output video signal from a television camera at a normal scanning rate. Since the sampling rate of a normal television signal is approximately 6 MHz, a sampling rate of, for example, 14.3 MHz (4f _SC ) or 13.5 MHz is usually used in consideration of the color subcarrier frequency f _SC . In this example, the sampling rate in the A/D conversion circuit 3 is three times that
Around 42.9MHz or 40.5MHz will be selected.

In this example, the sampling rate is 40.5MHz, and this 40.5MHz clock signal _CKN is
The signal is supplied to the D conversion circuit 3 and converted into a digital signal of, for example, 8 bits per sample.

The output digital signal of this A/D conversion output path 3 is written into the memory in the speed conversion circuit 4 for three fields per one field period FS of a standard television signal by the same 40.5 MHz clock signal _CKN . At the same time, the digital video signal previously written during this one field period FS is processed in parallel for three fields by the clock signal _CKO of 13.5MHz at 1/3 clock rate, that is, the normal speed. It is read out as a channel signal. Then, the digital video signals read out in parallel are sent to the D/A conversion circuits 5 1 and 5 ₁ , respectively.
At 5 ₂ and 5 ₃ , it is returned to an analog video signal,
It is led out to output terminals 6 ₁ , 6 ₂ , and 6 ₃ .

In this case, the signals of each channel of the three parallel channels from the speed conversion circuit 4 are obtained in field units, for example, the video signal of the first one field of the video signals of three fields read out in one field period FS. is sent to the output terminal ₆₁ as the first channel signal, the second video signal for one field is sent to the output terminal ₆₂ as the second channel signal, and the third video signal for one field is sent as the third channel signal. as output terminal 6 ₃ ,
each will be made available. Since the sampling rate of each channel signal is reduced to 1/3, the signal becomes a normal speed video signal. Therefore, the video signals available at the output terminals 6 ₁ , 6 ₂ , 6 ₃ respectively are exactly equivalent to the video signals from a television camera at normal scanning speed. However, in this case, the signals obtained at each of the output terminals 6 ₁ , 6 ₂ , and 6 ₃ are signals of every third field of the high-speed video signal from the television camera 1, that is, the signals obtained at the output terminal 6 ₁ are the signals of every third field. After the second video signal, for example, the fourth field signal follows, followed by the seventh field, the tenth field, and so on, intermittently in terms of the field order of high-speed video signals. However, the video signal itself is exactly the same as a normal one.

In this way, according to the circuit shown in FIG. 1, a television signal obtained by imaging with a television camera having a high scanning speed is converted in speed, and a signal having the same speed as a standard television signal is obtained in parallel.

Therefore, the signals of each parallel channel can be processed in the same way as normal speed signals.

These three channel signals are then recorded using a special VTR as shown below to form a pattern in, for example, SMPTE type C format.
By playing this on a normal VTR that can play recording tapes in this format, it is possible to view high-speed phenomena in slow motion as a reproduced image.

Figure 2 shows an example of this special VTR rotary head device, which consists of three rotary heads H ₁ , H ₂ ,
H ₃ are installed at equiangular intervals, i.e. 120° square intervals,
On the other hand, a tape 8 is wound around the circumferential surface of the guide drum 7 at a predetermined angle Ω, and these three heads H ₁ ,
H ₂ and H ₃ enable video signals of three parallel channels to be recorded accordingly.

In this case, a VTR with this rotating head device
Since the VTR is designed to record in the SMPTE Type C format, the rotational speed of the rotary head is set at a rate of one rotation per field of a standard television signal, and the VTR is designed to record in the SMPTE Type C format. , but the tape speed is tripled in this case. By increasing the tape speed by three times,
The inclination angle of the track with respect to the longitudinal direction of the tape is different from that of the SMPTE type C format. This can be made to match that of the SMPTE type C format by adjusting the angle at which the tape 8 is wound diagonally around the drum 7 (so-called still angle).

In this way, the head can be opened as shown in Figure 3.
Every third track T ₁₁ , T ₁₂ , T ₁₃ ... by H ₁
is formed, head H ₂ forms every third track T ₂₁ , T ₂₂ , T ₂₃ ... in the adjacent position, and head H ₃ forms every third remaining track.
T ₃₁ , T ₃₂ , T ₃₃ ... are formed. In this case, since the tape speed is triple speed, the tape will shift by one track in the SMPTE type C format from when head _H1 starts scanning until when head _H2 starts scanning. In other words, the pitch of the recording track is also the same as that of the SMPTE Type C format, and completely matches the SMPTE Type C format.

With such a VTR, output terminals 6 ₁ , 6 ₂ ,
For example, the FM modulated signal of the video signal obtained at terminal ₆₁ is sent to head _H1 , and the FM _modulated signal of the video signal obtained at terminal ₆₂ is sent to head H1. ₂ , if the FM modulated signal of the video signal obtained at the terminal ₆₃ is recorded by the head _H3 , the video signal for each field is sequentially recorded on one track _T11 , _T21 , _T31 , _T12 ,
They will be recorded as T ₂₂ , T ₃₂ , etc. In this case, the signals obtained at the output terminals 6 ₁ , 6 ₂ , 6 ₃ are
When recording on a VTR, the head angle interval is
That is, the time period is shifted by 1/3 of one field period FS.

As mentioned above, if a tape recorded in this way is played back using a normal VTR (using one rotating head) that can play back tapes recorded in the SMPTE Type C format, the playback speed will be three times that of a normal VTR. The image at the speed of be.

Note that when the scanning speed of the television camera 1 is set to N times the normal scanning speed as in this example, and the value of N is an odd number, the signals obtained at each output terminal are odd field O, Even field E, odd field O, even field E
By monitoring one channel of the signals, an image similar to that captured by a normal speed television camera can be obtained. That is, for example, if the scanning speed of the television camera 1 is set to 4 times the scanning speed, output signals will be extracted in parallel for every 4 fields of the high-speed video signal.
For example, if the first channel of the video signal obtained in the field period FS is an odd field O, the second channel is an even field E, the third channel is an odd field O, and the fourth channel is an even field E. Similarly, in the field period FS, odd number O, even number E,
Odd number O, even number E, so the video signal of the first channel is always odd field O, the video signal of the second channel is always even field E, etc., and the signal of each channel is a normal field considering interlace. This results in a signal having a different form from that of the television signal. On the other hand, in the case of an odd number multiplication, for example, 3 times the speed as in this example, as shown in Fig. 5, one field period
In FS, the first channel is odd field O,
The second channel is an even field E, the third channel is an odd field O, and in the next one field period FS, the first channel is an even field E, the second channel is an odd field O,
Since the third channel is an even field E, each channel obtains a television signal similar to a normal interlaced television signal in which odd number O, even number E, odd number O, and even number E are arranged alternately.

Specifically, the speed conversion circuit 4 in the circuit shown in FIG. Three channels are read out in parallel at a sampling rate of 1/3.

FIG. 6 shows an example of a specific configuration of this speed conversion circuit 4, which includes three field memories 11 ₁ , 11 ₂ , 1
1 ₃ are provided, and the high-speed digital video signal from the A/D conversion circuit 3 is sent to these field memories 11.
₁ , 11 ₂ , and 11 ₃ . Then, the write address signals ADW ₁ , ADW ₂ , ADW ₃ from the write address setting circuit 12 are supplied to the respective field memories 11 ₁ , 11 ₂ , 11 ₃ , and the read address signal ADR from the read address setting circuit 13 is supplied. ₁ , ADR ₂ , ADR ₃
are field memories 11 ₁ , 11 ₂ , 11 respectively
₃ . The write address signal setting circuit 12 is supplied with a clock signal CK _N of 40.5 MHz, three times the normal speed.
Write address signal ADW that changes at double speed ₁ ~
ADW ₃ is formed. On the other hand, the read address setting circuit 13 is supplied with a clock signal _CKO at a normal speed of 13.5 MHz, and address signals ADR ₁ to ADR ₃ that change at the normal speed are formed. In the memory access operations of these field memories 11 ₁ , 11 ₂ , 11 ₃ , writing and reading are performed in a time-division manner, so that writing and reading can apparently be performed simultaneously. That is, as shown in FIG. 7, the high-speed digital video signal DV (FIG. 7A) is sent to the field memories 11 ₁ , 11 ₂ ,
11 ₃ , but as is clear from FIG. 7B, C, and D, the writing timing is delayed by 1/3 period of one field period FS of the normal speed television signal. .
This means _, for example, that the memories _{11 1 , 11 2 ,} 1
1 ₃ in sequence, and in the write address setting circuit 12, each 1/3 period
The same address will be repeatedly set in F ₁ , F ₂ , and F ₃ . Therefore, the address signal
Since ADW ₁ , ADW ₂ and ADW ₃ are the same, they may be common. Then, as shown in FIGS. 7B, C, and D, in the first 1/3 period _F1 of the period FS, the odd field signal _O1 of the high-speed television signal is written into the field memory ₁₁₁ , and the next one In /3 period _F2 , the even field signal _E1 of the high speed video signal is written to the field memory ₁₁₂ , and in the next 1/3 period _F3 , the next odd field of the high speed video signal is written to the field memory ₁₁₃ . video signal O ₂ is written, and this will be repeated sequentially thereafter.

Then, at the same time as the high-speed video signal is written, the written signal is immediately sequentially read out from each field memory at 1/3 the speed.
Therefore, the read address signals _{ADR 1} , ADR ₂ , supplied to each field memory 11 ₁ , 11 ₂ , 11 ₃ from the read address setting circuit 13
In ADR ₃ , the same address data is sequentially supplied with a shift of 1/3 of the period FS. Therefore, as shown in FIGS. 7E, F, and G, the signals read from the field memories 11 ₁ , 11 ₂ , and 11 ₃ are obtained with a time difference of 1/3 FS. And this is the output terminal 6 ₁ , 6 ₂ , 6
₃ .

As mentioned above, when recording video signals for three channels with a VTR equipped with a rotating head device as shown in Figure 2, it is necessary to record each channel with a 1/3 FS period shift. However, if the speed conversion circuit 4 shown in the example shown in FIG. 6 is used, it becomes possible to record data as is without using any special buffer memory for delay.

Note that field memories 11 ₁ , 11 ₂ , 11 ₃
If the access time is slow, processes such as serial-to-parallel conversion and parallel-to-serial conversion are required when writing and reading digital signals, as in the general case.

FIG. 8 shows another specific example of the configuration of the speed conversion circuit 4. In this example, field memory 11
₁ , ₁₁₂ , and ₁₁₃ , the speed conversion is performed by a line memory having a capacity sufficient to store one horizontal line's worth of video signals. That is, at least three line memories are provided, and the A/D conversion circuit 3 is connected to the three line memories at a high sampling rate.
A high-speed digital video signal is written therein, and speed conversion is performed by reading out three lines in parallel at a normal speed sampling rate. In this example, especially considering the speed of the memory, every three samples are written to the memory in parallel.

In this example, it makes sense to set the sampling frequency at normal speed to 13.5MHz and set the sampling rate at triple speed to 40.5MHz. That is, considering the conditions for determining the sampling frequency of A/D conversion in this example, the horizontal scanning frequency f _H is
In the case of the NTSC system, it is 15.75kHz, and in the case of the PAL system, it is 15.625kHz, and it is desirable that it is a common multiple of these. Because not only NTSC system
This is because it can be directly applied to the PAL system.
Further, it is desirable that the number of clocks per horizontal line on the effective screen be approximately the same in the case of the PAL system and the case of the NTSC system. Furthermore, as in this example, when processing every 3 samples at 3x speed and outputting 3 lines in parallel every horizontal period, the number of clocks per horizontal line is It is desirable that it be a multiple of 3.

The sampling frequency that satisfies the above conditions is
At normal speed, it is 13.5MHz, which is 858 samples per horizontal line for NTSC signals and 864 samples per horizontal line for PAL signals.
It satisfies all of the above conditions. Therefore, selecting a sampling frequency of 13.5 MHz for normal speed and 40.5 MHz for triple speed is extremely beneficial when considering not only NTSC signals but also PAL signals. be.

Next, the configuration of the example shown in FIG. 8 will be explained. A/
The output signal of the D conversion circuit 3 is sent to a shift register 21 driven by a 40.5MHz clock signal _CKN .
It is converted into a 3-sample parallel signal at . That is, the A/D is sent to the shift register 21 every 3 samples.
The output digital signal of the conversion circuit 31 is taken in,
This is latched in three samples in parallel in the latch circuit 22 by the 13.5 MHz clock signal _CKO , and the signal of every three samples is written into the line memory.

As mentioned above, in this example, the output signals for three horizontal lines are obtained in parallel, so in principle, three line memories are sufficient, but by using the fact that the output signal is obtained as a signal for each horizontal line, Special consideration has been given to the processing required for each signal, for example, to enhance the high-frequency components of a video signal obtained from a television camera to sharpen the contours of the image.

Therefore, six line memories are provided. The 3-sample parallel signal from the latch circuit 22 is transmitted to these six line memories 23 ₁ , 23 ₂ . . . 23 ₆
are written sequentially. That is, 3 samples are written in parallel to _the six line memories 23 ₁ , _{23 2} , . However, the period at the beginning of 1/3 of 1 horizontal scanning period HS of a normal television signal
In H _A , the next 1/3HS is stored in line memory 23 ₁ .
The output of the latch circuit 22 is sequentially transferred to the line memory 23 ₂ during the period _HB , to the line memory 23 ₃ during the next 1/3 HS period _HC , and so on. are written into the line memories 23 ₁ to 23 ₆ of the following. This state is shown in FIG.

Of the signals written in the six line memories 23 ₁ to 23 ₆ , the selector 24 selects and takes out signals for five consecutive lines, and these 3
When the lines are taken out in parallel, the signal is supplied to image enhancers 25 ₁ , 25 ₂ , and 25 ₃ as high frequency enhancement circuits for each of the three lines. _At the same time _{, the} signals _{S 0 ,}
Signal S ₁ of specific three lines among S ₁ , S ₂ , S ₃ , S ₄ ,
S ₂ and S ₃ are image enhancers 25 ₁ , 25 ₂ , 25
Delay circuit 26 ₁ , 26 considering the delays in _3
2 , 26 ₃ , and addition circuits 27 ₁ , 27 ₂ , 27 ₃ for horizontal high-frequency emphasis signals as described later.
and a vertical high-frequency emphasis signal addition circuit 28 ₁ ,
Through 28 ₂ , 28 ₃ , field memories 11 ₁ ,
11 ₂ and 11 ₃ . In this case, the signal obtained from the selector 24 is for 5 lines, because when the image enhancers 25 ₁ , 25 ₂ , 25 ₃ obtain high frequency emphasized signals in the vertical direction, the high frequency emphasized signals are This is because the signals of the line before and after the line to be output are required, so it is necessary to read out the signals of the previous line and the line after the three lines of signals to be taken out as output. . The number of line memories of six is the minimum case in which memory access can be ensured for reading and writing. In principle, eight line memories are required, but this can be reduced to six by time-sharing one memory access between the write period and the read period, as described above. . When selecting a line memory in the selector 24, for example, when extracting horizontal line information of "1", "2", and "3", line memories 23 ₁ to 23 ₅ are selected, and the 5th line memory is selected as shown in FIG. Five lines of signals are read out in parallel from the three line memories 23 ₁ to 23 ₅ , and then when information on the horizontal lines "4", "5", and "6" is retrieved, the signals are read out from the line memories 23 ₄ , 23 ₅ ,
23 ₀ , 23 ₁ , and 23 ₂ are selected, and thereafter, a line memory from which signals for the necessary five lines can be obtained is selected. This can be easily achieved by programming the lines to be selected in advance.

Then, similar to the above-described example, this high-frequency emphasized signal is sequentially read out from the field memories 11 ₁ , 11 ₂ , and 11 ₃ with a shift of 1/3 FS period.

In other words, the data for three parallel lines is clocked at a clock rate of 13.5MHz, and the write address setting circuit 1
Write address signal ADW ₁ ′ from 2′,
ADW ₂ ′ and ADW ₃ ′ sequentially write one field of a high-speed video signal in three lines in parallel. That is, as shown in FIG _{. 10} , horizontal lines _{L 1 ,} L ₂ ,
Signals S ₁ , S ₂ , S ₃ of L ₃ are simultaneously clocked at a clock rate of 13.5 MHz to field memories 11 ₁ , 11 ₂ , 11 _{3 .}
are sequentially written to predetermined address locations in
In this case, the upper two bits of the write address indicate the line address, and the lower bits serve as a signal indicating which sample position within the line. The stored contents of the memory shown in Fig. 10 are as follows.
One section corresponds to the capacity of one line. As described above, reading is also performed simultaneously, but writing is performed simultaneously in three lines in parallel, whereas reading is performed line by line in the correct order. Next, the state in which the data is output with a shift of 1/3 FS during reading will be explained below.

10A shows the contents of the field memory 11 ₁ , FIG. 10B shows the contents of the field memory 11 ₂ , and FIG.
indicate the contents of the field memory ₁₁₃ , respectively. At this stage, when the information of the first field of the high-speed video signal has been written to the first field memory ₁₁₁ , this first field memory 1
Reading 1 ₁ means that the data has advanced up to 87.5 lines. and a second high-speed video signal.
The information of the field number is stored in the second field memory 11.
₂ , the first field memory 1
1 The readout of ₁ advances to the 175th line, and the readout of the 2nd
The reading of the field memory ₁₁₂ proceeds to line 87 (because the second field is an even field, the first 1H has only a signal for 0.5 horizontal period). When the information of the third field of the high-speed video signal has been written to the third field memory ₁₁₃ , the readout of the first field memory ₁₁₁ advances to line 262.5, and the readout of the second field memory ₁₁₂ progresses to 262.5 lines.
Proceed to line 174.5 and enter 3rd field memory 1
The readout of 1 ₃ advances to line 87.5. Thereafter, writing and reading are performed in the same manner, and signals shifted by a period of 1/3 FS are obtained at the outputs of the three field memories 11 ₁ , 11 ₂ , and 11 ₃ . By the way, in this case, as is clear from FIG. 11, the signal for one field is 262.5 horizontal lines, which is not divisible by 3, so when writing, the field memory 11 ₁ , 1 is strictly divided into 1/3 FS periods.
If you switch 1 ₂ , 11 ₃ , the 3-line parallel data will be correctly stored in the field memory 11 ₁ , 11 ₂ ,
11 I end up not being able to write to ₃ . Taking this into consideration, writing to the first, second, and third field memories 11 ₁ , 11 ₂ , and 11 ₃ is actually performed at 1/3FS so that three lines of digital data are correctly captured in parallel. As shown in FIG. 11, when changing from an odd field to an even field, the writing period is made to overlap across two memories. That is, the same data is written to two memories. In this way, it is possible to prevent a situation in which one line of data is divided into two field memories and written. Of course, signals are recorded in an overlapping manner on the recording track on the tape, but this overlapping period is a vertical retrace period and has no effect on signal processing. In this example, the overlapping periods are, for example, 1.5 horizontal line periods and a total of 3 horizontal line periods.

Next, image enhancers 25 ₁ , 25 ₂ , 25 ₃
The specific configuration will be explained.

FIG. 12 is an example of this, in which the signals _{S 0} , L ₁ , L ₂ , L ₃ , L ₄ of five consecutive lines from the selector 24,
S ₁ , S ₂ , S ₃ , and S ₄ are respectively level adjustment circuits 30 ₀ ,
The three lines L ₁ to be obtained as output after being adjusted to a predetermined level through 30 ₁ , 30 ₂ , 30 ₃ , 30 ₄
Signal S ₁ of the first line L ₁ of the signals L ₂ and L ₃
The image enhancer 25 for ₁ has its previous line L ₀ and its line L ₁ and its subsequent line L ₂
signals S ₀ , S ₁ , S ₂ are supplied, and the next line
Image enhancer 25 ₂ for signal S ₂ of L ₂
Similarly, _the signals S ₁ , S ₂ , S ₂ , S 2 , S ₂ ,
S ₃ is supplied, and the last line of 3 lines L ₃
Similarly, the image enhancer 25 ₃ for the signal S ₃ of the line L ₂ , L ₃ , L ₄ receives the signals S ₂ , S ₃ ,
S ₄ are supplied each. In other words, the signals of the lines before and after the line to be obtained as output are supplied to the image enhancer for the line to be obtained as an output. Since the configurations of these image enhancers 25 ₁ , 25 ₂ , and 25 ₃ are the same, for ease of explanation,
Here, only the configuration of the image enhancer 25 ₁ for the signal of the first line L ₁ of the three lines will be explained, and the rest will be omitted.

That is, in this image enhancer ₂₅₁ , the signal I _V is first applied to increase the sharpness in the vertical direction.
The signals for these three lines are supplied to the circuit that obtains the signal, and the following processing is performed. That is, the signal S ₀ on the line L ₀ (FIG. 13A) and the signal S ₂ on the line L ₂ (the first
3B) is supplied to the adder circuit 31 to obtain a composite signal S ₁ +S ₂ . This composite signal is supplied to the level adjustment circuit 32 and the level is attenuated to 1/2, thereby obtaining a signal S _M as shown in FIG. 13C. The output signal of this level adjustment circuit 32 is
The signal S ₁ (D in the same figure) of S _M and line L ₁ is the subtraction circuit 33
From this, a signal L ₀ +L ₂ /2-L ₁ is obtained, which is supplied to the level adjustment circuit 35 through the noise removal circuit 34, and a predetermined vertical contour emphasis signal I _V (E in the same figure) is obtained. This is added to the signal on line L ₁ through delay circuit 26 ₁ in adder circuit 28 ₁ . here,
As shown in FIG. 13E, the noise removal circuit 34 is for removing noise on the base portion of the signal _IV , and is a so-called base clip circuit.

Signal S _M from level adjustment circuit 32 and line L ₁
The information signal S ₁ is also added in the adder circuit 36 to obtain a signal L ₀ +L ₂ /2+L ₁ , which is further added in the level adjustment circuit 37 by 1/2.
The level is attenuated to 2. This signal is a signal obtained by interpolating the average value of the signal S ₁ on line L ₁ and the signals S ₀ and S ₂ before and after it, that is, it is a composite signal of the signal that should be at the position of line L ₁ , and can be considered as the signal on line L ₁ . .
The signal on line _L1 from this level adjustment circuit 37 is supplied to a circuit 40 for obtaining a horizontal edge enhancement signal _IH . The circuit 40 for obtaining the horizontal edge enhancement signal I _H is similar to the vertical edge enhancement signal I _H , and the level adjustment circuit 37
The output signal is output from the delay circuit 4 for a predetermined time (a minute time sufficiently smaller than one horizontal scanning period).
The signal delayed by 1 and 2 times through the delay circuit 42 of the same time is supplied to the adder circuit 43 and added to the signal from the level adjustment circuit 37, and the signal is attenuated by 1/2 in the level adjustment circuit 44. Also,
The output signal of the level adjustment circuit 37 is subtracted in the attenuation circuit 45 from the signal delayed by the delay circuit 41 by .times., thereby obtaining a signal similar to that shown in FIG. 13E. Then, like the vertical emphasis signal _IV , this signal passes through the noise removal circuit 46, the level adjustment circuit 47, and the delay circuit 26.
₁ is added to the signal S ₁ on the line L ₁ through the addition circuit 27 ₁ .

The signal obtained by adding the vertical and horizontal edge emphasis signals is written into the field memory 11 ₁ as described above.
The image enhancers 25 ₂ and 25 ₃ for the signals S ₂ and S ₃ of the lines L ₂ and L ₃ are exactly the same, and the field memories 11 ₂ and 11 ₃ are supplied with contour-enhanced signals. Become.

As in this example, in addition to using a field memory for speed conversion, a line memory is provided in the previous stage, and the speed conversion is performed in advance in this line memory, so that the signal for each line is Therefore, the necessary processing for each line can be easily performed at the same time as this speed conversion. Moreover, since this can be done in the form of digital signals, there is the advantage that the signal processing is extremely easy.

The above is an example of using a TV camera 1 with a scanning speed of 3 times, but the scanning speed is not limited to 3 times, and odd and even fields are alternated as parallel signals as described above. Taking this into consideration, it is possible to use a television camera with a scanning speed that is an odd number multiple speed.

The example shown in FIG. 14 is an example in which a television camera that can switch between 3x and 5x scanning speed is used.

In this example, as is clear from the above explanation, the scanning speed of the television camera is set to 3x or 5x.
In synchronization with double-speed operation, various timing signals must be switched accordingly. That is, as shown in FIG. 14, a changeover switch 51 is provided to switch the television camera 1 between the 3x and 5x scanning speeds, and thereby the camera timing signals _t3 and t for the 3x and 5x speeds are provided. ₅ can be switched. Further, the camera output is switched through a switch circuit 52 to a low-pass filter 2A for 3x speed and a low-pass filter 2B for 5x speed in response to switching of the scanning speed of the camera 1. Further, the sampling clock signal of the A/D conversion circuit 3 is also switched by the switch circuit 53 to a clock CK ₃ for triple speed and a clock CK ₅ for quintuple speed in accordance with the speed change. The write clock in the speed conversion circuit 4 is a switch circuit 54.
, the address signal is also set by the selector 55 to address AD ₃ for 3x speed and address AD ₅ for 5x speed.
can be switched to In this case, the normal speed readout clock _CK0 naturally does not need to be switched.

In this example, the output of the speed conversion circuit 4 is 5 D/
The signal is supplied to the A conversion circuits 5 ₁ , 5 ₂ , 5 ₃ , 5 ₄ , and 5 ₅ , but when the speed is 3x, three of them are supplied to the D/A conversion circuits 5 ₁ , 5 ₂ , and 5 _{3 .} is used.

According to this example, it is possible to realize a 3x speed and a 5x speed with one piece of hardware. Therefore, a separate system for 5x speed is not required, which is very convenient.

Effects of the Invention As described above, according to the present invention, a high-speed video signal from a television camera having a scanning speed N times the scanning speed of a standard television signal is converted into a normal signal, that is, a signal having a speed equal to that of the standard television signal. It can be extracted as Therefore, this high-speed signal can be processed in exactly the same way as a standard television signal, without any of the drawbacks that occur when dealing with conventional high-speed signals as mentioned at the beginning.

In addition, in this invention, the speed of the N-times video signal is reduced to 1/N, and at the same time, N channels are extracted in parallel in field units.
If you look at the signals of each channel, you will get a signal that is exactly the same as a normal standard television signal.
If the signals of each channel are viewed on a monitor, a normal image can be obtained as is.

In addition, these N-channel parallel video signals can be processed using a special VTR as shown in the example in the figure.
If SMPTE type C format recording is made, the recorded signal can be played back on a VTR that plays back a normal SMPTE type C format recording tape, thereby allowing high-speed phenomena to be viewed in a relaxed state, that is, in slow motion. It becomes possible to

[Brief explanation of drawings]

FIG. 1 is a system diagram for explaining the basic configuration of this invention, FIGS. 2 and 3 are diagrams for explaining an example of a VTR that records signals obtained by this invention, and FIGS. Figure 5 is a diagram for explaining the field continuity of N-channel parallel output video signals, Figure 6 is a system diagram of an example of the main part of this explanation, Figure 7 is a diagram for its explanation, 8 is a system diagram of another example of the main part of this invention, FIGS. 9, 10, and 11 are diagrams for explaining the same, and FIG. 12 is a diagram of a part of the circuit of the example of FIG. 8. An example of a family tree, No. 13
The figure is a waveform diagram for explaining the circuit in Figure 12.
FIG. 4 is a system diagram of another example of the present invention. 1 is a television camera with high scanning speed, 3 is A/D
conversion circuit, 4 a speed conversion circuit having memory, 5
₁ to 5 ₃ are D/A conversion circuits.

Claims (1)

[Claims] 1 A television camera whose scanning speed is N times the standard scanning speed (N is an integer of 2 or more) and a video signal from this television camera at a high sampling rate.
It has an A/D conversion circuit that performs D conversion, a memory that converts the speed of the output digital signal of this A/D conversion circuit, and a D/A conversion circuit that performs D/A conversion of the output signal of this memory, The output digital signal of the A/D conversion circuit is written to the memory at the high sampling rate, and when read from this memory, the sampling rate is 1/1/2.
N channels and the outputs are read out in parallel from this memory for N channels, so that N channels of parallel digital video signals at a standard scanning speed can be obtained field by field at the output of the memory.