JPH0576056U - Integrated circuit device - Google Patents

Integrated circuit device

Info

Publication number
JPH0576056U
JPH0576056U JP013590U JP1359092U JPH0576056U JP H0576056 U JPH0576056 U JP H0576056U JP 013590 U JP013590 U JP 013590U JP 1359092 U JP1359092 U JP 1359092U JP H0576056 U JPH0576056 U JP H0576056U
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit chip
chip
housed
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP013590U
Other languages
Japanese (ja)
Inventor
泰浩 森
直樹 藤原
Original Assignee
日本プレシジョン・サーキッツ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本プレシジョン・サーキッツ株式会社 filed Critical 日本プレシジョン・サーキッツ株式会社
Priority to JP013590U priority Critical patent/JPH0576056U/en
Publication of JPH0576056U publication Critical patent/JPH0576056U/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Wire Bonding (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

(57)【要約】 【目的】 回路規模が増大しても十分な歩留りを確保す
ることが可能な集積回路装置を提供することである。 【構成】 １１は集積回路チップ、１２はボンディング
パッド、１３は外部回路と接続するためのリ―ド端子、
１４はボンディングワイヤであり、これらの要素は図示
しない単一のパッケ―ジに収納されている。各集積回路
チップ１１は機能ブロック毎に別々に形成されている
が、各集積回路チップ１１だけではシステムとして完全
な動作を行うことはできず、上記単一のパッケ―ジに収
納されているすべての集積回路チップ１１をボンディン
グワイヤ１４で相互接続することにより、初めてシステ
ムとして完全な動作を行うことができる。 (57) [Abstract] [Purpose] To provide an integrated circuit device capable of ensuring a sufficient yield even if the circuit scale increases. [Structure] 11 is an integrated circuit chip, 12 is a bonding pad, 13 is a lead terminal for connecting to an external circuit,
Reference numeral 14 is a bonding wire, and these elements are housed in a single package (not shown). Although each integrated circuit chip 11 is formed separately for each functional block, the integrated circuit chip 11 alone cannot perform a complete operation as a system, and all the integrated circuits are housed in the above-mentioned single package. Only by connecting the integrated circuit chips 11 of FIG. 1 to each other by the bonding wires 14, the complete operation of the system can be performed.

Description

【考案の詳細な説明】[Detailed description of the device]

【０００１】[0001]

【産業上の利用分野】[Industrial applications]

本考案は、集積回路装置に関する。 The present invention relates to an integrated circuit device.

【０００２】[0002]

【従来の技術】[Prior Art]

通常の集積回路装置は、単一の集積回路チップ内にすべての機能を集積化し、 これを所定のパッケ―ジに収納している。 In a typical integrated circuit device, all the functions are integrated in a single integrated circuit chip, and they are stored in a predetermined package.

【０００３】[0003]

【考案が解決しようとする課題】[Problems to be solved by the device]

一般に、回路規模の増大に伴って１チップの当たりの面積も増大するため、そ れだけ不良品が生じる確率が増大する。したがって、上記従来の集積回路装置で は、回路規模の増大に伴って歩留りが低下するという問題点があった。 Generally, as the circuit scale increases, the area per chip also increases, which increases the probability of defective products. Therefore, the above-mentioned conventional integrated circuit device has a problem that the yield decreases as the circuit scale increases.

【０００４】 本考案の目的は、回路規模が増大しても十分な歩留りを確保することが可能な 集積回路装置を提供することである。An object of the present invention is to provide an integrated circuit device capable of ensuring a sufficient yield even if the circuit scale increases.

【０００５】[0005]

【課題を解決するための手段】[Means for Solving the Problems]

本考案における集積回路装置は、一定の動作を行う回路を複数の回路ブロック に分割し、上記各回路ブロック毎に集積回路チップをそれぞれ構成し、上記各集 積回路チップを単一のパッケージに収納したものである。 In the integrated circuit device according to the present invention, a circuit that performs a certain operation is divided into a plurality of circuit blocks, an integrated circuit chip is configured for each circuit block, and each integrated circuit chip is housed in a single package. It was done.

【０００６】[0006]

【実施例】【Example】

図１は、本考案の第１実施例を示した説明図である。１１は集積回路チップ、 １２はボンディングパッド、１３は外部回路と接続するためのリ―ド端子、１４ はボンディングワイヤであり、これらの要素は図示しない単一のパッケ―ジに収 納されている。各集積回路チップ１１は機能ブロック（回路ブロック）毎に別々 に形成されているが、各集積回路チップ１１だけではシステムとして完全な動作 を行うことはできず、上記単一のパッケ―ジに収納されているすべての集積回路 チップ１１をボンディングワイヤ１４で相互接続することにより、初めてシステ ムとして完全な動作を行うことができる。各集積回路チップ１１は、不良解析等 を容易にするために、製造の後工程におけるマルチテストが可能となるように構 成されている。なお、機能ブロック毎に構成された各集積回路チップ１１は、そ れぞれ別々のウエハに作成してもよいし、同一のウエハに作成してもよい。この ように、各集積回路チップ１１を機能ブロック毎に別々に形成しているため、各 集積回路チップ１１の面積を小さくすることができる。 FIG. 1 is an explanatory view showing a first embodiment of the present invention. 11 is an integrated circuit chip, 12 is a bonding pad, 13 is a lead terminal for connecting to an external circuit, 14 is a bonding wire, and these elements are contained in a single package (not shown). . Although each integrated circuit chip 11 is formed separately for each functional block (circuit block), the integrated circuit chip 11 alone cannot perform a complete operation as a system, and is housed in the above-mentioned single package. Only by connecting all the integrated circuit chips 11 to each other with the bonding wires 14, the complete operation of the system can be performed. Each integrated circuit chip 11 is configured to be capable of multi-test in a post-process of manufacturing in order to facilitate defect analysis and the like. The integrated circuit chips 11 configured for each functional block may be formed on different wafers or the same wafer. In this way, since each integrated circuit chip 11 is formed separately for each functional block, the area of each integrated circuit chip 11 can be reduced.

【０００７】 図２は、本考案の第２実施例を示した説明図であり、図１の第１実施例と実質 的に同一の構成要素には同一の番号を付している。上記第１実施例ではボンディ ングパッド１２どうしをボンディングワイヤ１４で直接接続しているため、集積 回路チップ１１に位置ずれが生じたときににボンディングが困難となる場合があ る。これに対して、本実施例では中間端子１５を介してボンディングパッド１２ を相互接続しているため、集積回路チップ１１が多少位置ずれしても容易にボン ディングを行うことができる。FIG. 2 is an explanatory view showing a second embodiment of the present invention, in which substantially the same components as those of the first embodiment of FIG. 1 are designated by the same reference numerals. In the first embodiment, since the bonding pads 12 are directly connected to each other by the bonding wires 14, there are cases where bonding becomes difficult when the integrated circuit chip 11 is displaced. On the other hand, in this embodiment, since the bonding pads 12 are interconnected via the intermediate terminals 15, even if the integrated circuit chip 11 is slightly displaced, the bonding can be easily performed.

【０００８】[0008]

【考案の効果】[Effect of the device]

本考案では、各回路ブロック毎に集積回路チップをそれぞれ構成したので、各 集積回路チップの面積を小さくすることができる。したがって、回路規模が増大 しても十分な歩留りを確保することが可能となる。 In the present invention, since the integrated circuit chip is configured for each circuit block, the area of each integrated circuit chip can be reduced. Therefore, it is possible to secure a sufficient yield even if the circuit scale increases.

【図面の簡単な説明】[Brief description of drawings]

【図１】本考案の第１実施例を示した説明図である。FIG. 1 is an explanatory view showing a first embodiment of the present invention.

【図２】本考案の第２実施例を示した説明図である。FIG. 2 is an explanatory view showing a second embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１１……集積回路チップ 11 ... Integrated circuit chip

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 【請求項１】 一定の動作を行う回路を複数の回路ブロ
ックに分割し、上記各回路ブロック毎に集積回路チップ
をそれぞれ構成し、上記各集積回路チップを単一のパッ
ケージに収納した集積回路装置。1. An integrated circuit device in which a circuit that performs a certain operation is divided into a plurality of circuit blocks, an integrated circuit chip is configured for each circuit block, and each integrated circuit chip is housed in a single package. .
JP013590U 1992-03-16 1992-03-16 Integrated circuit device Withdrawn JPH0576056U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP013590U JPH0576056U (en) 1992-03-16 1992-03-16 Integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP013590U JPH0576056U (en) 1992-03-16 1992-03-16 Integrated circuit device

Publications (1)

Publication Number Publication Date
JPH0576056U true JPH0576056U (en) 1993-10-15

Family

ID=11837415

Family Applications (1)

Application Number Title Priority Date Filing Date
JP013590U Withdrawn JPH0576056U (en) 1992-03-16 1992-03-16 Integrated circuit device

Country Status (1)

Country Link
JP (1) JPH0576056U (en)

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