JPH0575400A - Flip-flop circuit - Google Patents

Abstract

PURPOSE:To provide a current control function and a register reset function through a current control line only without external provision of a circuit for register reset control at the outside of the flip-flop with respect to the flip-flop circuit realizing both the current control function and the register reset function through a common signal line. CONSTITUTION:Since the circuit is devised to have configuration such that constant current sources Ja, Jb are added to the circuit and a reset purpose constant current is always supplied to load resistors R1, R3 in the inside of the flip-flop, it is not required to provide a control circuit for register reset at the outside of the flip-flop and both the current control function and the register reset function are realized by using the current control line only.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip-flop circuit composed of current switching type logic gates such as ECL and SCFL, and more particularly to one having a current control function and a register reset function used in an integrated circuit.

[0002]

2. Description of the Related Art A prescaler is one application example of a flip-flop circuit having a current control function. This is a frequency divider that precedes the programmable counter in the PLL.

By the way, a frequency synthesizer for switching frequency channels in a mobile phone or the like is desired to operate with a low power consumption as much as possible because of the problems of battery life and size reduction. Aims to reduce power consumption by intermittently operating the frequency synthesizer and monitoring the call signal.

In order to further reduce the power consumption of the frequency synthesizer, an initial phase matching technique for reducing the time until the frequency and phase of the synthesizer are locked has been announced, but in order to realize this function. Needs to reset the prescaler registers. The reason is that the shorter the lock time, the shorter the monitoring time of the calling signal can be.

From the above viewpoint, a flip-flop having both a current control function and a register reset function is required.

FIG. 4 shows a conventional flip-flop circuit used in an integrated circuit frequency divider, which can perform a current control function and a register reset function by a common signal. The flip-flop shown in FIG. 4 is a master-slave flip-flop composed of source coupled FET logic (SCFL), and is a D-flip-flop in terms of the type of flip-flop.

In FIG. 4, J _{1 to} J ₂₂ are field effect transistors (hereinafter referred to as FETs), of which J 1
₇ , J ₁₀ , J ₁₁ , J ₁₈ , J ₂₁ , and J ₂₂ operate as a constant current source of a flip-flop. Further, J ₂₃ and J ₂₄ are FETs for register reset, R _{1 to} R ₄ are load resistances of FETs, D _{1 to} D ₆ are diodes, D and / D are data input terminals, and T and / T are clock signal inputs. Terminals, Q and / Q are output terminals, V _DD is a power supply terminal, RC is a common input terminal for current control and register reset, B ₁ is an inverter, RS is a reset signal line, and CS is a current source of this flip-flop circuit. This is a control signal line.

FIG. 5 shows a conventional frequency divider constructed using the flip-flop circuit of FIG. In the figure, 5 is shown in FIG.
, A frequency divider composed of a flip-flop circuit, and B ₁ is an inverter also serving as a delay circuit. RC is a common input terminal for current control and register reset, IN is a frequency division input signal terminal, and OUT is a frequency division output signal terminal.

Next, the operation will be described. In FIG. 4, when the common signal RC is "High", the current control line CS is "High" and the reset signal line RS is "Low".
Flip-flop circuit current sources J ₇ , J ₁₀ , J ₁₁ ,
Current flows through J ₁₈ , J ₂₁ , and J ₂₂ , but current sources J ₂₃ and J _22
No current flows through ₂₄ . Therefore, this flip-flop is in the same state as that without the current sources J ₂₃ and J ₂₄ . At this time, the flip-flop shown in FIG. 4 performs a well-known master-slave flip-flop operation in which data is taken in from the data input terminals D and / D and output from Q and / Q.

When the common signal RC is "Low", the current control line CS is "Low" and the reset signal line RS is "High", so that the current source J ₇ of the flip-flop shown in FIG.
No current flows through J ₁₀ , J ₁₁ , J ₁₈ , J ₂₁ , and J ₂₂ ,
Since current flows through the current sources J ₂₃ and J ₂₄ , the output Q of this flip-flop circuit is forcibly set to “High”. After that, the output Q of the flip-flop is forcibly set to "Hig
When set to h ", the flip-flop is called" reset. "

After that, the common signal RC is changed from "Low" to "Hig.
When set to h ", first the current source J in the flip-flop circuit
_{7, J 10, J 11,} J 18, J 21, the input of the J ₂₂ is operable remains "High". On the other hand, at this time, the reset signal line RS is still "High" due to the delay circuit B _1, so that current continues to flow in the current sources J ₂₃ and J ₂₄ , and the output Q of this flip-flop is in the "High" state. Holds (reset state). When the reset signal line RS becomes "Low" after the delay time elapses, the current sources J ₇ , J ₁₀ ,
Current flows through J ₁₁ , J ₁₈ , J ₂₁ , and J ₂₂ , and current sources J ₂₃ and J
_No current flows through ₂₄ , and the flip-flop eventually starts operating from the reset state.

The operation of the above conventional circuit will be described in more detail below. First, FIG. 6 shows a conventional flip-flop corresponding to the case where the current sources J ₂₃ and J _{24 of} FIG. 4 are not provided, and the operation thereof will be described below with reference to FIG.

In FIG. 6, when the clock / T is "High" and T is "Low", the input data from D and / D are D and / D.
Data is taken in according to the state of. However, since the clock Q of the outputs Q and / Q is "Low", this new data is not sent to the outputs Q and / Q, so the outputs of Q and / Q are the previous D and / D captured. The output is according to the state of.

After that, when T becomes "High" and / T becomes "Low", the newly fetched data is sent to the outputs Q and / Q. This operation is seen from the outside-as shown in Table 1-.

[0015]

[Table 1]

The flip-flop of FIG. 6 basically operates as described above, but in order to show the internal state in more detail, the state until the next data D = 1 and / D = 0 is sent to the output Q is shown. For example: Here, the previous data is D = 0,
It is assumed that / D = 1. Needless to say, "1"
Is a "High" voltage and "0" is a "Low" voltage.

Further, since the flip-flop does not operate unless a current flows, the FETs J _7, J _10, J _11, J
It is assumed that the voltage of the current control line CS is "High" so that _18, J _21, J ₂₂ are all in the "On" state.

Now, the clock is T = “Low” and / T =
If "High", in this state, the previous data D =
Since 0, / D = 1 is output, the signal line l ₂₀ is "Low".
", L ₁₉ is" High ". FETs J ₁₉ and J ₂₁ , F
It can be considered that the source follower unit composed of ET J ₂₀ and J ₂₂ simply level shifts the potentials of the signal lines l ₁₉ and l ₂₀ by the diodes D _{5 and} D ₆ . Not only the slave stage B but also the FE of the source follower section of the master stage A
The same applies to T J _8, J _10, J _{9, and} J ₁₁ . The signal line l ₁₉ is “High” and the signal line l ₂₀ is “Low”.
A current does not flow through the resistor R ₃ , but only a current flows through the resistor R ₄ , but this current is the clock T = “Low”, / T =
The FET J ₁₆ is “Off” and the FET J ₁₇ is “On” from “High”, and the FET connected to the FET J ₁₇ is eventually
Of J ₁₄ and J ₁₅ , it flows through the FET J ₁₅ . Here, when D = 0, / D = 1, the signal line l ₁₄ = “Low”, l ₁₅ =
Although it is "High", it is consistent with the state where the FET J ₁₄ is "Off" and the J ₁₅ is "On", and a current flows through the FET J ₁₅ . In other words, the previous data D = 0, / D = 1
It can be said that the FETs J ₁₄ and J ₁₅ play a role of holding the clock T = “Low” and / T = “High”.

Next, another FET will be examined. Since clock T = “Low” and / T = “High”, FET
J _6, J ₁₆ is "Off", and the thus the _{FET J 3, J 4, J} 12, J 13 connected thereon a current does not flow.

New data D = 1, 1 is input to inputs D and / D.
Since / D = 0, D = of the resistors R ₁ and R ₂
A current flows through the resistor R 1 of the FET J ₁ of _{No. 1} and the current is R ₁
→ J ₁ → J ₅ → J ₇ Therefore, in the signal lines l ₈ and l ₉ , l ₈ is “Low” and l ₉ is “High”,
This signal line potential is level-shifted by the diodes D ₂ and D ₃ and transmitted to the signal lines l ₄ , l ₃ , l ₁₃ and l ₁₂ , and l
₃ = "High", l ₄ = "Low", l ₁₂ = "High", l ₁₃
= Becomes "Low". The fact that l ₃ = “High” and l ₄ = “Low” means that the clock is T = “High”, / T =
It should be noted that when J ₆ is “Low” and J ₆ is “On”, the signal lines l ₈ and l ₉ can be maintained in the states of L ₈ = “Low” and l ₉ = “High”. ..

Now, after that, the clock T = "High" / T
Consider the state where = "Low". At this time, FET
J ₅ and J ₁₇ are “Off”, FETs J ₆ and J ₁₆ are “On”
As described above, the signal line L ₃ = “High”, L ₄
= “Low”, the current flowing from R ₁ → J ₁ → J ₅ → J ₇ is only R ₁ → J ₃ → J ₆ → J _7, and the potentials of the signal lines l ₈ and l ₉ are l ₈ = "Low", l ₉ = "High", the same as before clock inversion.

The signal potentials of the signal lines l ₈ and l ₉ are transmitted to the signal lines l ₁₂ and l ₁₃ as mentioned above, but when T = “High”, J ₁₆ becomes “ "On", so
FETs J ₁₂ and J ₁₃ are in a conductive state, l ₁₂ =
_{"High", l 13 = "} Low" from the current R ₃ → J ₁₂ → J ₁₆
→ flows and J _18. At this time, since the FET J ₁₇ are "Off", the signal line l ₁₄ The _{FET J 14, J 15, l} 15
No current flows regardless of the potential of.

Regarding the potentials of the signal lines l ₁₉ and l ₂₀ , the current is the resistance R
Flow _3, the signal line by not flow to R ₄ l ₁₉ = "Lo
w ", l ₂₀ =" High ". This potential is level-shifted by the level shift diodes D ₅ , D ₆ and appears at the outputs Q, / Q. That is, Q =" High ", / Q =" Lo ".
w "That is, Q = 1, / Q = 0 is output.

The potentials of the signal lines l ₁₄ and l ₁₅ are l ₁₄ =
"High", l ₁₅ = "Low", which means that when the clock becomes T = "Low", / T = "High" after this, the current Q =
It is ready to hold the state of 1, / Q = 0.

As described above, the FETs J ₆ and J ₁₆ and the FETs J ₅ and J ₁₇ are alternately turned "O" according to the clocks T and / T.
n "and" Off ", and according to that, a current flows through either of the two FETs connected to it and determines the state of the flip-flop.

Then, the FET J ₈ , the diode D ₂ , the FET J ₁₀ and J ₉ , the diode D ₃ and the FET J ₁₁ ,
The four source follower sections composed of J ₁₉ , diode D ₅ , FET J ₂₁ , J ₂₀ , diode D ₆ and FET J ₂₂ simply level shift the signal line potential and are not directly involved in the state of the flip-flop. I can't come.

Next, the circuit shown in FIG. 4 in which FETs J ₂₃ and J ₂₄ are present will be described. First of all,
The potential of the reset signal line RS connected to the gates of the FETs J ₂₃ and J ₂₄ is

(I) When RS = "Low", FET J
₂₃ and J ₂₄ are "Off" and operate the same as the circuit of FIG.

(Ii) When RS = "High", FET J
_The current flows through the FETs J ₂₃ and J ₂₄ regardless of “On” and “Off” of ₆ and J ₇ , and FETs J ₁₆ and J ₁₇ . Therefore, the current flows as R ₁ → J ₂₃ → J ₇ , R ₃ → J ₂₄ → J ₁₈ . Therefore, the outputs Q and / Q are Q = "High", / Q = "Low"
Note that the flip-flop circuit is referred to as "set" or "reset" in this specification.

[0030] Here, FET J _23, the gate voltage of the FET J _23, J ₂₄ to flow a current only in J ₂₄ FET J
It can be obtained by increasing the gate voltage applied to ₅ , J ₆ , J ₁₆ , and J ₁₇ . However, since the flip-flop must be operating even in the reset state, the current signal line C
It has its effect only when S is "High".

When configuring the frequency synthesizer, the current control function of the frequency divider as described above is used for reducing power consumption by the intermittent operation of the frequency synthesizer, and the register reset function (function of resetting the flip-flop) is used. It was used for high-speed phase matching in the initial phase matching of the frequency synthesizer, and the current of the circuit was reduced by realizing both of these functions with a common signal.

Here, the intermittent operation means that the frequency synthesizer is intermittently operated, and the current flows through the frequency synthesizer only when the frequency synthesizer is in operation, and the current is not supplied when the operation is stopped, thereby reducing the current of the frequency synthesizer (low consumption). It is carried out in order to achieve power conversion). In addition, initial phase matching can reduce the time until the phase of the frequency synthesizer locks to the desired value by aligning the initial states of the frequency divider and programmable counter in the frequency synthesizer by resetting. Becomes

[0033]

Since the conventional flip-flop circuit is configured as described above, when the flip-flop starts operating after the reset of the flip-flop is released, the current control line CS becomes "High". If the reset line RS becomes "Low" before the flip-flop starts, the flip-flop starts its operation regardless of the reset state until then, so that the operation of the flip-flop can be surely started from the reset state. It was not possible and measures needed to be avoided. As a measure to avoid this, a method of placing a delay circuit such as an inverter on the reset line RS side and setting the reset line RS to "Low" after a certain period of time when the current control line CS is "High" has been considered. However, even if this delay circuit is provided, due to variations in the operating speed of the current control signal and the reset signal due to the temperature conditions, etc.,
There was a problem that the flip-flop could not be reset surely.

The present invention has been made to solve the above problems, and in a flip-flop circuit having a current control function and a register reset function, the current control of the flip-flop is performed only by the signal terminal for current control. It is an object of the present invention to provide a flip-flop circuit capable of resetting a register and reducing the chip area and simplifying the product by simplifying the register.

[0035]

In the flip-flop circuit according to the present invention, a constant current source for resetting is provided in advance in the flip-flop so that it can be reset regardless of "High" or "Low" of the current control line. The configuration is such that a necessary current is passed. Further, the circuit for supplying the constant current is constituted by a field effect transistor or a resistor. Further, another load resistance is made larger than the load resistance through which the constant current flows, or a level shift diode is provided at the output of the flip-flop.

[0036]

The flip-flop circuit according to the present invention performs a normal flip-flop operation by causing a current larger than the reset current to flow through the load resistor when the current control terminal is "High", and the current control terminal is "Low". At this time, the resetting constant current source causes the current to flow in the load resistance to enter the reset state, so that the reset terminal of the flip-flop is not necessary. Therefore, a delay circuit such as an external inverter is not required, the reset operation is stable, and the circuit can be simplified.

Further, since the circuit for supplying a constant current is constituted by the field effect transistor or the resistor, a bias power source and a terminal for applying the power source are not required separately.

Further, since another load resistance is made larger than the load resistance through which the constant current flows or a level shift diode is provided at the output of the flip-flop, it is possible to avoid the occurrence of offset in the output of the flip-flop. ..

[0039]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of a flip-flop circuit according to an embodiment of the present invention. In the figure, J _{1 to} J ₂₂ , R ₁
~ R ₄ , D ₁ ~ D ₄ , D, / D, T, / T, Q, / Q,
V _DD is exactly the same as the above conventional circuit. J _a , J
_b is a normally-on type FET as a constant current source for register reset, RCS is a common control terminal for simultaneously performing current control of the flip-flop and register reset,
CS (RCS) is a current line control signal line of the flip-flop.

FIG. 2 shows a frequency divider constituted by using the flip-flop shown in FIG. In the figure, IN, OUT
Is exactly the same as the above conventional circuit. Reference numeral 2 is a frequency divider constituted by using the flip-flop shown in FIG.

FIG. 3 shows another embodiment of the present invention.
This is one in which a level shift diode is added in the circuit to adjust the output waveform of the flip-flop in FIG. 1 and the outlet of the output terminal is changed. In FIG. 3, D _a and D _b are newly added level shift diodes.

[0042] In the arrangement the frequency divider as described above, the control terminal RCS is of the flip-flop when the "High" current source _{J 7, J 10, J 11} , J 18, J 21, J 22 current , And the current flowing through the load resistance by J ₇ and J ₁₈ is larger than the constant current flowing through it by J _a and J _b , the frequency divider performs the normal frequency dividing operation and the input signal terminal IN The signal input from is divided by this flip-flop circuit and output from the output terminal OUT.

When the control terminal RCS is "Low", the flip-flop current sources J ₇ , J ₁₀ , J ₁₁ , J ₁₈ ,
Since no current flows in J ₂₁ and J ₂₂ , a constant current source J
Only the current due to _a and J _b flows through the load resistors R ₁ and R ₃ ,
The flip-flop is set to "High", that is, the register composed of the flip-flop is reset.
When the control terminal RCS changes from "High" to "Low",
The frequency divider registers all start resetting when they are completely reset. With respect to the frequency divider, the flip-flop circuit described above makes it possible to operate without problems.

Next, an example of a timing chart in the case where the current control and the reset are performed by the common signal RC and an example of the timing chart in the case where the current control and the reset are not normally performed are shown in FIG.
And shown in FIG.

In FIG. 7, the common signal RC changes from "High" to "Low".
The current control signal CS changes from "High" to "Low"
, The reset signal RS goes from "Low" to "High", and no current flows through the flip-flop, so that the flip-flop stops operating regardless of the clock signal T and the input data D. And the common signal RC changes from "Low" to "Hig
When the current control signal CS changes from "Low" to "High" at "h", the flip-flop starts its operation. At this time, the reset signal RS has a sufficient delay from "High" to "Low". if the referred to as the RS until falls the output Q of the flip-flop by the FET J _23, J ₂₄ in the flip-flop is set to "High". this here is reset. Thus The state of the flip-flop can be forcibly changed, and if the counter is made with this flip-flop, the value of the internal register can be reset.

On the other hand, when the signal delay in the inverter B1 of FIG. 4 is not sufficient as shown in FIG. 8, the common signal R
When C changes from “Low” to “High” and the current control signal CS changes from “Low” to “High” to start the operation of the flip-flop, the delay of the reset signal RS becomes insufficient with respect to CS, Flip-flops may not be able to start operation when they are correctly set to "High".

Therefore, if a small current is made to flow through J ₂₃ and J ₂₃ to the flip-flop irrespective of the current control signal CS in advance (FIG. 1), the CS signal changes from "Low" to "High" and when starting the operation, its initial state is dumped towards state resulting current due FET J _23, J _24, in a state of being set to "High". Therefore, the reset signal line RS and the delay circuit are not required, which simplifies the circuit and stabilizes the operation.

On the other hand, the output waveform of the flip-flop of the frequency divider having the above-described structure is such that if the load resistances R ₁ and R ₂ and R ₃ and R ₄ in the flip-flop have the same resistance values, the resistances are previously set. The output waveform of Q is offset by the amount of the voltage drop caused by the constant current for resetting flowing through R ₁ and R ₃ . Now, the constant current generated by the current sources J _a and J _b is I
_0, the resistance R _1, the voltage amplitude of the R ₃ side resistor R _2,
The voltage amplitude on the R ₄ side is offset by R ₁ · I ₀ and R ₃ · I ₀ .

This does not pose a problem when either one of the outputs Q and / Q is used, but it operates with the voltage difference between the outputs Q and / Q like a differential amplifier in the next stage. This can be a problem when connecting circuits.

To avoid this problem, R ₁ and R ₂ , R
By changing the ratio of the resistance values of ₃ and R ₄ , for example, by setting the currents of the current sources J ₇ , J ₁₈ of the flip-flop as I, the resistance value R ₂ ,
The values of R ₄ are respectively R ₁ · (1+ (I ₀ / I)), R ₃
・ Set to (1+ (I ₀ / I)). Alternatively, in the circuit of FIG. 3, the voltage drops at the level shift diodes D _a and D _b are made equal to the voltage drops R ₁ · I ₀ and R ₃ · I ₀ at the load resistance due to the constant current for resetting, respectively. Measures such as selection can be considered. Then, as a result, the yield and reliability can be improved.

Further, although the reset constant current source is realized by the normally-on type FET in the embodiment of FIG. 1, any form may be adopted as long as it is a circuit configuration to be a constant current source. However, by using the normally-on type FET or resistor shown in FIG. 1, a separate bias power source and a terminal for applying the bias voltage are not required.

In this way, the reset terminal can be removed by previously supplying the current for resetting the register to the flip-flop, and the reset operation can be reliably performed without the risk of causing instability of the reset operation by the delay circuit. Can be done.

In the above embodiment, the flip-flop is constituted by the SCFL (Source Coupled FET Logic) circuit. However, the flip-flop is constituted by the current switching type logic gate and the offset of the output waveform is changed by the level shift diode. You may avoid it by using
The same effect as that of the above embodiment is obtained. Further, the same effect can be expected for other digital circuits that require a current control function and a register reset function.

[0054]

As described above, according to the flip-flop circuit of the present invention, a constant current source for resetting is provided in advance in the flip-flop, and "High" of the current control line is set.
Alternatively, the flip-flop circuit is configured so that the current control function and the register reset function can be performed only by the current control terminal by allowing the current necessary for reset to flow regardless of "Low". Not only can it be used in common, but reset operation can be performed reliably and reliably, and circuits can be simplified and the cost can be reduced.

Further, since the circuit for supplying the constant current is constituted by the field effect transistor or the resistor, the bias power source and the terminal for applying the power source are not required separately.

Further, since another load resistance is made larger than the load resistance through which the constant current flows or a level shift diode is provided at the output of the flip-flop, it is possible to avoid the occurrence of offset in the output of the flip-flop. ..

[Brief description of drawings]

FIG. 1 is a circuit diagram of a flip-flop circuit according to an embodiment of the present invention.

FIG. 2 is a block configuration diagram of a frequency divider configured using a flip-flop circuit according to an embodiment of the present invention.

FIG. 3 is a circuit diagram of a flip-flop circuit having a current control function and a register reset function, and a function of correcting its output waveform according to another embodiment of the present invention.

FIG. 4 is a circuit diagram of a conventional flip-flop circuit.

FIG. 5 is a block diagram of a conventional frequency divider.

FIG. 6 is a circuit diagram of a conventional flip-flop circuit without J ₂₃ and J ₂₄ in FIG.

FIG. 7 is a timing chart when current control and reset are performed by a common signal RC.

FIG. 8 is a timing chart showing an example of a case where current control and reset are performed by a common signal RC, which is not normally performed.

[Explanation of symbols]

J _{1 to} J ₂₄ field effect transistor (FET) J ₇ flip-flop current source J ₁₀ flip-flop current source J ₁₁ flip-flop current source J ₁₈ flip-flop current source J ₂₁ flip-flop current source J ₂₂ flip-flop FET J _a for FET J ₂₄ register reset for current source J ₂₃ registers reset flop, J _b load resistance of the resistor reset the constant current source _{FET R 1 ~R 4 FET D 1} ~D 4 diode D _a, D _b Output waveform correction diode D, / D data input terminal T, / T clock signal input terminal Q, / Q output terminal B ₁ Inverter also functioning as a delay circuit V _DD power supply terminal RC, RCS Current control and register reset common input Terminal RS Reset signal line CS Current signal control signal line of flip-flop IN Frequency division input signal terminal OUT Frequency division output signal Terminal

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] July 8, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0008

[Correction method] Change

[Correction content]

FIG. 5 shows a conventional frequency divider constructed using the flip-flop circuit of FIG. In the figure, 5 is shown in FIG.
, A frequency divider composed of a flip-flop circuit, and B ₁ is an inverter also serving as a delay circuit. Also, RC S the common input terminal of the current control and register reset, IN is divided input signal terminal, OUT is a divided output signal terminal.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] 0029

[Correction method] Change

[Correction content]

(Ii) When RS = "High", FET J
Current flows through FETs J ₂₃ and J ₂₄ regardless of “On” and “Off” of ₅ and J ₆ , and FETs J ₁₆ and J ₁₇ . Therefore, the current flows as R ₁ → J ₂₃ → J ₇ , R ₃ → J ₂₄ → J ₁₈ . Therefore, the outputs Q and / Q are Q = "High", / Q = "Low"
Note that the flip-flop circuit is referred to as "set" or "reset" in this specification.

[Procedure 3]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 4

[Correction method] Change

[Correction content]

[Figure 4]

Claims (5)

[Claims] 1. A flip-flop circuit which is composed of a current switching type logic gate and which performs current control and register reset by a common signal line, wherein a constant current is caused to flow through a required load resistor provided in the flip-flop. A flip-flop circuit having a constant current circuit for performing reset. 2. The flip-flop circuit according to claim 1, wherein the circuit for supplying the constant current is composed of a field effect transistor. 3. The flip-flop circuit according to claim 1, wherein the circuit for supplying the constant current is composed of a resistor. 4. The flip-flop circuit according to claim 1, wherein other load resistances are made larger than the load resistances for flowing the constant current. 5. The flip-flop circuit according to claim 1, further comprising a level shift diode for removing an offset of an output waveform of the flip-flop.