JPH0529889A - Flip-flop circuit - Google Patents

Abstract

PURPOSE:To simplify the configuration by using an external reset signal so as to apply draw control to a current flowing to a load of a drive control section thereby resetting a flip-flop output of an output section and eliminating the need for the production of a reset signal in the inside. CONSTITUTION:The flip-flop is provided with an output section 11 giving a flip-flop output in response to an input signal and a drive control section 12 controlling a flip-flop output of the output section 11 by applying switching operation to a current switching logic circuit with an input signal thereby driving a load. Then a reset section 13 applies lock control to a current flowing to a load of the drive control section 12 with a reset signal given externally to reset the flip-flop output of the output section 11. Thus, it is not required to generate newly a reset signal in the inside and to implement reset processing according to the generated reset signal thereby simplifying the configuration.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip-flop circuit having an ECL (current switching logic) type reset function.

[0002]

2. Description of the Related Art Conventionally, there is a flip-flop (F / F) circuit having a reset function, which is configured as shown in FIG. 3, for example.

In FIG. 3, the F / F circuit mainly comprises an ECL type circuit for switching operation by switching a current path by a differential pair transistor having emitter terminals commonly connected. Specifically, the F / F circuit causes the transistors Q9 to Q12 to perform a switching operation by the clock signal (CK) serving as an input signal and its inverted input signal (/ CK), so that the load resistors R1 to R4 are connected to the transistors Q1 to Q8. The output of the differential pair transistors Q15 and Q16 is controlled by the emitter follower outputs of the transistors Q13 and Q14 driven by the potential of one end of the load resistors R3 and R4.
Type flip-flop outputs Q and / Q are obtained.

On the other hand, when the reset operation is performed, a reset signal is externally applied to the reset signal generating circuit 1 in the F / F circuit, and the reset signal is generated in accordance with the internal reset signal 1 generated by the generating circuit 1. The transistors Q22 and Q23 are rendered conductive, and the reset transistors Q24 and Q25 are rendered conductive in accordance with the internal reset signal 2 generated by the generation circuit 1.
At this time, the high level value of the internal reset signal 2 applied to the base terminal of the transistor Q25 is the clock signal (CK) applied to the base terminal of the transistor Q11.
Since it is set to a value higher than the high level value of, the transistor Q11 becomes non-conductive regardless of the potential of the clock signal.

As a result, the base potential of the transistor Q13 becomes high level, the base potential of the transistor Q14 becomes low level, and the output Q becomes low level and is reset as shown in the timing chart of FIG.

During normal operation, the transistors Q22 to 25 are controlled so as to be non-conductive, and the transistors Q1, Q7, Q10, and Q12 that form a differential pair with these transistors Q22 to Q25 operate. It has no effect.

In such a configuration, in order to ensure that the reset transistors Q22 to Q25 are made non-conductive, the transistors Q1, Q7, Q10, and Q12 which form a differential pair with these transistors Q22 to Q25. It is necessary to apply a low-level potential slightly lower than the low level of the base potential to the base terminals of the reset transistors Q22 to Q25. Similarly, in order to surely make the reset transistors Q22 to Q25 conductive, it is necessary to apply to the base terminal a high level potential that is slightly higher than the high level of the base potentials of the transistors Q1, Q7, Q10, and Q12. is there.

The reset transistor Q22,
Since the collector potential and the emitter potential of Q23 are different from those of the reset transistors Q24 and Q25 during operation, the transistor characteristic of the ECL circuit can be switched in the non-saturated state by the transistor Q2.
2, the high level value and the low level value of the base potential of Q23, that is, the potential of the internal reset signal 1 and the base potential of the transistors Q24 and Q25, that is, the potential of the internal reset signal 2, must be set according to the corresponding transistors. . That is, the internal reset signal 1
And the internal reset signal 2 have different high level values, and the internal reset signal 1 and the internal reset signal 2 also have different low level values.

Therefore, two kinds of internal reset signals 1,
2 is required, and the reset signal generation circuit 1 for generating these signals is required.

[0010]

As described above,
The conventional F / F circuit shown in FIG. 3 requires two types of internal reset signals. The high level value and low level value of these internal reset signals are F /
The original high level value and the low level value inside the F circuit are different, and the high level value and the low level value between the internal reset signals are also different.

For this reason, a circuit for generating these special reset signals is required, and since these two reset signals are required, the circuit configuration becomes complicated and large in size.

Therefore, the present invention has been made in view of the above, and an object of the present invention is to simplify the structure by eliminating the internal generation of the reset signal without impairing the high speed operation. To provide a flip-flop circuit.

[0013]

In order to achieve the above object, the present invention provides an output section for providing a flip-flop output according to an input signal and a load by switching a current switching type logic circuit by the input signal. A drive control unit that controls the flip-flop output of the output unit by driving, and a flip-flop output of the output unit by controlling the current flowing through the load of the drive control unit by a reset signal given from the outside. It is composed of a reset unit for bringing the device into a reset state.

[0014]

In the above structure, according to the present invention, the current flowing through the load of the drive control unit for controlling the flip-flop output is forcibly drawn in synchronization with the reset signal given from the outside to put the flip-flop output in the reset state. I am trying.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the configuration of a flip-flop (F / F) circuit according to an embodiment of the present invention. In the F / F circuit of the embodiment shown in the figure, the reset operation is directly performed by the reset signal given from the outside without generating the reset signal inside the circuit.

In FIG. 1, the F / F circuit drives and controls the output section 11 which gives a T-type flip-flop output (Q, / Q) according to the input signal (CK, / CK). The drive control unit 12 and the reset unit 13 that performs the reset operation, which is a feature of the present invention, are provided.

In FIG. 1, the same reference numerals as those in FIG. 3 have the same functions. Therefore, the output unit 11 in the configuration shown in FIG. 1 has the same configuration as that in FIG. 3, and the drive control unit 12 has the transistor Q in the configuration shown in FIG.
22 to Q25 and the reset signal generation circuit 1 are deleted, and have the same configuration. Therefore, the configuration of the reset unit 13, which characterizes the present invention, will be described below.

The reset section 13 comprises a switch circuit 14 and a current mirror circuit.

The switch circuit 14 receives a reset signal given from the outside and outputs a switching signal for controlling the conduction of a transistor for controlling the conduction of the current of the current mirror circuit. Specifically, when a low-level reset signal for instructing a reset operation is externally applied to the switch circuit 14, the switch circuit 14 is brought into a non-conducting state, and a high-level reset signal is supplied so that normal operation is performed. Switch circuit 14 becomes conductive. In this way, the switch circuit 14
Has a simple operation, the circuit is very simple to construct.

The current mirror circuit whose current is controlled to be conducted by the switch circuit 14 is composed of transistors Q17 to Q21 and a low current source I6. By switching the transistors Q20 and Q21 with the current Ir, the current path through the load resistor R2 connected to the collector terminal of the transistor Q20 and the load resistor R4 connected to the collector terminal of the transistor Q21 is controlled.

In such a circuit configuration, when the reset operation is instructed and the reset signal becomes low level, the switch circuit 14 becomes non-conductive and both transistors Q20 and Q21 become conductive. This allows
The current flowing through the load resistors R2 and R4 is the transistor Q2.
0, drawn as collector current of Q21.

In such a state, the load resistance R2
The current drawn from R4 is adjusted so that the potentials of the connection point 15 at one end of the load resistor R2 and the connection point 16 at one end of the load resistor R4 have a low level slightly lower than the low level potential originally set in the circuit. Set to potential.

When the potentials of the connection points 15 and 16 are set in this manner, the transistors Q2 and Q5 whose base terminals are connected to the connection points 15 are rendered non-conductive, and the base terminals are connected to the connection points 16. Transistors Q4 and Q
6 also becomes non-conductive. As a result, the transistor Q
The base terminals of the transistor Q13 connected to the collector terminals of 5, 5 and one end of the load resistor R3 become high level, and the base terminal of the transistor Q14 becomes low level.

Therefore, regardless of the input signal, the flip-flop output Q becomes low level, the flip-flop output / Q becomes high level, and the F / F circuit is reset. As shown in the timing chart of FIG. 2, such a reset operation is surely executed in synchronization with the reset signal being in the low level state regardless of the state of the flip-flop output.

Therefore, in the F / F circuit as described above, it is not necessary to generate the reset signal inside the circuit unlike the conventional circuit, and the high speed characteristic of the ECL type circuit is not impaired and the FCL circuit is simple. It is possible to realize an F / F circuit capable of performing a reset operation with various circuit configurations.

[0027]

As described above, according to the present invention, the flip-flop output is reset by forcibly drawing in the current flowing through the load of the drive control unit for controlling the flip-flop output by the external reset signal. Therefore, it is not necessary to internally generate a new reset signal and perform the reset process according to the generated reset signal, and the configuration can be simplified.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit configuration of a flip-flop circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a timing chart of the circuit shown in FIG.

FIG. 3 is a diagram showing a circuit configuration of a conventional flip-flop circuit with a reset function.

FIG. 4 is a diagram showing a timing chart of the circuit shown in FIG.

[Explanation of symbols]

1 Reset signal generation circuit 11 Output section 12 Drive controller 13 Reset section 14 switch circuit 15, 16 connection points Q1 to Q25 bipolar transistors R1 to R6 resistance I1 to I6 constant current source

Claims (2)

[Claims] 1. An output section for providing a flip-flop output according to an input signal, and a drive control for controlling a flip-flop output of the output section by switching a current switching type logic circuit by the input signal to drive a load. And a reset unit for bringing a flip-flop output of the output unit into a reset state by controlling a current flowing through a load of the drive control unit by a reset signal given from the outside. circuit. 2. The flip-flop circuit according to claim 1, wherein the reset unit is configured by a current mirror circuit whose conduction is controlled by a reset signal applied from the outside.