JPH0574940A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the time for designing an overall circuit with a diminished clock skew by providing signal lines of the same length and making each wiring delay time equal for transferring a clock signal to each clock operation circuit at each step. CONSTITUTION:An exclusive clock line 2a is connected to a clock driver circuit 4a and flip-flop circuits 5a to 5c in a channel region 1a. As for a second-stage channel region 1b, a clock driver circuits 4b and flip-flop circuits 5d and 5e are provided, but are different in number and at different intervals from the first-step channel region 1a. An exclusive clock line 2b is located in a second- step wiring region 3b and has a wiring length L, which is equal to that of the exclusive signal line 2a. The exclusive signal line 2b are connected to flip- flop circuits 5d and 5e, and to a channel driver circuit 4b, which is connected to a clock driver circuit 4a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit such as a CMOS gate array, and more particularly to a flip-flop,
The present invention relates to a semiconductor integrated circuit in which a clock operating circuit such as a clock driver and a dedicated clock line are arranged and wired.

[0002]

2. Description of the Related Art FIG. 4 shows a concrete example of a conventional semiconductor integrated circuit arranged and wired. In FIG. 4, 1a,
1b is a channel region, 3a and 3b are wiring regions, 2a and 2
Reference numeral b is a dedicated clock line, 4a and 4b are CDs (clock drivers), and 5a to 5f are flip-flops. Figure 4
The circuit is an example in which the channel region and the wiring region are in two stages. In this circuit, the wiring length of the dedicated clock line 2a is A and is connected to the clock driver 4a and the clock operating circuits of the flip-flops 5a and 5b. The wiring length of the dedicated clock line 2b is B and is connected to the clock driver 4b and the clock operating circuits of the flip-flops 5c to 5f.

[0003]

In the conventional arrangement and wiring of the dedicated clock lines and the like in the semiconductor integrated circuit, the clock dedicated line of the first stage is considered in consideration of the wiring position and number of flip-flops and the degree of integration of other elements. The wiring length A differs from the wiring length B of the second-stage clock dedicated line, and the wiring delay from the clock drivers 4a and 4b causes a difference in the wiring delay of the clock signal. Further, the wiring delay increases in proportion to the length of the dedicated clock line and the number of elements in the channel region connected to the second stage. FIG. 5 shows an equivalent circuit in the above-mentioned two-stage circuit. The first-stage circuit supplies a clock signal to the clock operating circuits 52-1 to 52-n via the buffer 50 and the second-stage circuit is supplied. The circuit supplies the clock signal to the clock operating circuits 52-1 to 52-m via the buffer 51, and the number of circuits supplied at each stage is different. As described above, since the wiring lengths of the clock dedicated lines in the two stages are different, variations in the wiring delay of the clock signal occur in each stage, and setup errors and hold errors occur, and the circuit malfunctions. Therefore, when designing a circuit, it is necessary to make the wiring delay of the clock signal the same in all stages to eliminate the clock skew, which requires a considerable design time. Also, when simulating a designed circuit, there is a problem that the number of simulation executions increases because the clock skew is taken into consideration.

The present invention has been made in order to solve the above-mentioned problems, and the wiring delay of the clock signal is made the same in all stages to reduce the clock skew, and the circuit design time can be shortened. An object of the present invention is to provide a semiconductor integrated circuit that can reduce the number of times of simulation of a designed circuit.

[0005]

The semiconductor integrated circuit according to the first aspect of the present invention, as shown in FIG.
a to 1c) and wiring regions (3a to 3c) are alternately arranged in a plurality of stages in a wiring region of a semiconductor integrated circuit, and a clock signal is uniformly supplied to a clock operating circuit such as a flip-flop (FF) or a clock driver (CD). Long clock lines (2a to 2c) are provided. In the semiconductor integrated circuit according to the second invention, as shown in FIG. 3, a dummy cell 6 of a clock operating circuit such as a flip-flop or a clock driver connected to a dedicated clock line 2b is provided in a channel region 1b of a predetermined stage. Was established.

[0006]

In the semiconductor integrated circuit according to the first aspect of the present invention, when the clock signal is supplied from the dedicated clock line to the clock operating circuit such as the flip-flop and the clock driver, the dedicated clock lines of all stages have a uniform length. It is possible to reduce the clock skew by using the same wiring delay in all stages of the clock signal by the dedicated clock line. In the semiconductor integrated circuit according to the second aspect of the present invention, dummy cells of a clock operating circuit such as a flip-flop and a clock driver are provided in a channel region of a predetermined stage, so that clock skews are made equal in wiring delay of clock signals in all stages. To reduce The channel region in which the dummy cell is provided is a channel region of a stage having few circuits such as flip-flops.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic diagram of a semiconductor integrated circuit according to an embodiment of the first invention, and FIG. 2 is a diagram showing in detail the configuration of the circuit of FIG. In FIG. 1, 1a to 1c are channel regions, 3a to 3c are wiring regions, and the channel regions and the wiring regions are alternately arranged in three stages. Reference numerals 2a to 2c are dedicated clock lines, all of which have a uniform length and are provided in parallel with the channel regions 1a to 1c. FIG. 2 shows in detail the circuit of FIG. 1 in which the channel region and the wiring region are alternately arranged in two stages. In FIG. 2, 4a and 4b are shown.
Is a clock driver, and 5a to 5e are flip-flops.

In the first-stage channel region 1a of FIG. 2, a clock driver 4a and flip-flops 5a-5c are provided.
Are provided at different intervals (distances). In the wiring area 3a of the first stage, a dedicated clock line 2a for supplying a clock signal to a flip-flop or the like is provided. The wiring length of the dedicated clock line 2a is L, and the clock driver 4a and the flip-flop 5 in the channel region 1a are included.
a to 5c. Second-stage channel region 1b
Includes a clock driver 4b and a flip-flop 5
d and 5e are provided at a different number and interval from the channel region of the first stage, and the dedicated clock line 2b is provided in the wiring region 3b of the second stage.
Is provided. The dedicated clock line 2b has a wiring length L and a uniform length with the dedicated clock line 2a, and the channel driver 4b and the flip-flop 5 in the channel region 1b.
It is connected to d and 5e. Also clock driver 4
b is connected to the clock driver 4a.

As described above, by making the wiring length of the dedicated clock line in the wiring region of each stage uniform L
The wiring load capacitance is made constant, the clock signal wiring delay is made equal, and the clock skew is reduced.

FIG. 3 is a diagram showing a semiconductor integrated circuit according to an embodiment of the second invention. In FIG. 3, reference numeral 6 is a dummy cell of a clock operating circuit such as a clock driver and a flip-flop. With this dummy cell, the number of flip-flops in the channel region 1b with few flip-flops is set to be the same as that in the channel region 1a, and the wiring load capacitance is made constant to reduce clock skew.

When a circuit is designed by the automatic placement and routing apparatus, the dedicated clock line may be given priority so that it is executed independently of other wirings.

[0012]

As described above, according to the first aspect of the present invention, the clock dedicated line for supplying the clock signal to the clock operating circuit such as the flip-flop and the clock skew has a uniform length. Since it is not necessary to strictly consider the variation and the clock skew in the circuit, it is possible to shorten the circuit design time and reduce the number of simulation executions of the designed circuit. According to the second aspect of the invention, since the variation in the clock signal wiring delay and the clock skew can be adjusted by the dummy cells in the channel region of the predetermined stage, the clock signal wiring delay and the clock skew can be reduced in each stage. There is an effect that can be finely adjusted.

[Brief description of drawings]

FIG. 1 is a schematic diagram of a semiconductor integrated circuit in an embodiment of the first invention.

FIG. 2 is a diagram showing in detail the configuration of the circuit of FIG.

FIG. 3 is a diagram showing a configuration of a semiconductor integrated circuit according to an embodiment of the second invention.

FIG. 4 is a diagram showing a configuration of a conventional semiconductor integrated circuit.

5 is a diagram showing an equivalent circuit of the clock dedicated line peripheral circuit of FIG. 4;

[Explanation of symbols]

 1a to 1c Channel area 2a to 2c Clock dedicated line 3a to 3c Wiring area

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[Procedure amendment]

[Submission date] June 25, 1992

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 5

[Correction method] Change

[Correction content]

[Figure 5]

Claims (2)

[Claims] 1. A plurality of stages of channel regions and wiring regions are alternately arranged in the same direction, and a clock operation circuit such as a flip-flop and a clock driver having a different number and a different place for each channel region are arranged in each stage of the channel regions. In the semiconductor integrated circuit provided with, a dedicated clock line having a uniform length for supplying a clock signal to the clock operating circuit is provided in each wiring region. 2. A semiconductor integrated circuit according to claim 1, wherein dummy cells of a clock operating circuit such as a flip-flop and a clock driver connected to the dedicated clock line are provided in a channel region of a predetermined stage. circuit.