JPH09121022A - Layout designing of integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable layout designing of high speed and high precision by batched generation of layouts even in the case where cell arrays are not regularly arranged in a portion. SOLUTION: A portion where cell arrays are not regularly arranged is extracted from information of arranged cell arrays in accordance with connection strength of signal lines (S2). A pseudo cell is inserted in the extracted portion so that each cell array has a constant length (S3). A block is generated for each cell array having the pseudo cell inserted (S4). It is detected that the blocks thus generated have the same length (S5). Adjustment is made so that the blocks have the same length (S6).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout design method for an integrated circuit, and more particularly to a layout design method for an integrated circuit for laying out regularly arranged arithmetic circuits at a high speed.

[0002]

2. Description of the Related Art As a conventional layout design of an integrated circuit, there is a design method using primitive cells in order to reduce the design man-hour and design time. This design method reduces the design time by grouping regularly arranged arithmetic circuit cells into blocks, performing batch generation processing on the blocks, and deleting redundant layouts in primitive cells. ing.

[0003] Primitive cells are prepared by designing layouts by dividing functions necessary for an integrated circuit into unit functions in advance. An example of the primitive cell having a NAND function will be described with reference to FIGS. FIG. 7 is a circuit diagram thereof, and FIGS. 8A and 8B are layout diagrams thereof. This NAND circuit 24 has an input terminal 2
5, 26 and an output terminal 27.

In FIG. 8A, a primitive cell 28 includes a P-channel diffusion layer 33 and an N-channel diffusion layer 3.
5, a transistor comprising a polysilicon layer wiring 30, an aluminum layer wiring 31, and a diffusion contact 34, which is connected to a ground wiring 29 and a power supply wiring 32, and is connected to input / output terminals 25, 26 and 27 to form other primitive cells. It is configured to be connected to a signal line. The primitive cell 28 is connected to another primitive cell in the horizontal direction as shown in FIG. 8B, so that the ground wiring 29 and the power supply wiring 32 are connected to each other. Such a simple connection results in a redundant portion 36 as shown by the dotted line.

A design method using the primitive cells will be described with reference to a flowchart shown in FIG. First, in step S11, circuit information is input. Next, step S
Based on the circuit information input at 12, each primitive cell 28 is arranged as shown in FIG. The arrangement of the primitive cells is determined by the strength of the connection existing between the primitive cells. For example, when the number of nets connected between two primitive cells is large, the strength of the connection is strong, and when the number is small, the strength of the connection is weak. Those having weak connection strength are arranged apart from each other, and those having strong connection strength are arranged close to each other. The layout design is performed by arranging the primitive cells thus arranged in step S13.

As another conventional integrated circuit designing method, there is a method of generating a new block for each cell column after arranging in the same manner as described above (for example, Katsunori Tani et al., "TWO-DI
MENSIONAL LAYOUT SYNTHESI
S FOR LARGE-SCALE CMOS CI
RCUITS ", PROCEEDINGS OF TH
E 1991 IEEE INTERNATIONAL
CONFERENCE ON COMPUTER-AI
DED DESIGN, November 11-14
1991). In this case, generation of a block indicates that a plurality of primitive cells are collectively redesigned into one block based on transistor circuit information on each primitive cell. In this case, the cell row is the one shown in FIG.
As shown in (b), a plurality of primitive cells 28 are combined to form a column of cells formed by connecting a power supply wiring and a ground wiring.

The second design method will be described with reference to a flowchart shown in FIG. First, in step S21, each primitive, as shown in FIG.
Each primitive determined by the connection strength between cells
The cell arrangement is given, and in the next step S22, a block is generated for each cell column based on the given primitive cell arrangement information. Next, rearrangement is performed in step S23 using each generated block, and finally, in step S2
Wire between the blocks generated in step 4. In this case, if a cell column is generated in one block, each primitive
Since a redundant portion existing in the cell can be reduced, a higher density layout can be designed.

FIG. 11A shows a layout of a cell column designed as described above. The cell columns 1 to 4 are configured by connecting various primitive cells 5 to 9 so as to connect the ground wiring 12 (29) and the power supply wiring 11 (32). These cell columns 1 to 4 have primitives
There will be locations 10 where cells are not regularly arranged.

[0009]

In the conventional layout designing method using the primitive cells described above, the primitive cells are designed in advance. For this reason, there is a disadvantage in the layout of the primitive cell that there is a redundant portion 36 that becomes unnecessary when combined with other primitive cells as shown in FIG. 8B. FIG. 12 shows a state where the redundant portion 36 is deleted. In FIG. 12, when two primitive cells 28 having the NAND function of FIG. 8A are connected, a redundant portion 36 of FIG. 8B is generated. This redundant portion 36 is formed by sharing the diffusion layer of the transistor. This shows that a layout which is deleted and becomes the shared portion 38 is obtained.

In order to solve this problem, a second design method for eliminating a redundant portion by making a cell row into one cell is as follows.
As shown in FIG. 11B, the primitive cell 5
The lengths of the generated blocks differ depending on the combination of the combinations No. to No. 9, and the irregular portion 37 becomes a redundant area, the layout area deteriorates, the length of the generated blocks differs, and the terminal positions between cells are changed. Will deviate from each other.

For example, as shown in FIG. 13A, a path 3 connected to a terminal 40 of each cell 8 between cell rows 1 to 4
Numeral 9 passes over these cells 8 and is wired to connect between terminals 40 of adjacent blocks. Therefore, when the position of the cell 8 shifts, the position of the terminal 40 changes as shown in FIG. Therefore, the path of the path 39 for wiring between the blocks may be bent which did not exist before the combination.

When the path 39 is bent and becomes uneven as described above, the wiring length of the path 39 is increased by the amount of the bent wiring, and the signal transmission time (delay time) is correspondingly increased.
Becomes longer, the operation speed of the data path to be created becomes slower, and its performance deteriorates.

An object of the present invention is to solve these problems,
It is an object of the present invention to provide a layout design method for an integrated circuit that enables a higher-density layout design, eliminates a difference in transmission speed between blocks, and enables high-speed operation.

[0014]

According to the present invention, there is provided an integrated circuit in which cells of elements including arithmetic circuits arranged regularly are grouped into blocks, and the blocks are subjected to collective generation processing to adjust each block. In the layout design method of
A step of extracting locations that are not regularly arranged in the information of the cell rows arranged according to the connection strength of the signal lines, and that the length of each cell row is constant with respect to the extracted locations. Inserting a pseudo cell into a cell, generating a block for each cell row with respect to the arrangement information in which the pseudo cell is inserted, and detecting that the generated block has the same length. And a step of adjusting each block to have the same length.

Further, in the configuration of the present invention, a step of extracting a part which is not regularly arranged in the information of the cell string arranged according to the connection strength of the signal line, and the step of extracting the cell string at the extracted part. Dividing, and generating a block for each of the divided cell columns based on the divided arrangement information, and setting a block interval between the divided cell columns so that the generated blocks have the same length. Adjusting step may be included.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a flow chart for explaining an embodiment of the layout designing method of the present invention. In this layout design method, as in the conventional example, the cells of the elements are grouped into blocks, and the blocks are subjected to collective generation processing to adjust each block. The state of the cell row where the primitive cells are arranged Is shown in FIG. FIG. 2 shows a layout diagram when the layout design method of this embodiment is applied to this primitive cell column.
In the present embodiment, a pseudo cell 13 is inserted at a location 10 where the primitive cells in FIG. 11A are not regularly arranged.

That is, in this embodiment, the cell columns 1 to 4
Is constructed by connecting the various primitive cells 5 to 9 and the pseudo cell 13 so as to connect the ground wiring 12 and the power supply wiring 11, respectively. The block configuration of the cell row thus configured is as shown in FIG. The cell rows 1 to 4 have a uniform length.

By inserting such a pseudo cell 37, each of the primitive cells 5 to 9 has the same configuration as before the block generation. Since the wiring of the path connects the terminals of the block, the terminal position does not relatively change if the configuration of the primitive cell is the same. As described above, if the terminal positions before and after the block generation are the same, no extra bend occurs in the path between them.

A layout design method for such an integrated circuit will be described with reference to FIG. First, in step S1, the primitive cell arrangement information determined by the connection strength as shown in FIG. 11 is input. Next, in order to insert the pseudo cell 13 shown in FIG. 2, a portion where the primitive cells 5 to 9 are not regularly arranged is extracted in step S2. The fact that the cells are not arranged regularly means that the primitive cells 5 to 9 in the cell columns 1 to 4
Are not connected (for example, cell columns 2 and 4 in FIG. 5).
Between primitive cells 5 and 7).
If the cell rows 2 and 4 are generated in one block without any change, if the places where the primitive cells are not regularly arranged are reduced, the length of the generated blocks may vary as shown in FIG. 11B. become.

Next, in step S3, the generated blocks are all of the same length at locations that are not regularly arranged (between primitive cells 5 and 7 in cell rows 2 and 4). The pseudo cell 13 is inserted into the cell array to generate arrangement information having a uniform cell column length as shown in FIG. Next, in step S4, a block is generated as a new block for the cell columns 2 and 4 in which the pseudo cells 13 are inserted.
Further, in step S5, it is extracted whether or not the generated blocks have the same length. As a result, if the lengths of the generated blocks are not equal, the pseudo cell 1 in step S3
Returning to the process of inserting 3, the amount of insertion of the pseudo cell 13 is adjusted, steps S <b> 3 to S <b> 5 are repeated, and the length of the block is adjusted to be equal. The insertion amount of the pseudo cell 13 is reduced when the block length is longer than the cell row in which the pseudo cell 13 is not inserted, and is increased when the block length is short.

The layout shown in FIG. 3 obtained in this manner has no redundant portion included in each primitive cell and can be designed to have the same length of each block.

Next, a second embodiment of the present invention will be described.
This will be described with reference to the flowchart shown in FIG. First, in step S1, the primitive cell arrangement information determined by the connection strength as shown in FIG. 11 is input. Next, as shown in FIG. 5, in order to divide the cell row, in step S2, a place where the primitive cells are not regularly arranged is extracted. The extraction of the locations that are not regularly arranged is repeatedly performed for each cell column. The primitive cells are examined in order from the primitive cell at the end of the cell row, and a portion where the primitive cell is not connected to another primitive cell is extracted.

Referring to FIG. 11, when the cell column 2 is examined in order from the primitive cell 5, the primitive cell 5 is not connected to another primitive cell, and thus the primitive cell 5 A location 10 between the next primitive cell 7 and the next primitive cell 7 is not regularly arranged. Extraction of this irregularly arranged portion is such that when the primitive cell is examined up to the primitive cell at the opposite end of the cell column, the processing for that cell column ends, and then the extraction has not been performed yet Process cell columns.
In the next step S3A, the cell rows are grouped in units of locations that are not regularly arranged and divided into cell groups 15, 18 and 19. Here, the primitives obtained by dividing the cell row
The soul of the cell is the cell group.

In the next step S4A, a single block is generated in units of the divided cell groups 15, 16, 18, and 19. When the divided cell group becomes a single primitive cell, block generation is not performed on the cell group. In FIG. 5, the cell groups 15 and 16 are divided at locations 10 where one cell row 2 is not regularly arranged. Since the divided cell group 15 is a single primitive cell, no new block is generated as the cell group 15.

Then, in step S6, the generated block is rearranged. This will be described with reference to the example shown in FIG. 6. The intervals between the primitive cells 5 and the blocks 21 are adjusted to the blocks 20 or 22 so that the lengths of all the cell columns are equal. Thus, pseudo cell 1
3 can be inserted and the length of each block can be made equal without eliminating redundant portions in primitive cells without repeating the adjustment. In the last step S7, wiring is performed between the arranged blocks.

As described above, by adjusting the interval between the portions where no cells exist, the positions of the terminals (40) existing in the block can be aligned, and the terminals 40 between the paths 39 are aligned. Therefore, no extra bending occurs in the path between them.

[0027]

As described above, the present invention adds a block generation process to a layout design method using primitive cells, and reduces redundant layout portions in primitive cells to achieve higher density. In addition to designing a simple layout, by inserting pseudo cells and dividing and generating pseudo cells in places where primitive cells are not regularly arranged, the length of each generated block can be made the same,
Since there is no difference between the transmission speeds of the signals propagating in the respective blocks, there is an effect that a layout capable of high-speed operation can be designed without extra delay.

Further, according to the present invention, it is possible to suppress the bending of the path generated by performing the block generation, thereby shortening the signal transmission time. Performance can be satisfied.

[Brief description of the drawings]

FIG. 1 is a flowchart explaining a first embodiment of the present invention.

FIG. 2 shows a layout design method according to the present embodiment;
FIG. 11 is a layout diagram in which block generation is performed in the case of FIG.

FIG. 3 is a layout diagram in which blocks are generated for a cell column of the layout of FIG. 2;

FIG. 4 is a flow chart illustrating a second embodiment of the present invention.

FIG. 5 is a layout diagram in which a cell row is divided into cell groups at locations that are not regularly arranged in the case of FIG. 13 according to the second embodiment.

FIG. 6 is a layout diagram in which the length of each cell row is arranged equally by adjusting the generated block intervals of FIG. 5;

FIG. 7 is a circuit diagram of an example of a general NAND circuit.

8 is an example of a primitive cell of the NAND circuit shown in FIG. 7, and a layout diagram when the primitive cells are combined;

FIG. 9 is a flowchart illustrating a conventional layout design method using primitive cells.

FIG. 10 is a flowchart illustrating a conventional layout design method for generating a cell column into one cell.

FIG. 11 is a layout diagram of a cell column in which primitive cells are arranged and a cell column in which blocks are generated for this cell column.

FIG. 12 is a layout diagram in which a redundant portion is eliminated in a cell column in which two primitive cells are combined.

FIG. 13 is a layout diagram illustrating a state of a path before block generation and after a block generation.

[Explanation of symbols]

 1-4 Cell row 5-9 Primitive cell 10 Location without regular wiring 11, 32 Power supply wiring 12, 29 Ground (ground) wiring 13 Pseudo cell 14 Cell row after division 15-19 Split cell row 20-23 Generated block 24 NAND circuit 25, 26 Input terminal 27 Output terminal 28 Primitive cell layout unit 30 Polysilicon layer wiring 31 Aluminum layer wiring 33 P channel diffusion layer 34 Diffusion contact 35 N channel diffusion layer 36 Primitive cell redundant part 37 cell Irregular part 38 Diffusion sharing part 39 Pass 40 terminal

Claims (2)

[Claims] 1. An integrated circuit layout design method in which cells of elements including operation circuits arranged regularly are grouped into blocks, and the blocks are subjected to collective generation processing to adjust each block. A step of extracting a part that is not regularly arranged in the information of the cell string arranged according to the strength, and a pseudo cell is formed so that the length of each cell string is constant with respect to the extracted part. Inserting, and performing a block generation for each cell column for the placement information in which the pseudo cell is inserted, and detecting that the generated block has the same length,
Adjusting the blocks so that the blocks have the same length. 2. A layout design method for an integrated circuit in which cells of elements including arithmetic circuits arranged regularly are grouped into blocks, and the blocks are subjected to collective generation processing to adjust each block. A step of extracting a part that is not regularly arranged in the information of the cell rows arranged by the intensity, a step of dividing the cell string at the extracted part, and a step of extracting the divided arrangement information. A layout design method for an integrated circuit, comprising: generating a block for each divided cell column; and adjusting a block interval between the divided cell columns so that the generated blocks have the same length.