JPH11272729A - Layout design method for lsi - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a layout design method for LSI which minimizes influences of characteristic degradation and area increase due to scan path design. SOLUTION: This layout design method for LSI uses scan paths and is provided with an arrangement position determination processing stage 2 where relative arrangement position information of cells is generated based on circuit connection information 7 having no scan connections, a scan path connection stage 3 where circuit information 11 after scan connection is generated based on relative arrangement position information 8 of cells, and an arrangement direction determination stage 4 where arrangement directions are determined based on circuit information 11 after scan connection and relative arrangement position information 8 of cells without changing relative positions of cells determined in the arrangement position determination stage 2 to generate final arrangement position information 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI layout design method using a computer or the like, and relates to a method for connecting a plurality of scan paths F / F included in a logic circuit inside an LSI to one or a plurality of scan paths. The present invention relates to an LSI layout design method employing a campus connection method.

[0002]

2. Description of the Related Art Conventionally, a layout design of an LSI using a computer includes a step of deciding the arrangement of macrocells by an arranging means so as to minimize the area and the wiring length based on input circuit connection information; From the connection information and the circuit connection information determined by the above.

On the other hand, an increase in the circuit scale of an LSI requires a testability design technique for facilitating test and diagnosis of a logic circuit, and a scan path design technique has emerged as one of the techniques.

In LSI design using a scan path design technique, scan path connection is performed before a placement step or between a placement step and a wiring step.

[0005]

The scan path design method is characterized in that a plurality of scan F / Fs are connected in a daisy chain by a single or a plurality of chains.
It can be realized by SI. However, if the scan F / F is connected without considering the actual arrangement and wiring of the macro cells, an increase in the LSI area due to the congestion of the wiring and a wiring delay due to the connection of the scan F / F may cause a problem. This can be a source of LSI malfunction.

For example, when the circuit connection information that has completed the connection of the scan path is input to the arranging means, the arranging means finally determines the macro cell arrangement so as to optimize all the wirings including the scan path. When the wiring is completed, the delay of the original signal line may be increased due to the scan path.

Further, when scan paths are connected based on the macro cell arrangement after the macro cell arrangement is determined, the wiring area does not take into account the scan path wiring. There is.

An object of the present invention is to solve such a conventional problem, and an object of the present invention is to provide a layout design method of an LSI which minimizes the influence of characteristic deterioration and area increase due to scan path design.

[0009]

According to the present invention, an LSI layout design includes an arrangement step and a wiring step. Further, the inside of the arranging step is a step of determining the relative position of the macro cell based on the connection information of the circuit, and further arranging each macro cell again based on the peripheral connection information from the determined relative position. It comprises a step of determining a direction.

The present invention according to claim 1 is an LSI layout design method using a scan path, and a layout position determining process for generating relative layout position information of cells based on circuit connection information having no scan connection. A scan path connecting step of generating scan-connected circuit information based on the relative arrangement position information of the cell; and determining the arrangement position based on the scan-connected circuit information and the relative arrangement position information of the cell. An arrangement direction determining step of determining an arrangement direction and generating final arrangement position information without changing a relative position between cells determined in the step.
I is a layout design method.

According to the LSI layout design method of the present invention, the relative arrangement position is determined in the arrangement position determining step without being affected by the scan path connection. Further, since the placement direction is determined and the final placement position information is generated without changing the relative position between the cells determined in the placement position determination step in the placement direction determination step, the entire wiring including the scan path connection is determined. Optimization can be performed.

[0012]

Next, an embodiment of the present invention will be described.

FIG. 1 shows an LSI according to an embodiment of the present invention.
9 is a flowchart showing a layout design method of FIG. This method includes a replacement step 1 for a scan FF, an arrangement position determination step 2, a scan path connection step 3, an arrangement direction determination step 4, and a wiring step 5.

By inputting the circuit connection information 6 to the scan FF replacement step 1, the circuit connection information 7 based on the scan FF is obtained.
Is obtained. However, in the circuit connection information 7, the scan input pin of the scan FF is not connected.

By inputting the circuit connection information 7 to the layout position determining step 2, macro cell layout position information (relative layout position information) 8 is obtained.

By inputting circuit connection information 7, macro cell arrangement position information 8, and scan path connection constraint information 9 to scan path connection step 3, circuit connection information 11 after scan path connection can be obtained.

In the placement direction determining step 4, the circuit connection information 11 is added to the placement position information 8 of the macro cell, and only the placement direction of the macro cell is optimized without changing the relative placement position of the macro cell. By inputting the resulting placement information (final placement position information) 12 and circuit connection information 11 to the wiring step 5, layout data 13 in which placement and wiring have been completed can be obtained.

FIG. 2 is a schematic diagram of the output of the arrangement position determination step 2. Reference numerals 14 and 15 denote cell columns, and 16 to 21 are scan FFs. At this point, the scan input terminals DT (22 to 27) of the scan FFs (16 to 21) are not connected.

FIG. 3 is a schematic diagram of the output of the scan path connection step 3 and shows a scan path connection image. In the present embodiment, in the scan path connecting step 3, the scan FF is performed by sequentially scanning the cell rows.
To create connection information. That is, scan FFs 28 to 31 and scan FF 3 arranged in the same cell row
2, 33 are connected as the same scan chain. The scan path connection constraint 9 has the maximum
The number of FFs, the name of the clock signal, and the like are described, and the scan is performed while sequentially scanning the cell row and confirming the number of FFs on the chain and the driven clock. In FIG. 3, the scan FFs 28, 29, and 32 exist in the same cell column, but since the driving clocks are different,
Another chain.

FIG. 4 is an output diagram of the wiring step 5, which also serves as a schematic view of the scan wiring after the arrangement is changed in the arrangement direction determining step 4. In the example of FIG. 4, the scan FFs 34 to 39 show a case where there is no influence of the wiring other than the scan path connection and the influence of the scan wiring is large. When the wiring is performed without executing the arrangement direction determining step 4, the wiring result is the same as that shown in FIG. When FIG. 3 and FIG. 4 are compared, it is apparent that the congestion of the wiring is alleviated. In FIG. 4, since the placement direction is determined in consideration of the entire wiring, paying attention to the positions of the pins DT and Q of the scan FF, the placement direction of the scan FFs 34 to 39 is changed from the placement direction of FIG. I understand.

[0021]

As described above, in the layout design method of the present invention, the final layout position information is generated based on the circuit information after the scan path connection, so that the optimum wiring can be realized. Is obtained.

[Brief description of the drawings]

FIG. 1 is a flowchart showing an LSI layout design method according to an embodiment of the present invention;

FIG. 2 is an output schematic diagram of an arrangement position determination step 2;

FIG. 3 is an output schematic diagram of a scan path connection step 3;

FIG. 4 is a schematic diagram of a final layout after wiring.

[Explanation of symbols]

 1 Scan FF Replacement Step 2 Arrangement Position Determination Step 3 Scan Path Connection Step 4 Arrangement Direction Determination Step 5 Wiring Step 6 Circuit Connection Information 7 Circuit Connection Information Using Scan FF 8 Arrangement Position Information 9 Scan Path Connection Constraints 11 Scan Path Connection Subsequent circuit connection information 12 Layout information 13 Layout data 14, 15 Cell column 16-21 Scan FF 22-27 Scan input pin 28-33 Scan FF 34-39 Scan FF

Claims (1)

[Claims] 1. An LSI layout design method using a scan path, comprising: an arrangement position determination processing step of generating relative arrangement position information of cells based on circuit connection information having no scan connection; A scan path connecting step of generating scan-connected circuit information based on the arrangement position information; and a scan path connection step of generating the scan-connected circuit information based on the scan-connected circuit information and the relative arrangement position information of the cells. A layout direction determining step of determining a layout direction and generating final layout position information without changing a relative position.