JP3982927B2 - Scan chain design system and design method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a scan chain (scan path) design system and a design method thereof in an easily testable semiconductor integrated circuit.
[0002]
[Prior art]
Since an operation test after manufacturing a large-scale semiconductor integrated circuit requires a lot of time, for example, test wiring is incorporated in the integrated circuit layout design stage so that the subsequent operation test can be easily performed. . Such a semiconductor integrated circuit is called a test easy semiconductor integrated circuit.
[0003]
2. Description of the Related Art A scan-type testability semiconductor integrated circuit has many scan flip-flops of the type that share a system clock terminal with a scan clock terminal for testing (sometimes abbreviated as scan FF in this specification). include. The system clock signal is distributed so as to be suitable for the operation of the actual circuit (operation when not scanning). Therefore, the scan clock signal depends on the configuration of the system clock signal. If there is one system clock signal, there is also one scan clock signal, but usually there are a plurality of system clock signals.
[0004]
Many of the scan FFs included in the testability semiconductor integrated circuit are cascaded in at least one scan chain and arranged between the scan-in terminal and the scan-out terminal, and each scan clock terminal has a test Sometimes a scan clock signal is supplied.
[0005]
In general, it is desirable to make the scan chain length as short as possible to reduce unnecessary wiring. In addition, the plurality of scan FFs to which the scan clock signal is supplied through the scan clock signal supply buffer have a distance between the scan clock terminal and the scan clock signal supply source so as not to cause clock skew. The scan clock signals are designed to be transmitted at almost the same timing. When designing a scan chain, it is necessary to take care not to cause this clock skew.
[0006]
An example of clock skew generation will be described with reference to FIGS. FIG. 9 shows scans at different timings due to a long arrangement distance between the FFs in the scan FFs FF1 and FF2 which are continuous on the scan chain from the scan-in terminal SI to the scan-out terminal SO, or due to buffer interposition. An example of the clock skew generated when the clock signal CLK arrives is shown. What is expected of the signal at the scan-out terminal SO of the scan FF2 is a signal delayed by one cycle from the signal at the scan-out terminal SO of the scan FF1.
[0007]
FIG. 10 shows an example of clock skew that occurs when scan FFs, FF1, FF2, and FF3 that are continuous on the scan chain are mixed with those that receive scan clock signals at different timings. As described above, if scan FFs having different scan clock signals are irregularly included in the scan chain, the signal at the scan-out terminal SO of each scan FF cannot be predicted at all.
[0008]
An example of the prior art aimed at minimizing the total length of a plurality of scan chains (scan paths) is proposed in Japanese Patent Laid-Open No. 9-305642. In this prior art, in order to minimize the length of each scan chain, in the process of determining and improving the connection order of nodes including scan FFs, scan-in terminals, and scan-out terminals, a known method for solving a traveling salesman problem, etc. It describes that the algorithm can be used. Note that there is no description about the optimum design of the scan chain that avoids the occurrence of the clock skew.
[0009]
[Problems to be solved by the invention]
The use of the above algorithm, which determines and improves the connection order of scan FFs to minimize the length of the scan chain, is a process of evaluating the chain length by switching the connection order of the scan FFs if strictly attempted. It needs to be repeated. This increases the processing time as the number of scan FFs increases, and is not practical in a circuit having tens of thousands of scan FFs.
[0010]
Further, if only the minimization of the scan chain length is promoted, the scan chain is formed so that the scan FFs that receive the scan clock signal from the clock signal supply sources having different timings are connected (chained), and clock skew occurs. Cause.
[0011]
The problem of the present invention is that the optimum connection of the scan chain, that is, the minimization of the scan chain length, can be processed in practical time, and the occurrence of clock skew can be avoided even when the scan clock signal supply sources at different timings are included. An object of the present invention is to provide a compatible scan chain design system and design method therefor.
[0012]
[Means for Solving the Problems]
In order to solve the above-described problem, the scan chain design method of the present invention includes a first step of grouping a plurality of scan flip-flops having the same supply source of the scan clock signal into at least one group as a unit;
A second step for inter-group connection that determines a connection state of the groups including the plurality of scan flip-flops grouped in the first step so as to shorten a scan chain length;
The intra-group connection determining the connection state for cascading the plurality of scan flip-flops included in each group in which the connection state between the groups is determined by the second step so that the scan chain length is shortened. And a third step.
[0013]
The scan chain design system according to the present invention includes grouping means for grouping a plurality of scan flip-flops having the same supply source of the scan clock signal into at least one group as a unit;
Inter-group connection means for determining a connection state of the groups including the plurality of scan flip-flops grouped by the grouping means so that a scan chain length is shortened;
Intra-group connection means for determining a connection state for cascading the plurality of scan flip-flops included in each group in which the connection state between groups is determined by the inter-group connection means so as to shorten the scan chain length With.
[0014]
In this system, when the scan clock signal is supplied to each of the units of the plurality of scan flip-flops to be grouped through a multi-stage buffer, the grouping means makes the supply source of the scan clock signal the same. It is possible to adopt a configuration in which a first level group that is grouped in units of scan flip-flops and a second level group that groups a plurality of the first level groups into one can be adopted.
[0015]
Further, when the multi-stage buffer configuration is adopted for supplying the scan clock signal, the grouping means receives an instruction to select the multi-stage buffer for grouping the plurality of scan flip-flops as a unit, and at least the first stage Form a one-level group.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings.
Referring to FIG. 1 showing the configuration of a scan chain design system according to an embodiment of the present invention and FIG. 2 showing a scan chain design processing procedure, in this scan chain design system 1, a scan chain optimum connection device 2 is a scan flip-flop. (Scan FF) grouping unit 201, inter-group optimum connection unit 202, and intra-group scan FF optimum connection unit 203.
[0017]
The scan chain optimum connection device 2 determines how to connect the test-dedicated wiring. In particular, scan chain length minimization can be processed in practical time, and the generation of clock skew can be avoided even when scan clock signal sources with different timings are included, enabling the optimal connection of the scan chain. To do.
[0018]
In this design system 1, the input device 3, the placement device 4, the wiring device 5, and the output device 6 perform the layout of the entire integrated circuit including test-dedicated wiring.
The input device 3 inputs circuit information including connection information between the scan clock terminal (ck) of the scan FF and the scan clock signal supply source (including external terminals, buffers, oscillation circuits, etc.) (processing step S1 in FIG. 2). ). This circuit information is created based on the net list by a preprocessing program or the like and stored in advance in a file.
[0019]
The arrangement device 4 determines the arrangement position (coordinates on the substrate) of the scan FF and the scan clock signal supply source, and registers the arrangement position in the file as arrangement information (steps S2 and S3).
[0020]
Further, the wiring device 5 performs the scan chain wiring in accordance with the connection order of the scan FFs obtained by the scan chain optimum connection device 2 described in detail later (step S7). The output device 6 outputs layout information including the optimally connected scan chain (step S8).
[0021]
The scan chain optimum connection device 2 will be described in detail. The scan FF grouping unit 201 reads the arrangement information from the file, groups the scan FFs having scan clock terminals connected to the same scan clock signal supply source, and registers them in the memory. (Step S4).
[0022]
Here, referring to FIG. 3 showing the configuration of scan FF grouping in the scan FF grouping unit 201, scan FFs that receive scan clock signals from the same scan clock signal supply source are in the same group. Further, when the supplied scan clock signal is transmitted to the scan FF through the multi-stage buffer, it is possible to perform multi-stage grouping.
[0023]
In the illustrated example, scan FFs that receive a scan clock signal from a scan clock signal supply source (external terminal) CLK1 are grouped into a group (Group) 1. A scan FF of group 2 is connected to a scan clock signal supply source (external terminal) CLK2 having a timing different from that of the scan clock signal supply source CLK1. Groups 1 and 2 surrounded by a thick circle are each a level 0 group, and each group includes a plurality of level 1 groups surrounded by a thin circle.
[0024]
A plurality of scan FFs and buffers are arranged in groups 11, 12, 13, and 14 included in group 1 and groups 21, 22, and 23 included in group 2, respectively. Since each scan FF is supplied with a scan clock signal from the scan clock signal supply source CLK1 or CLK2 through a two-stage buffer, a multi-stage grouping configuration of levels 0 and 1 is adopted.
[0025]
Next, referring to FIG. 4 showing another configuration of grouping of scan FFs in the scan FF grouping unit 201, in this example, the designer instructs the buffer buff2 and buff3 to form a group with the previous scan FFs. Shows the grouping when For the scan FF group that receives the scan clock signal from the external terminal CLK2, a group 24 having the buffer buff2 as a scan clock signal supply source and a group 25 having the buffer buff3 as a scan clock signal supply source are configured.
[0026]
These buffers buff2 and 3 do not constitute a group of buffers buff1 that is one stage before. The grouping rule of the group 15 using the external terminal CLK1 and the buffer buff4 as the scan clock signal supply source is the same as the example shown in FIG. The groups 15, 24, and 25 may constitute a level 1 group, and the groups 24 and 25 may further constitute a level 0 group.
[0027]
Even if the scan FF groups that transmit clock signals from the external terminals of the scan clock signal at the same timing do not depend on each other in the operation of the actual circuit (operation when not in the test), the system clock signal Timing adjustment is performed separately by a timing adjustment buffer (not shown) arranged in the clock signal supply path. That is, the timing is not necessarily the same as the scan clock signal input to the scan FF. Therefore, the occurrence of clock skew can be avoided by making such scan FF groups separate groups.
[0028]
FIG. 5 shows a specific arrangement example of the scan FFs registered in one group by the above-described processing in the scan FF grouping unit 201. Here, the scan FF groups 51, 52, 53, and 54 form a level 1 group, and receive the scan clock signal from the external terminal CLK through the buffer buff50.
[0029]
By enabling connection of scan chains in units of grouped scan FFs in this way, it is possible to design a scan chain in consideration of avoiding clock skew.
[0030]
The inter-group optimum connection unit 202 of the scan chain optimum connection device 2 obtains representative arrangement coordinates in each group, and determines the optimum connection order between the groups based on the coordinates (step S5). Based on the arrangement example of the scan FFs shown in FIG. 5, the arrangement position of the buffer buff 50 that is the source of the scan clock signal is the central coordinate of this group. The inter-group optimal connection unit 202 determines the connection state so that the length of the chain in which the groups are connected in a daisy chain is shortened based on the central coordinates.
[0031]
As can be understood from the grouping configuration diagram of the scan FFs shown in FIG. 3, the scan FFs belonging to the same group can be expected to be arranged at positions close to each other. Therefore, the scan chain length is shortened by the optimum connection between the groups.
[0032]
FIGS. 6 and 7 show examples in which the connection order of the scan FF groups is optimal (that is, when the total length of the scan chain is shorter) and in the case where it is not optimal. In each figure, SI0 and SI1 indicate scan chain signal input terminals (scan-in terminals), and SO0 and SO1 indicate scan chain signal output terminals (scan-out terminals). Here, each group corresponds to a level 1 group, and each group receives a scan clock signal from a scan clock signal supply source that depends on the design of the supply path of the system clock signal.
[0033]
The intra-group scan FF optimum connection unit 203 determines the optimum connection order of the scan FFs registered as one group from the arrangement coordinates of each scan FF (step S6). FIG. 8 shows a connection example of scan chains corresponding to the arrangement example of the scan FFs registered in one group shown in FIG.
[0034]
In scan chain connection, the connection order of scan FFs is determined within the group, so there is no mix of scan FFs that receive scan clock signals from scan clock signal sources at different timings, avoiding clock skew. it can. In addition, since the chain length is evaluated only for the scan FFs in the group when determining the connection order of the scan FFs, processing can be performed in a shorter time than for all the scan FFs in the chain.
[0035]
【The invention's effect】
As described above, according to the present invention, the scan FFs having the same scan clock supply source are grouped, and the chain connection state between the groups and the chain connection state of the scan FFs in the group are set. The scan chain can be optimally connected without the occurrence of skew, and the processing time can be shortened compared with the case where no grouping is performed.
[Brief description of the drawings]
FIG. 1 shows a configuration of a scan chain design system according to an embodiment of the present invention.
2 shows a scan chain design processing procedure in the system of FIG.
FIG. 3 shows an example of grouping of scan FFs.
FIG. 4 shows another example of grouping of scan FFs.
FIG. 5 shows a specific arrangement example of scan FFs registered in one group.
FIG. 6 shows an example when the connection order between groups is optimal.
FIG. 7 shows an example when the connection order between groups is not optimal.
FIG. 8 shows an example of scan chain connection of scan FFs in one group.
FIG. 9 shows an example of clock skew generation.
FIG. 10 shows another example of clock skew generation.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Scan chain design system 2 Scan chain optimal connection apparatus 3 Input apparatus 4 Placement apparatus 5 Wiring apparatus 6 Output apparatus 201 Scan FF grouping part 202 Inter-group optimal connection part 203 Intra-group scan FF optimal connection part CLK, CLK1, CLK2 Scan clock Signal source external terminals buff2, buff3, buff4, buff50 Scan clock signal source buffers SI, SI0, SI1 Scan-in terminals SO, SO0, SO1 Scan-out terminals

Claims (4)

Scan chain optimal connection device, based on the connection information of the circuit design data, and registers the respective group multiple scan flip-flop with at least one group as a unit to the same supply source of the scan clock signal to the memory A first step;
Based on the arrangement information of the circuit design data, a representative position of each group grouped by the first step defined as source of position of the scan clock signal, the scan chain length when cascading representative position between A second step for inter-group connection that establishes a connection state such that
For intra-group connection for determining a connection state for cascading a plurality of scan flip-flops included in each group whose connection state between groups is determined by the second step so that the scan chain length is shortened A third step;
A scan chain design method characterized by executing: Based on the connection information of the circuit design data, and grouping means for each grouping a plurality of scan flip-flop with at least one group as a unit to the same supply source of the scan clock signal,
Based on the arrangement information of the circuit design data, determines the representative position of each group grouped by the grouping unit and the arrangement position of the source of the scan clock signal, the scan chain length when cascading representative position between An inter-group connection means for determining a connection state so as to be short;
Intra-group connection means for determining a connection state for cascading a plurality of scan flip-flops included in each group in which the connection state between groups is determined by the inter-group connection means, so as to shorten the scan chain length;
A scan chain design system characterized by comprising:   The grouping means forms scan flip-flops connected to each buffer as a lower group when the scan clock signal is supplied through a plurality of buffers in a plurality of stages within the group. The described scan chain design system. The grouping means receives a buffer selection instruction when there is an instruction, and forms a first level group that groups at least the scan flip-flops having the same supply source of the scan clock signal. The scan chain design system according to claim 3.

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