JPH0574221B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing an insulated gate field effect semiconductor device using a non-single crystal semiconductor layer on a substrate having an insulating surface.

In the present invention, the non-single crystal semiconductor layer is deposited on the substrate having the insulating surface by a deposition method such as plasma CVD, and the characteristics of this non-single crystal semiconductor layer are utilized.

That is, the present invention relates to a method for manufacturing an insulated gate field effect semiconductor device which has extremely superior stability of characteristics compared to conventional insulated gate field effect semiconductors.

The present invention also relates to a method for manufacturing an insulated gate field effect semiconductor device that is extremely easy to manufacture.

In this specification, the non-single crystal semiconductor layer is
Includes amorphous silicon semiconductors, crystalline silicon semiconductors with lattice strain, and polycrystalline silicon semiconductors. Further, in this specification, the non-single crystal semiconductor layer also includes a semi-amorphous silicon semiconductor included in the amorphous silicon semiconductor.

Regarding the semi-amorphous silicon semiconductor, Japanese Patent Application No. 55-26388 (filing date: March 3, 1980, semi-amorphous silicon semiconductor) and Japanese Patent Application No. 58863 (1982) filed earlier by the present applicant. Filing date
May 14, 1974, Semiconductor Device Manufacturing Methods), each of which is described in detail.

That is, a suitable semi-amorphous silicon semiconductor used in the present invention, for example a silicon semiconductor without single crystallinity, is an insulating substrate such as a glass substrate or a ceramic substrate such as polycrystalline alumina. formed on the surface.

The semi-amorphous silicon semiconductor formed on the surface of this insulating substrate is AM1 (100 [mW/cm ² ])
Even when applying light energy of 1×
An electro-optical conductivity of 10 ^-3 [1/Ωcm] to 8×10 ^-2 [1/Ωcm] can be obtained.

Further, the semi-amorphous silicon semiconductor has a concentration of 1×10 ^-3 in a substantially intrinsic state.
A dark conductivity of [1/Ωcm] to 1×10 ^-5 [1/Ωcm] can be obtained.

The photoconductivity and dark conductivity values of the semi-amorphous silicon semiconductor are 1/2 to 1/10 of those of a single crystal silicon semiconductor.

That is, the semi-amorphous silicon semiconductor has extremely excellent properties in terms of photoconductivity and dark conductivity.

The excellent properties of this semi-amorphous silicon semiconductor were experimentally discovered by the applicant.

Some details regarding the excellent properties of semi-amorphous silicon semiconductors are published in the following documents.

(1) Appl.Phys.Lett.39(3), 1981, pp.142-144.

(2) 1981 Spring Conference of the Japan Society of Applied Physics 1aS5,
“Structural observation and optical and electrical properties of a-Si containing microcrystals”, p. 422.

(3) 1981 Autumn 42nd Academic Conference of the Japan Society of Applied Physics 7a-A-1, 7a-A-2, p. 403.

[Conventional technology]

FIG. 1 is a longitudinal sectional view of a conventional insulated gate field effect semiconductor device using an amorphous silicon semiconductor.

In FIG. 1, gate electrodes 3 and 13 of the insulated gate field effect semiconductor device are formed on an insulating substrate 1. In FIG. This gate electrode 3,1
3 are formed from a heat resistant material, for example molybdenum.

The gate insulating film 11 formed on each surface of the gate electrodes 3 and 13 is configured as a single layer film. This gate insulating film 11 is a silicon oxide film formed by the CVD method. This silicon oxide film is formed with a thickness of 0.1 [μm] to 0.5 [μm].

Amorphous silicon semiconductors 5 and 10 are formed on the surface of the gate insulating film 11, respectively. Amorphous silicon semiconductor 5 is formed only on gate electrode 3 of N-channel insulated gate field effect semiconductor device 12 . The amorphous silicon semiconductor 10 is formed only on the gate electrode 13 of the P-channel insulated gate field effect semiconductor device 2 . Both amorphous silicon semiconductors 5 and 10 are formed by selective photoetching.

In the N-channel insulated gate field effect semiconductor device 12, each of the N-type semiconductor layers 6 and 7 is formed by selective fetetching. Each of the N-type semiconductor layers 6 and 7 includes a source region 6,
They are used as each of the drain regions 7.

In the P-channel insulated gate field effect semiconductor device 2, each of the aluminum films 8 and 9 formed by vacuum evaporation is formed by selective photoetching. Each of the aluminum films 8 and 9 is used as a source region 9 and a drain region 8, respectively.

In FIG. 1, it is formed of a P-channel type insulated gate type field effect semiconductor device 2 and an N-channel type insulated gate type field effect semiconductor device 12.
A CMOSFET (complementary MOSFET) is configured.

[Problem to be solved by the invention]

In the aforementioned N-channel insulated gate field-effect semiconductor device 12 (the same applies to the P-channel insulated-gate field-effect semiconductor device 2), the following points are not taken into consideration.

(1) In the N-channel insulated gate field effect semiconductor device 12, the gate insulating film 11 is formed of a single layer of silicon oxide film. Moreover, since this gate insulating film 11 is formed by the CVD method, it is difficult to obtain a high-density film quality, and there are portions that lack silicon-oxygen reactivity.

Therefore, pinholes are likely to occur in the gate insulating film 11, and shoots and leaks occur between the gate electrode 3 and the amorphous silicon semiconductor 5 due to the pinholes. In order to prevent this shot and leakage from occurring, the thickness of the gate insulating film 11 must be increased to 0.3 [μm] or more.

Further, at the interface between the silicon oxide film as the gate insulating film 11 and the amorphous silicon semiconductor 5, hydrogen existing in each film acts as a catalyst, and a chemical reaction easily proceeds. For this reason, the reliability of the film quality of the gate insulating film 11 and the amorphous silicon semiconductor 5 has decreased, and the characteristics have also deteriorated.

Because the gate insulating film 11 must be made thick to prevent shortcuts and leaks, the N-channel insulated gate field effect semiconductor device 12 requires a gate voltage of 20 [V] to 60 [V]. It is necessary to apply a large driving voltage.

That is, the N-channel insulated gate field effect semiconductor device 12 has a voltage of 1.5 [V] to 5.
It is difficult to realize driving based on a low voltage of [V].

(2) Furthermore, in the N-channel insulated gate field effect semiconductor device 12, both ends of the gate electrode 15 in the gate length direction, an amorphous silicon semiconductor 5
, one end of the source region 6 , one end of the drain region 7
It is not possible to precisely align each end of the

That is, in addition to mask misalignment during manufacturing, warpage and shrinkage of the insulating substrate (glass substrate) 1,
Since the alignment is performed in a state where there are irregularities on the insulating substrate 1, it is almost impossible to perform alignment with high accuracy within 1 [μm].

Therefore, the N-channel insulated gate field effect semiconductor device 12 requires a tolerance of 20 [μm] to [30 μm] in manufacturing.

Therefore, in the N-channel insulated gate field effect semiconductor device 12, the degree of overlap between the gate electrode 15 and the drain region 7 to which a high voltage is applied increases, and with this increase, parasitic Capacity increases. Due to this increase in parasitic capacitance, the drain voltage must be increased to 50 [V] to 70 [V].

Further, the parasitic capacitance has large variations due to manufacturing. Therefore, the N-channel type insulated gate type field effect semiconductor device 12 cannot be used practically.

(3) Furthermore, the N-channel type insulated gate field effect semiconductor device 12 is in close contact with the channel formation region having structural sensitivity, that is, the surface of the amorphous silicon semiconductor 5, and the source region 6 and the drain region 7, respectively. is formed. Each of the source region 6 and drain region 7 is N
The impurity of the conductivity type of the mold is 0.5 [%] to 2 [%]
The semiconductor layers 6 and 7 are each formed with a large amount of doping in the range of . Unless each of the semiconductor layers 6 and 7 is completely etched away on the surface of the amorphous silicon semiconductor 5, a shot will occur between the source region 6 and the rain region 7.

However, since the lower amorphous silicon semiconductor 5 and the upper semiconductor layers (source region) 6 and (drain region) 7 each have the same main component, it is difficult to ensure etching selectivity, and the source region 6 and Shorts are likely to occur between the drain region 7 and the drain region 7.

(4) Furthermore, the amorphous silicon semiconductor 5
Even after the source region 6 and the rain region 7 are formed in a later process and the N-channel insulated gate field effect semiconductor device 12 is completed, the surface of the is exposed to the air as shown in FIG. do. Amorphous silicon semiconductor 5
has structural sensitivity, and particularly in amorphous silicon systems, has microcrystallinity.

For this reason, the N-channel type insulated gate type field effect semiconductor device 12 is difficult to put into practical use industrially due to low reliability of the film quality and characteristics of the amorphous silicon semiconductor 5 and manufacturing problems with large variations. I couldn't do it.

For these reasons, the insulated gate field effect semiconductor device having the structure shown in FIG. 1 is not suitable for actual industrial use.

The present invention has been made in order to solve the above-mentioned problems, and is capable of preventing leakage due to pinholes between the gate electrode and the channel forming region, and is based on the reaction between the channel forming region and silicon.
An object of the present invention is to provide a method for manufacturing an insulated gate field effect semiconductor device that can prevent deterioration of the film quality or characteristics of a gate insulating film.

In addition to the above object, the present invention also provides an insulated gate field effect semiconductor that can reduce parasitic capacitance between a gate electrode and a drain electrode and prevent shortening between the gate electrode and the drain region. The purpose is to provide a method for manufacturing the device.

Furthermore, in addition to the above-mentioned objects, it is an object of the present invention to provide a method for manufacturing an insulated gate field effect semiconductor device that can improve the reliability of the film quality and characteristics of a channel forming region.

[Means to solve the problem]

In order to achieve the above object, the method for manufacturing an insulated gate field effect semiconductor device of the present invention includes forming a gate electrode 20 by patterning a semiconductor or conductor material of one conductivity type on a substrate 1 having an insulating surface. forming an oxide insulating film on the top and side surfaces of the gate electrode 20 through a step of oxidizing the gate electrode material; and covering the oxide insulating film with a silicon nitride film to form a multilayer film structure. a step of forming the gate insulating film 21 of the substrate 21;
and a step of forming a mask forming layer 220 and a photoresist film on the gate electrode 20 covered with the insulating film 21, and using the photoresist film 24 formed by exposing from the back side using the gate electrode 20 as a mask. patterning the mask forming layer 22 to form the mask 22 only on the upper surface of the gate electrode 20; and doping impurities on the substrate 1, the peripheral edge on the side of the gate insulating film 21, and on the mask 22. A step of forming the semiconductor layer 270, and forming the semiconductor layer 270 in such a way as to leave a portion of the semiconductor layer 270 that will become the source region 29 and drain region 30 and a portion above the mask 22, and to make a hole in the portion above the mask 22. The semiconductor layer 270 on the mask 22 is patterned and lifted off the mask 22.
, and the source region 29 and drain region 3
and a step of forming a non-single crystal semiconductor layer doped with intrinsic or substantially intrinsic hydrogen that forms the channel forming region 27 in close contact with the silicon nitride film, the source region, and the drain region. It is characterized by consisting of.

[Effect]

The present invention is based on the above-described invention and provides the following effects in a method for manufacturing an insulated gate field effect semiconductor device.

The method for manufacturing an insulated gate field effect semiconductor device of the present invention provides the following effects.

(1) A gate insulating film is formed on the upper surface and side surfaces of the gate electrode, and a source region and a drain region are formed on both sides of the gate electrode, respectively, and spaced apart from each other with the gate insulating film interposed therebetween.

The source region and the drain region are formed by matching the end of the source region with one of the ends of the gate electrode and matching the end of the drain region with the other, so that Each is formed by self-alignment.

(2) Due to the effect (1), the tolerance between the gate electrode and the source and drain regions is reduced during manufacturing, so that the channel length of the insulated gate field effect semiconductor device can be shortened. .

For example, insulated gate field effect semiconductor devices can have extremely short channel lengths of 1 [μm] to 10 [μm].

(3) Due to the effect (1), it is possible to reduce the overlap between the gate electrode and each of the source and drain regions, especially the drain region, thereby reducing the parasitic capacitance added to the drain region and reducing the drain voltage. can be reduced.

For example, in an insulated gate field effect semiconductor device, the drain voltage can be lowered from 40 to 80 V to 5 to 10 V.

(4) Due to the effect (2), the resistance of the channel formation region can be reduced, so that the insulated gate field effect semiconductor device can obtain high frequency characteristics.

For example, when an insulated gate field effect semiconductor device is driven at 1.5 [V] and an amorphous silicon semiconductor having microcrystallinity is used in the channel formation region, the insulated gate field effect semiconductor device has a frequency of 10 [MHz] to 40 [MHz].
Hz] high frequency characteristics can be obtained. Furthermore, when an amorphous silicon semiconductor is used in the channel forming region, an insulated gate field effect semiconductor device can obtain high frequency characteristics of 10 [[MHz] to 30 [MHz]].

(5) Due to the effect (1), the upper surface of the gate electrode is brought close to the upper surface of each of the source region and the drain region so that it is on the same plane as each other. In other words, in an insulated gate field effect semiconductor device, the top surface of the gate electrode, which is the base of the channel formation region, the top surface of the source region, and the top surface of the drain region are each smoothly continuous to form a planar structure (flattened structure). is formed.

(6) A source region and a drain region are formed in advance at both ends of the gate electrode, and then channel formation regions are formed on the upper surface of the gate electrode, the upper surface of the source region, and the upper surface of the drain region, so that the channel formation The resistance of the source region and drain region can be controlled independently.

For example, an insulated gate field effect semiconductor device has a source region and a drain region formed of a P-type or N-type non-single crystal semiconductor, particularly a polycrystalline silicon semiconductor, so that the electrical conductivity of the polycrystalline silicon semiconductor is increased to 1. [Ωcm ^-1 ] or
Can be set to 100 [Ωcm ^-1 ].

(7) After forming the gate electrode, source region, and drain region, a channel formation region is formed on each of the upper surface of the gate electrode, the upper surface of the source region, and the upper surface of the drain region as a final step. Even when the film is formed of an intrinsic, P-type, or N-type non-single crystal semiconductor having structural sensitivity, deterioration of film quality and change in characteristics due to heat treatment during manufacturing can be minimized.

The non-single crystal semiconductor used as the channel forming region has a thickness in the range of, for example, 0.05 [μm] to 5 [μm], and typically has a thickness of 0.1 [μm] to 1 [[μmm]]. be done.

Furthermore, according to the present invention, the following effects can be obtained.

(1) A plurality of the insulated gate field effect semiconductor devices are arranged in the channel length direction, and in this arrangement, one source region or drain region of the adjacent insulated gate field effect semiconductor device in the preceding stage is connected to the insulated gate in the succeeding stage. By sharing it with the other drain region or source region of the type field effect semiconductor device, the occupied area corresponding to the source region or drain region can be reduced.
Integration density can be improved.

(2) Due to the effect (1), one source region or drain region of the insulated gate field effect semiconductor device at the front stage of the array and the other drain region or drain region of the insulated gate field effect semiconductor device at the rear stage of the array are adjacent to each other in the array. Since the isolation region between the source region and the source region can be eliminated, the integration density can be further improved.

(3) Due to the effect (2), high integration density can be obtained even when the insulated gate field effect semiconductor devices are arranged in a matrix structure.

(4) According to the effect (2) or the effect (3), an image sensor can be constructed by using a translucent quartz glass substrate as the insulating substrate. In this image sensor, one cell can be constructed from one insulated gate field effect semiconductor device.

(5) According to operation (2) or operation (3), a flat panel liquid crystal display can be constructed by using a light-shielding alumina ceramic substrate as the insulating substrate. This flat panel liquid crystal display consists of one cell (one pixel) consisting of one insulated gate field effect semiconductor device and one capacitor (one transistor/one capacitor structure) connected to it on the surface of an alumina ceramic substrate. can. A liquid crystal is disposed between the electrodes of the capacitor.

(6) By the above action (2) or action (3), one insulated gate field effect semiconductor device is made into one cell (one memory cell), and a nonvolatile memory is configured in which a plurality of these cells are arranged in a matrix structure. can.

〔Example〕

Examples of the present invention will be described below.

FIG. 2 is a vertical end view of an insulated gate field effect semiconductor device according to an embodiment of the present invention. FIG. 3 is a longitudinal sectional view of an insulated gate field effect semiconductor device which is a first reference example of the present invention. FIG. 4 is a longitudinal sectional view of an insulated gate field effect semiconductor device according to an embodiment of the present invention. FIG. 5A is a longitudinal sectional view of an insulated gate field effect semiconductor device which is a second reference example of the present invention. FIG. 5B is a longitudinal sectional view of an insulated gate field effect semiconductor device according to a third reference example of the present invention. FIG. 6 is a block circuit diagram of an image sensor according to a fourth reference example of the present invention.

In FIG. 2, of the entire manufacturing process from the substrate preparation process to the process of completing the insulated gate field effect semiconductor device, the manufacturing method for the first stage from the substrate preparation process to the process of forming the gate insulating film will be explained. .

First, as shown in FIG. 2A, a substrate 1 having an insulating surface is prepared. Then, as shown in FIG. 2A, a gate electrode 20, a gate insulating film 21, and a mask forming layer (protective layer) 220 are sequentially formed on the insulating surface of the substrate 1.

The substrate 1 is a quartz glass substrate that is insulating and translucent.

Further, as the substrate 1, a ceramic substrate having insulating properties is used.

The gate electrode 20 is formed by a plasma vapor phase method. That is, the gate electrode 20 is formed of a non-single crystal semiconductor deposited on the insulating surface (forming surface) of the substrate 1 by plasma vapor deposition.

In the plasma vapor phase method, silane (monosilane or polysilane) or silicon fluoride is used as a reactive gas. Helium or hydrogen is used as a carrier gas to dilute the reactive substrate. In the plasma gas phase method, first, a reactive gas is diluted with a carrier gas, the reactive gas and carrier gas are introduced into a reactor, and the reactive gas and carrier gas are turned into plasma in the reactor, and the reactive gas is decomposed. By reacting, a non-single crystal semiconductor is formed on the insulating surface of the substrate 1.

The above plasma vapor phase method uses 0.01 [torr] to 10
The pressure inside the reactor is set to [torr], for example 0.3 [torr]. The substrate 1 placed in the reactor is
It is heated to 100 [°C] to 400 [°C], for example 300 [°C]. The reactive gas and carrier gas are turned into plasma using direct current or 500 [KHz] to 50
[MHz] For example, arc discharge or glow discharge using a high frequency of 13.5 [MHz] is performed.

Furthermore, the plasma generation is performed by applying the direct current or high frequency to 1 [GHz] to 10 [GHz], for example.
The electromagnetic energy of microwaves of 2.45 [GHz] is 5
Arc discharge or glow discharge applied as an output of [W] to 200 [W] may be used.

By plasma vapor deposition under such conditions, an intrinsic or substantially intrinsic non-single crystal semiconductor having microcrystallinity is formed on the insulating surface of the substrate 1. This non-single crystal semiconductor is, for example, 0.1 [μm]
It is formed with a thickness of 1 μm to 1 μm.

As is clear from the completed diagram shown in FIG. 4C, the current flowing between the source region 29 and the drain region 30 flows in a direction parallel to the insulating surface of the substrate 1.

Therefore, in this example, when generating a non-single crystal semiconductor, the insulating surface of the substrate 1 is arranged parallel to the surface of the electrode for glow discharge or arc discharge, and the lateral electrical conductivity is set to be large. do.

In the reactor of the same plasma CVD apparatus used in this example, the non-single crystal semiconductor has a dependence on the formation temperature, for example, 5 [W] or
In the case of a microwave power of 200 [W], it is formed as an amorphous silicon semiconductor.

In addition, non-single crystal semiconductors have a power of 20 [W] to 50
In the case of the microwave output of [W], an amorphous silicon semiconductor with microcrystallinity, which is an intermediate region,
That is, it is formed as a semi-amorphous silicon semiconductor.

In addition, non-single crystal semiconductors have a power of 80 [W] to 200
In the case of microwave output of [W], it is formed as a polycrystalline silicon semiconductor.

Further, a non-single crystal semiconductor is formed as a polycrystalline silicon semiconductor at a generation temperature of 400 [° C.] or higher and a microwave output of 50 [W] or higher.

The amorphous silicon semiconductor has short range ordering (some regularity)
However, it does not have crystallinity.

Further, an amorphous silicon semiconductor having microcrystallinity, that is, a semi-amorphous silicon semiconductor has microcrystallinity having lattice strain in the short range order of 5 [Å] to 100 [Å].

Each of these amorphous silicon semiconductors and semi-amorphous silicon semiconductors has a recombination center neutralizing agent of 0.01 [mol%] by a halogen element such as hydrogen or fluorine that neutralizes the dangling bonds of silicon.
It is added in an amount of 5 to 5 [mol%].

In addition, in the semi-amorphous silicon semiconductor, an alkali metal such as lithium, sodium, or potassium is added to the semi-amorphous silicon semiconductor in order to neutralize the dangling bonds that cannot be canceled out by the neutralizing agent ^.
It may be added at a concentration of [cm ^-3 ] to 10 ¹⁸ [cm ^-3 ] to improve radiation resistance and frequency characteristics.

In the semi-amorphous silicon semiconductor, 1×10 ^-6 [1/Ωcm] to 3×10 ^-3 [1/Ωcm]
cm] dark conductivity is 1×10 ^-3 under AM1 conditions.
Photoconductivities of 1/Ωcm to 8×10 ⁻² 1/Ωcm were obtained experimentally, respectively.

In addition, amorphous silicon semiconductor is 10 ^-10
[1/Ωcm] to 10 ^-6 [1/Ωcm] dark conductivity is 10 ^-6 [1/Ωcm] to 3×10 ^-4 [1/Ωcm]
A photoconductivity of , respectively, was obtained experimentally.

Each of these amorphous silicon semiconductors and semi-amorphous silicon semiconductors can be used depending on the practical use.

When the gate electrode 20 is formed of a non-single crystal semiconductor layer of P-type or N-type conductivity type, a valent impurity or a valence impurity is added to the reactive substrate in the plasma vapor phase method.

For example, diborane (B ₂ H ₆ ) is used as a functional impurity.

Diborane is added at a ratio of 0.2% to 2% relative to silane, which is a reactive gas.

Further, as a functional impurity, for example, phosphine (PH ₃ ) is used.

Phosphine is added at a rate of 0.2% to 2% relative to silane.

In particular, the P-type or N-type conductivity type semiconductor layer is formed not as an amorphous silicon semiconductor but as a semi-amorphous silicon semiconductor or a polycrystalline silicon semiconductor.

Each of these semi-amorphous silicon semiconductors and polycrystalline silicon semiconductors is 0.1 to 100
An electrical conductivity of [1/Ωcm] and an activation energy of 0.02 [eV] can be obtained, and all of the added impurities can be made into acceptors or donors.

Note that the non-single crystal semiconductor may be formed using a reduced pressure vapor phase method.

As a result, the gate electrode 20 of this embodiment has P+
type or N+ type conductivity type semiconductor layer, i.e.
It is formed from either a semi-amorphous silicon semiconductor or a polycrystalline silicon semiconductor. Gate electrode 2
The film thickness of 0 is formed in the range of 0.1 [μm] to 0.5 [μm]. The gate length dimension of the gate electrode 20 is
The thickness is 1 [μm] to 30 [μm], typically 5 [μm] to 10 [μm]. This gate electrode 20
The patterning is performed by etching using a mask formed by photolithography.

Further, the gate electrode 20 may be formed of a heat-resistant metal conductor such as molybdenum or tungsten, or a heat-resistant metal silicide conductor such as molybdenum silicide or tungsten silicide.

The gate insulating film 21 is composed of a multilayer film of an oxide film of the gate electrode material formed on the upper surface and side surfaces of the gate electrode 20, and a nitride film formed on the surface of this oxide film.

The oxide film of the gate insulating film 21 is formed by a thermal oxidation method or a plasma oxidation method. That is, in this embodiment, since the gate electrode 20 is formed of either a semi-amorphous silicon semiconductor or a polycrystalline silicon semiconductor, the oxide film is formed of a silicon oxide film. This silicon oxide film is formed to have a thickness of, for example, 10 [nm] to 100 [nm].

The silicon nitride film is heated at a temperature of, for example, 200 [°C] or
It is formed in ammonia heated to 1100 degrees Celsius and excited by microwaves. The silicon nitride film is formed to have a thickness of, for example, 2 [nm] to 5 [nm].

Further, the silicon nitride film may be formed to have a thickness of, for example, 10 [nm] to 150 [nm] using a reduced pressure vapor phase method.

In this way, the gate insulating film 21 is formed with a multilayer structure consisting of a silicon oxide film obtained by oxidizing the surface of the gate electrode 20 and a silicon nitride film formed on the surface of this silicon oxide film. The silicon oxide film and the silicon nitride film of the gate insulating film 21 are selectively formed on the upper surface and side surfaces of the gate electrode 20, respectively.

As a result, in the gate insulating film 21, few pinholes occur in the silicon oxide film itself. In particular, it is extremely unlikely that pinholes will occur at the same location in the silicon oxide film and the silicon nitride film.

That is, in the gate insulating film 21 of this embodiment, the occurrence of pinholes is generally reduced compared to a gate insulating film having a single layer structure formed by a vapor phase method.

When the gate insulating film 21 is formed of a single-layer silicon nitride film as in the conventional case, and this silicon nitride film is formed by a low pressure vapor phase method, coverage of the corner portions of the gate electrode 20 is poor. Pinholes are likely to form in this area, causing leaks.

In this respect as well, the gate insulating film 2 of this embodiment
1, since a silicon oxide film with extremely few pinholes is previously formed on the surface of the gate electrode 20 by an oxidation method, there is a gap between the gate electrode 20 and the channel forming region 27 (see FIG. 4B) that will be formed later. can prevent leaks.

Furthermore, the silicon nitride film constituting the gate insulating film 21 has a property of not allowing hydrogen to pass through.

That is, the passage of hydrogen is blocked between the silicon oxide film underlying the gate insulating film 21 and the channel forming region 27 formed on the surface of the gate insulating film 21 by the silicon nitride film forming the gate insulating film 21. be done.

Even if there is no pinhole in the silicon oxide film constituting the gate insulating film 21, oxygen, which is a component of the silicon oxide film, may come into direct contact with the hydrogen-containing silicon constituting the channel forming region 27. If so, they may react with each other, causing deterioration of the film quality and characteristics of the silicon oxide film.

That is, since the silicon nitride film constituting one layer of the gate insulating film 21 blocks hydrogen and oxygen, deterioration of the film quality of the silicon oxide film constituting the other layer of the gate insulating film 21 can be prevented. I can do it.

The mask forming layer 220 formed on the surface of the gate insulating film 21 is formed of a silicon oxide film deposited by a low pressure vapor phase method or a heat resistant polyimide resin (PIQ) film coated by a spin coating layer. The silicon oxide film or heat-resistant polyimide resin film as the mask forming layer 220 is formed to have a thickness of 0.5 [μm] to 3 [μm], typically 0.1 [μm] to 1.5 [μm].

Next, as shown in FIG. 2B, a photoresist film (not shown) is applied to the entire surface of the mask forming layer 220. This photoresist film is then patterned to form a mask 24 from the photoresist film.

As the photoresist film, a negative type photoresist film is used. This photoresist film is irradiated with ultraviolet rays 23 from below the substrate 1 and exposed using the gate electrode 20 as a mask 24.

That is, when the photoresist film is subjected to a development process and a rinsing process after exposure, it remains only on the upper surface of the gate electrode 20 as a mask 24, and other areas are removed. Moreover, the mask 24
is formed in self-alignment with respect to the gate electrode 20.

Next, as shown in FIG. 2C, the mask forming layer 220 is patterned using the mask 24, and the mask 22 is formed from this mask forming layer 220. The mask 24 is then removed.

When a silicon oxide film is used as the mask forming layer 220, patterning is performed by a solution method using a hydrofluoric acid-based etching solution.

Furthermore, when a heat-resistant polyimide resin film is used as the mask forming layer 220, the patterning is performed as follows.
This is done by elution using a hydrazine-based etching solution.

The mask 22 is formed in self-alignment with the gate electrode 20 because the mask 24 for patterning it is self-aligned with the gate electrode 20.
It is formed by self-alignment with respect to 0.

As shown in FIG. 2C, according to this embodiment,
Gate electrode 20 formed on the insulating surface of substrate 1
The upper surface 25 and side surfaces of the gate insulating film 21 are surrounded by the gate insulating film 21.

Further, a mask 22 having the same shape is formed on the upper surface 25 of the gate electrode 20 so as to substantially match both ends of the gate electrode 20.

(First Reference Example) Next, a first reference example of the present invention will be described using the vertical cross-sectional view of FIG. 3.

In this reference example, similar to the manufacturing method of the above example,
In this method, the gate electrode 20 and the mask 22 are formed using one mask 24, and the mask 24 is exposed to light from above the substrate 1.

First, as shown in FIG. 3A, a substrate 1 is prepared, and a gate electrode forming layer 200, a gate insulating film forming layer 210, and a mask forming layer 220 are sequentially formed on the insulating surface of the substrate 1.

Next, as shown in FIG. 3A, a mask 24 is selectively formed on the surface of the mask forming layer 220.

As the substrate 1, a quartz glass substrate or a ceramic substrate is used as described above.

As described above, the gate electrode forming layer 200 is made of a non-single crystal semiconductor, for example, a P-type or N-type conductivity type semiconductor layer. Furthermore, for the gate electrode forming layer 200, a heat-resistant metal conductor or a heat-resistant metal silicide conductor is used.

As described above, the gate insulating film forming layer 210 includes a silicon oxide film (or metal oxide film) formed on the surface of the gate electrode forming layer 200 by an oxidation method, and a nitride film formed on the surface of this silicon oxide film. It has a multilayer structure made of silicon film.

The mask forming layer 220 includes, as described above,
A silicon oxide film or a heat-resistant polyimide resin film is used.

The mask 24 is formed by sequentially exposing, developing, and rinsing a photoresist film coated on the entire surface of the mask forming layer 220 by a spin coating method, and patterning it to the size of the gate electrode 20. It is formed by The photoresist film may basically be either negative or positive (active type). To expose the photoresist film, ultraviolet rays are irradiated from above the substrate 1 .

Next, as shown in FIG. 3B, using the mask 24, the mask forming layer 220, the gate insulating film forming layer 210, and the gate electrode forming layer 200 are sequentially patterned.
1 and a gate electrode 20 are formed.

That is, each of the mask 22, the gate insulating film 21, and the gate electrode 20 is patterned based on one mask 24, and is formed in self-alignment with respect to the mask 24.

Next, the mask 24 is removed. Then, as shown in FIG. 3C, the gate electrode 20
An insulating film 26 is formed on the exposed side surface.

The insulating film 26, like the gate insulating film 21, has a multilayer structure consisting of a silicon oxide film and a silicon nitride film formed on the surface of the silicon oxide film.

The silicon oxide film of the insulating film 26 is formed by a thermal oxidation method or a plasma oxidation method. When the oxidation temperature by the plasma oxidation method is in the range of 100 [°C] to 300 [°C], a heat-resistant polyimide resin film can be used as the mask 22.

Furthermore, if the oxidation temperature is 600 [°C] or higher, especially in the range of 1000 [°C] to 1150 [°C] used for manufacturing, the heat resistance will be exceeded, so the mask 22 cannot be formed using the CVD method. A silicon oxide film is used.

The silicon nitride film constituting the insulating film 26 is formed by a plasma nitriding method. When this plasma nitriding method is performed, the exposed surface of the mask 24 is also nitrided, but this nitride film can be easily removed in a subsequent step.

As shown in FIG. 3C, according to this reference example,
Similar to the first embodiment, the upper surface of the gate electrode 20 formed on the insulating surface of the substrate 1 is surrounded by the gate insulating film 21, and the side surfaces are surrounded by the insulating film 26.

Further, a mask 22 having the same shape is formed on the upper surface of the gate electrode 20 and substantially coincides with both ends of the gate electrode 20.

Further, in this reference example, after forming the mask 22 shown in FIG. 3B, selective side etching may be performed on the mask 22 to form the mask 22 into a slim shape. The mask 22 formed in this slim shape can be easily removed by a lift-off method in a post-process (see FIG. 4C of this embodiment).

Furthermore, in this embodiment, the thicknesses of the gate insulating film 21 on the top surface of the gate electrode 20 and the insulating film 26 on the side surfaces can be controlled independently. That is, the thickness of the gate insulating film 21 is reduced, for example, to 10 [nm].
By setting the film thickness to 100 nm to 100 nm, an insulated gate field effect semiconductor device can be driven at a low voltage.

On the other hand, the thickness of the insulating film 26 is increased, for example, by 20 mm.
By setting the film thickness to [nm] to 400 [nm], the parasitic capacitance generated between the gate electrode 20 and the drain region 30 in particular can be reduced.

In this embodiment, a manufacturing method from the step of forming the gate insulating film 21 to the step of completing the insulated gate field effect semiconductor device will be explained using the longitudinal cross-sectional view of FIG. 4.

This embodiment will be explained from the steps after the step shown in FIG. 2C.

The manufacturing method of this embodiment is the same even if it is performed from the steps after the step shown in FIG. 3C, which is the first reference example.

After the step shown in FIG. 2C of this embodiment, that is, the step in which the gate electrode 20, gate insulating film 21, and mask 22 (first mask) are formed, as shown in FIG. 4A, semiconductor layer 270,
Each of the masks 28 (second masks) is formed in sequence.

The semiconductor layer 270 includes a mask 22 and an insulating film 2.
1, that is, at least the portions where the source region 29 and drain region 30 are formed at both ends of the gate electrode 20.

The semiconductor layer 270 is formed using the same method as the gate electrode 20. semiconductor layer 270
In the case of an N-channel insulated gate field effect semiconductor device, an N-type impurity is added, and in the case of a P-channel insulated gate field-effect semiconductor device, a P-type impurity is added. The semiconductor layer 270 is
It is formed with a film thickness of 0.1 [μm] to 0.5 [μm].

The mask 28 is formed on the surface of the semiconductor layer 270. This semiconductor layer 270 is patterned to leave a portion that will become the source region 29 and drain region 30 and a portion above the mask 22, and to form a hole in the portion above the mask 22.

By lifting off the mask 22, the semiconductor layer 270 on the mask 22 is removed, and a source region 29 and a drain region 30 are formed.

The mask 22 is dissolved by the lift-off method,
When a silicon oxide film is used, a hydrofluoric acid-based etching solution is used. Furthermore, when a heat-resistant polyimide resin film is used, the mask 22 is removed using a hydrazine-based etching solution.

Further, in removing the mask 22, light ultrasonic vibration is applied in combination with etching.

The adhesive strength between the mask 22 and the surface of the gate insulating film 21, which is the underlying surface thereof, is weaker than the adhesive strength between the source region 29 and its underlying surface, and the adhesive strength between the drain region 30 and its underlying surface. Therefore, by using ultrasonic vibration, the mask 22
are all removed.

In this way, the mask 22 is selectively removed, and as a result, it is removed by the lift-off method.

The aforementioned source region 29 and drain region 30
are formed separately at both ends of the gate electrode 20. In addition, the source area 29
and drain region 30 are formed as a pair of impurity regions.

One side surface of each of the source region 29 and drain region 30 on the gate electrode 20 side is adjacent to the side surface of the gate electrode 20 with the gate insulating film 21 interposed therebetween.

That is, one of the two side surfaces of the gate electrode 20 is formed to substantially coincide with one side surface of the source region 29 . Similarly, the other side of the both sides of the gate electrode 20 is formed to substantially coincide with one side of the drain region 30.

As a result, each of source region 29 and drain region 30 is formed in self-alignment with respect to gate electrode 20. Moreover, the gate electrode 2
The manufacturing alignment between the source region 29 and the drain region 30 is substantially performed using one mask 22 (first mask).

Furthermore, as explained in the previous embodiment (see FIG. 2), this mask 22 is formed based on one mask 24, and is formed in self-alignment with respect to this mask 24.

Through the steps so far, the gate electrode 20, gate insulating film 21, source region 29, and drain region 30 were formed.

As described above, the gate insulating film 21 is formed on the upper surface of the gate electrode 20 and the side surfaces of the gate electrode 20.

Each of the source region 29 and the drain region 30 is formed of an intrinsic semiconductor layer 270 or a substantially intrinsic semiconductor layer 270 which has a conductivity type and is structurally sensitive by the plasma vapor deposition method shown in the above embodiment. Ru. Each of the source region 29 and drain region 30 is formed in close contact with each of the gate insulating films 21, particularly the silicon nitride film.

Furthermore, source region 29 and drain region 3
0 are formed on the insulating surface of the substrate 1 at each of both ends of the gate electrode 20 .

Next, as shown in FIG. 4B, a channel forming region 27 is formed on the upper surface of each of the gate electrode 20, source region 29, and drain region 30. The channel forming region 27 is connected to the gate electrode 20
The gate insulating film 21 is formed on the upper surface of the gate insulating film 21 .

Further, the channel forming region 27 is located in the source region 2
9 and the drain region 30 are formed directly in close contact with each other. The channel forming region 27 is
Patterning is performed using a photomask (third mask) shown in FIG. 4B.

The channel forming region 27 is preferably formed of a semi-amorphous silicon semiconductor layer having microcrystalline properties. The channel forming region 27 formed of this semi-amorphous silicon semiconductor layer is
High-speed operation of an insulated gate field effect semiconductor device can be realized.

Furthermore, an insulating film may be formed on the surface of the channel forming region 27 before patterning with the photomask (third mask). This insulating film is
Deterioration of the characteristics of the channel forming region 27 can be prevented.

Furthermore, the patterning using the photomask (third mask) can simultaneously remove the edge of the gate insulating film 21 on the upper surface of the gate electrode 20, and the gate extraction electrode 36 is formed together with the source region extraction electrode 38 and the drain region extraction electrode 39. be done.

By performing the above steps, three photomasks, namely, the first mask, the second mask,
and a third mask, an insulated gate field effect semiconductor device is formed on the insulating surface of the substrate plate 1. Moreover, the insulated gate field effect semiconductor device is formed with a planar structure.

Next, as shown in FIG. 4C, an interlayer insulating film 6 is formed on the upper surface of the insulated gate field effect semiconductor device.
5 is coated. Then, electrode holes 66 are formed in this interlayer insulating film 65. after that,
Electrodes 67, 68 and 69 are formed.

The interlayer insulating film 65 is made of, for example, heat-resistant polyimide resin. The electrode 69 is connected to the source region extraction electrode 38 at the contact portion 41 .

The electrode 67 is connected to the drain region extraction electrode 39 at the contact portion 40 . Electrode 68 is connected to gate extraction electrode 36 .

As explained above, this embodiment includes a step of forming the gate electrode 20 on the insulating surface of the substrate 1, a step of forming the gate insulating film 21 surrounding the gate electrode 20, and a step of self-aligning the gate electrode 20. Moreover, it includes a step of forming a pair of source regions 29 and a drain region 30 in a planar structure in close contact with the insulating surface of the substrate 1, and a step of forming a channel forming region 27 from a semiconductor layer having the highest structural sensitivity in the final step. . Then, an insulated gate field effect semiconductor device can be obtained by sequentially performing each of the above steps.

In the above process, an insulated gate field effect semiconductor device with a planar structure is obtained using three photomasks (first mask, second mask, and third mask).

Further, by adding two photomasks (masks for forming patterns and in FIG. 4C) to the above process, a two-layer wiring in an insulated gate field effect semiconductor device is adopted.

Furthermore, the gate electrode 20, source region 29, and drain region 30 of the insulated gate field effect semiconductor device (also referred to as a thin film transistor)
are formed in self-alignment with respect to the mask 24, so the channel length of the insulated gate field effect semiconductor device is set to 1 [μm] to 10 [μm].
It can be reduced to a range of .

Further, the insulated gate field effect semiconductor device uses an amorphous silicon semiconductor having microcrystalline properties in the channel forming region 27, and can flow a current in the lateral direction, so that frequency characteristics can be improved.

For example, in an insulated gate field effect semiconductor device,
If you prototype an 11-stage ring oscillator, 10 [M
Hz] to 100[MHz] frequency characteristics were obtained.

(Second Reference Example) This reference example uses the insulated gate field effect semiconductor device of the above embodiment to obtain the maximum packaging density.

The vertical cross-sectional structure of an insulated gate field effect semiconductor device according to this reference example will be explained using FIG. 5A.

In this reference example, as shown in FIG. 5A, one insulated gate field effect semiconductor device 40 and another insulated gate field effect semiconductor device 41 are arranged adjacent to each other on the insulating surface of the substrate 1. be done. No isolation region is provided between each of the insulated gate field effect semiconductor devices 40 and 41.

The one insulated gate field effect semiconductor device 4
0 is composed of a gate electrode 20, a gate insulating film 21, a source region 29, a drain region 30, and a channel forming region 27. Another insulated gate field effect semiconductor device 41 has a gate electrode 2
0', gate insulating film 21', source region 29', drain region 30, and channel forming region 27'
It consists of

The one insulated gate field effect semiconductor device 4
The drain region 30 of No. 0 is shared with the drain region 30 of another insulated gate field effect semiconductor device 41. Similarly, the source region 29 of one insulated gate field effect semiconductor device 40 is shared with the source region 29 of the adjacent insulated gate field effect semiconductor device 43. The source region 29' of another insulated gate field effect semiconductor device 41 is further shared with the source region 29' of the adjacent insulated gate field effect semiconductor device 42.

Each of the gate electrodes 20 and 20' is
Gate extraction electrodes and leads are formed in a direction perpendicular to the plane of the paper. Similarly, source region 29,
29' in the direction perpendicular to the plane of the paper,
Moreover, a source region lead electrode and lead are formed parallel to the gate lead electrode and lead.

On the other hand, in the figure, the drain regions 30 of each of the plurality of insulated gate field effect semiconductor devices arranged in a row in the left-right direction are connected to the drain regions 30 of each of the plurality of insulated gate field-effect semiconductor devices arranged in a row in the left-right direction. Each drain region 3 of the insulated gate field effect semiconductor device
electrically isolated from zero. In one row, the drain regions 30 of a plurality of insulated gate field effect semiconductor devices are connected to leads 50 extending in the left-right direction.
are connected. This lead 50 is connected to the interlayer insulating film 6
Formed on the surface of 5.

In this manner, the plurality of insulated gate field effect semiconductor devices are arranged in a matrix structure, forming a close-packed arrangement.

FIG. 6 is a block circuit diagram showing the integrated structure of the insulated gate field effect semiconductor device in the close-packed arrangement. The reference numerals in FIG. 5A correspond to the reference numerals in FIG. 6.

As shown in FIG. 6, in the matrix structure, cells each composed of one insulated gate type field effect semiconductor device are arranged, three in the row direction and four in the column direction.

In FIG. 6, a decoder and driver 73 in the X direction (row) is arranged on the left side. In FIG. 6, a Y-direction (column) decoder and driver 74 are arranged on the upper side.

The vertical cross-sectional structure of the region 72 surrounded by the broken line in FIG. 6 is shown as a vertical cross-sectional view in FIG. 5A.

The block circuit diagram shown in FIG. 6 shows an image sensor. In this image sensor, a substrate 1 having translucency is used.

In the image sensor, an electrical signal obtained from incident light is transferred laterally by control signals of the decoder and drivers 73 and 74, and this transferred signal is output as a detection signal.

For example, in cell (1, 1), light detection is selectively performed by control signals 5 and 75' of the decoder and driver 74, respectively.

Further, in the cell (2, 1), light detection is selectively performed by control signals 76 and 76' of the decoder and driver 74, respectively.

As described above, the channel forming region 27 of the insulated gate field effect semiconductor device is made of a non-single crystal semiconductor. The mobility of this non-single crystal semiconductor is not as high as that of a single crystal semiconductor.

Therefore, for example, a field insulator between a cell (1, 2) constituted by the insulated gate field effect semiconductor device 40 and a cell (2, 2) constituted by another insulated gate field effect semiconductor device. can be abolished.

Furthermore, by eliminating this field insulator,
The number of manufacturing steps can be reduced. Furthermore, since the area occupied by the field insulator is not added to the size of one cell, the size of one cell can be reduced as a result.

When performing photodetection, the image sensor irradiates light directly onto the channel forming region (active semiconductor layer) 27 of the cell from above, rather than from below, to improve the photodetection sensitivity of the cell. It's okay.

(Third Reference Example) In this reference example, a nonvolatile memory is constructed using the insulated gate field effect semiconductor device of this embodiment.

The vertical cross-sectional structure of the insulated gate field effect semiconductor device according to this reference example will be explained using FIG. 5B.

As shown in FIG. 5B, in the nonvolatile memory, insulated gate field effect semiconductor devices 40 and 41 are arranged on the insulating surface of the substrate 1, respectively. Similar to the second reference example, the drain regions 30 of the insulated gate field effect semiconductor devices 40 and 41 are shared. Further, the source region 29 of the insulated gate field effect semiconductor device 40 is shared by the source region 29 of an adjacent insulated gate field effect semiconductor device, and the source region 29' of the insulated gate field effect semiconductor device 41 is further shared by the source region 29 of the adjacent insulated gate field effect semiconductor device. It is shared by the source region 29' of the insulated gate field effect semiconductor device.

The insulated gate field effect semiconductor device 40, 4
1, the gate insulating film 21 includes a charge trapping center layer 91 formed of an insulator, an insulating film 90 surrounding the lower surface of the charge trapping center layer 91, and an upper surface and side surfaces of the charge trapping center layer 91. It is composed of an insulating film 92 surrounding each of the peripheries.

The charge trapping center layer 91 is replaced with an insulating film,
Semiconductors, in particular silicon semiconductor layers with a non-monocrystalline structure (non-monocrystalline semiconductors) or germanium, or metal clusters or thin films may also be used.

In the nonvolatile memory, each insulated gate field effect semiconductor device 40, 41 is configured as a 1-bit memory cell.

In this manner, according to this reference example, an integrated nonvolatile memory can be obtained, similar to a nonvolatile memory having an insulated gate field effect semiconductor device mainly composed of single crystal silicon.

Furthermore, the gate insulating film 21 shown in FIG. 5B is
is the gate insulating film 21 shown in FIG. 3 of the first reference example.
It may be formed in the same manner as the step of forming. That is, the gate insulating film 21 is formed by sequentially stacking a first insulating film 90, a semiconductor layer (charge trapping center layer) 91, and a second insulating film 92, as shown in FIG. 3A. After that, in the step shown in FIG. 3C, the periphery of the side surface of the semiconductor layer 91 is oxidized,
It is formed by forming an insulating film 92 around the side surfaces of this semiconductor layer 91.

Although the embodiments of the present invention have been described in detail above, the present invention is not limited to the above embodiments. Various design changes can be made without departing from the scope of the invention as set forth in the claims.

For example, although the present invention has been described with a focus on silicon semiconductors, instead of this silicon semiconductor,
Si _x C _1-x (0≦x<1) and SiN _4-x (0<x<4) may also be used.

Furthermore, in the present invention, germanium or - group compound semiconductors may be used instead of silicon semiconductors.

As explained above, according to the embodiments of the present invention, the following effects can be obtained.

(1) In an insulated gate field effect semiconductor device,
A step of forming a gate electrode 20 on the insulating surface of the substrate 1, forming a silicon oxide film on the surface of the gate electrode 20 by an oxidation method, and forming a silicon nitride film on the surface of this silicon oxide film, thereby forming a multilayer structure. The method includes a step of forming a gate insulating film 21 having a film structure, and a step of forming a channel forming region 27 made of a non-single crystal semiconductor to which hydrogen is added in close contact with the silicon nitride film of the gate insulating film 21.

With this configuration, since the silicon nitride film is interposed between the silicon oxide film of the gate insulating film 21 and the channel forming region 27, it is possible to prevent a reaction mediated by hydrogen that lowers reliability.

In addition, since a dense silicon oxide film is formed on the surface of the gate electrode 20, even if a pinhole occurs in the silicon nitride film, especially in the corner portion of the gate electrode 20 of the silicon nitride film, the gate electrode 20 and the channel forming region 27 can be prevented. Since the silicon oxide film of the gate insulating film 21 is formed by an oxidation method, it is formed with the same thickness on the top surface, side surfaces, and corner portions of the gate electrode 20, and has the same ability to prevent pinholes in each region. be able to.

(2) In an insulated gate field effect semiconductor device,
One end of the source region 29 and one end of the drain region 30 can be formed at each end of the gate electrode 20 with the gate insulating film 21 interposed therebetween so as to substantially coincide with each other.

(3) In an insulated gate field effect semiconductor device,
By devising the circuit configuration and utilizing the characteristics of non-single crystal semiconductors, the source region 29 or drain region 30 of each of the plurality of insulated gate field effect semiconductor devices can be shared, and the surrounding isolation region can be used in common. Can be reduced.

(4) Due to the effect (2) or effect (3), the integration density of the insulated gate field effect semiconductor device can be improved.

(5) In an insulated gate field effect semiconductor device,
Since the channel length can be shortened, both the gate voltage and the drain voltage can be reduced.

For example, an insulated gate field effect semiconductor device can have a channel length of 1 [μm] to 10 [μm]. In addition, the insulated gate field effect semiconductor device has a gate voltage and a drain voltage of 40% compared to the conventional one.
[V] to 80 [V] to 5 [V] to 10 [V]
It is possible to lower the voltage.

〔Effect of the invention〕

As described above, according to the present invention, the following effects can be obtained.

(1) Although the oxide insulating film obtained by oxidizing the gate electrode itself is thinner than the gate insulating film formed by the deposition method, it is difficult to connect the gate electrode to the channel formation region. There are no pinholes between the two, which prevents leaks.

In addition, the reaction between hydrogen or silicon in the channel forming region and oxygen in the oxide insulating film,
The reaction between the metal of the gate electrode and the channel forming region can be prevented by the multilayer structure of the oxide insulating film and the silicon nitride film formed thereon. Deterioration can be prevented.

(2) In addition to the above effects, a method for manufacturing an insulated gate field effect semiconductor device that can reduce the parasitic capacitance between the gate electrode and the drain region and prevent shorts between the gate electrode and the drain region. can be provided.

(3) In addition to the above-mentioned effects, it is possible to provide a method for manufacturing an insulated gate field effect semiconductor device that can improve the reliability of the film quality and characteristics of the channel forming region.

[Brief explanation of the drawing]

FIG. 1 is a longitudinal cross-sectional view of a conventional semiconductor device. FIG. 2 is a vertical end view of an insulated gate field effect semiconductor device according to an embodiment of the present invention. FIG. 3 is a longitudinal sectional view of an insulated gate field effect semiconductor device which is a first reference example of the present invention. FIG. 4 is a longitudinal sectional view of an insulated gate field effect semiconductor device according to an embodiment of the present invention. FIG. 5A is a longitudinal sectional view of an insulated gate field effect semiconductor device which is a second reference example of the present invention. FIG. 5B is a longitudinal sectional view of an insulated gate field effect semiconductor device according to a third reference example of the present invention. FIG. 6 is a block circuit diagram of an image sensor according to a fourth reference example of the present invention. 1...Substrate, 20, 20'...Gate electrode, 2
1, 21'...gate insulating film, 22, 24, 28
...Mask, 23...Ultraviolet light, 26...Insulating film,
27, 27'... Channel forming region, 29, 2
9'... Source region, 30... Drain region, 4
0, 41, 42, 43... Insulated gate field effect semiconductor device, 200... Gate electrode forming layer, 21
0... Gate insulating film forming layer, 220... Mask forming layer.

Claims (1)

[Claims] 1. A process of forming a gate electrode by patterning a semiconductor or conductor material of one conductivity type on a substrate having an insulating surface, and a process of oxidizing the gate electrode material,
forming an oxide insulating film on the top and side surfaces of the gate electrode; forming a multilayer gate insulating film by covering the oxide insulating film with a silicon nitride film; forming a mask forming layer and a photoresist film on the covered gate electrode; patterning the mask forming layer using the photoresist film formed by exposing the gate electrode from the back surface using the gate electrode as a mask; a step of forming a mask only on the upper surface of the electrode; a step of forming a semiconductor layer doped with impurities on the substrate, a side peripheral edge of the gate insulating film, and the mask; a source region of the semiconductor layer; patterning the semiconductor layer so as to leave a portion that will become the drain region and a portion on the mask, and to make a hole in the portion on the mask; and lifting off the mask to remove the semiconductor layer on the mask. forming a channel forming region in close contact with the silicon nitride film, the source region and the drain region; A method for manufacturing an insulated gate field effect semiconductor device, comprising the steps of: forming a crystalline semiconductor layer;