JPH07109891B2 - Insulated gate type field effect semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate field effect semiconductor device using a non-single crystal semiconductor layer on a substrate having an insulating surface. The present invention is to deposit the non-single-crystal semiconductor layer on a substrate having the insulating surface by a deposition method such as a plasma CVD method and utilize the characteristics of the non-single-crystal semiconductor layer.

In the present specification, the non-single-crystal semiconductor layer includes an amorphous silicon semiconductor, a crystalline silicon semiconductor having a lattice strain, and a polycrystalline silicon semiconductor. Further, in this specification, the non-single-crystal semiconductor layer also includes a semi-amorphous silicon semiconductor included in the amorphous silicon semiconductor. Regarding the above-mentioned semi-amorphous silicon semiconductor, Japanese Patent Application No. 55-26388 (filed on March 3, 1980) filed earlier by the present applicant.
Japan, semi-amorphous silicon semiconductor), Japanese Patent Application No. 54-
No. 58863 (filed May 14, 1979, semiconductor device manufacturing method).

That is, the "semi-amorphous silicon semiconductor" in this specification has the following properties. For example, a semiconductor that is a silicon semiconductor and does not have single crystallinity is formed on the surface of an insulating substrate, which is either a glass substrate or a ceramic substrate such as polycrystalline alumina. The semi-amorphous silicon semiconductor formed on the surface of this insulating substrate is AM1 (100 [mW / c
m ² ]) even when light energy is applied, 1 × 1
An electro-photoconductivity of 0 ⁻³ [1 / ohm cm] to 8 × 10 ⁻² [1 / ohm cm] is obtained. Further, the semi-amorphous silicon semiconductor is 1 × 10 ⁻³ [1 / ohm cm] to 1 × in a substantially intrinsic state.
A dark conductivity of 10 ⁻⁵ [1 / ohm cm] is obtained. The values of photoconductivity and dark conductivity of the semi-amorphous silicon semiconductor are 1/2 to 1 of those of the single crystal silicon semiconductor.
It is / 10. That is, the semi-amorphous silicon semiconductor has extremely excellent characteristics in photoconductivity and dark conductivity.

The excellent characteristics of this semi-amorphous silicon semiconductor have been experimentally found by the present applicant.
Details regarding the excellent properties of semi-amorphous silicon semiconductors are partly published in the following documents. (1) Appl. Phys. Lett. 38 (3),
1981, pp. 142-144. (2) Spring 1981, Japan Society of Applied Physics 1a
S5, "Structural observation and optical / electrical characteristics of a-Si containing microcrystals", p. (3) Autumn 1981, 42nd Annual Meeting of the Society of Applied Physics, 7a-A-1, 7a-A-2, page 403.

[0005]

2. Description of the Related Art FIG. 1 is a vertical sectional view of an insulated gate field effect semiconductor device using an amorphous silicon semiconductor in a conventional example. In FIG. 1, on the insulating substrate 1, the gate electrodes 3 and 13 of the envelope gate type field effect semiconductor device are formed. Each of the gate electrodes 3 and 13 is formed of a heat resistant material such as molybdenum. The gate insulating film 11 formed on the surface of each of the gate electrodes 3 and 13 is formed as a single layer film. As the gate insulating film 11, a silicon oxide film is formed by the CVD method. This silicon oxide film has a thickness of 0.1 [μm]
To 0.5 [μm] in thickness.

Amorphous silicon semiconductors 5 and 10 are formed on the surface of the gate insulating film 11. The amorphous silicon semiconductor 5 is formed only on the gate electrode 3 of the N-channel insulated gate field effect semiconductor device 12. The amorphous silicon semiconductor 10 is
It is formed only on the gate electrode 13 of the P-channel type insulated gate field effect semiconductor device 2. Each of the amorphous silicon semiconductors 5 and 10 is formed by the selective photoetching method. In the N-channel insulated gate field effect semiconductor device 12, each of the N-type semiconductor layers 6 and 7 is formed by selective photoetching. Each of the semiconductor layers 6 and 7 includes a source region 6 and a drain region 7.
Used as each. In the P-channel insulated gate field effect semiconductor device 2, each of aluminum films 8 and 9 formed by a vacuum deposition method is formed by selective photoetching. The aluminum films 8 and 9 are used as the source region 9 and the drain region 8, respectively. In FIG. 1, the CM formed by the P-channel insulated gate field effect semiconductor device 2 and the N-channel insulated gate field effect semiconductor device 12 is shown.
An OSFET (complementary MOSFET) is configured.

[0007]

The following points are not taken into consideration in the above-mentioned N channel type insulated gate field effect semiconductor device 12 (the same applies to the P channel type insulated gate field effect semiconductor device 2). In the N-channel insulated gate field effect semiconductor device 12, the gate insulating film 11 is formed of a single layer of silicon oxide film. Moreover, since the gate insulating film 11 is formed by the deposition method such as the CVD method,
It is difficult to obtain a high-density film quality, and a portion lacking silicon-oxygen reactivity is generated. Therefore, pinholes are easily generated in the gate insulating film 11, and short circuits and leaks due to the pinholes occur between the gate electrode 3 and the amorphous silicon semiconductor 5. In order to prevent the occurrence of this short circuit or leak, the film thickness of the gate insulating film 11 must be increased to, for example, 0.3 [μm] or more.

Further, at the interface between the silicon oxide film as the gate insulating film 11 and the amorphous silicon semiconductor 5, hydrogen existing in each film serves as a catalyst to easily proceed the chemical reaction. For this reason, reliability of the film quality of each of the gate insulating film 11 and the amorphous silicon semiconductor 5 is deteriorated, and the characteristics are also deteriorated. The N-channel insulated gate field effect semiconductor device 12 has, for example, a gate voltage of 20 [V] to 60 [V] because the gate insulating film has to be thick in order to prevent a short circuit and a leak. It is necessary to apply a large drive voltage of That is, the N-channel insulated gate field effect semiconductor device 12 has a so-called 1.5.
It is difficult to realize driving based on a low voltage of [V] to 5 [V].

Further, in the N-channel insulated gate field effect semiconductor device 12, the both ends of the gate electrode 15 in the gate length direction, both ends of the amorphous silicon semiconductor 5, one end of the source region 6 and one end of the drain region 7 are respectively provided. Can not be precisely aligned. That is, since the alignment is performed in the state where the insulating substrate (glass substrate) 1 is warped or shrunk and the insulating substrate 1 is uneven in addition to the mask misalignment in the manufacturing process, the accuracy is within 1 [μm]. At, it is almost impossible to perform the alignment. Therefore, the N-channel insulated gate field effect semiconductor device 12 is required to have a tolerance of 20 [μm] to 30 [μm] in manufacturing.

Therefore, in the N-channel insulated gate field effect semiconductor device 12, the degree of overlap between the gate electrode 15 and the drain region 7 to which a high voltage is applied increases, and with this increase, the drain region 7 is added to the drain region 7. Increased parasitic capacitance. Due to this increase in parasitic capacitance, the drain voltage becomes
It must be raised to 50 [V] to 70 [V]. Further, the parasitic capacitance has a large variation in manufacturing. Therefore, the N-channel insulated gate field effect semiconductor device 12 cannot be used practically.

Further, the N-channel insulated gate field effect semiconductor device 12 is in close contact with the channel forming region having structure sensitivity, that is, the surface of the amorphous silicon semiconductor 5, and the source region 6 and the drain region 7 are respectively formed. It is formed. The source region 6 and the drain region 7 are formed in the source region 6 and the drain region 7, respectively, which are heavily doped with N-type conductivity type impurities in the range of 0.5% to 2%. To be done. Each of the source region 6 and the drain region 7 causes a short circuit between them on the surface of the amorphous silicon semiconductor 5 unless they are completely removed by etching. However, since each of the lower amorphous silicon semiconductor 5, the upper source region 6, and the drain region 7 has the same main component, it is difficult to secure the etching selection ratio.
A short circuit is likely to occur between the source region 6 and the drain region 7.

Further, even after the source region 6 and the drain region 7 are formed on the surface of the amorphous silicon semiconductor 5 and the N-channel type insulated gate type field effect semiconductor device 12 is completed in a later step, the structure shown in FIG.
As shown in, exposed to the air. The amorphous silicon semiconductor 5 has structure sensitivity, and has microcrystallinity especially in an amorphous silicon system. Therefore, the N-channel insulated gate field effect semiconductor device 12 cannot be industrially put into practical use due to low reliability of the film quality and characteristics of the amorphous silicon semiconductor 5 and manufacturing problems with large variations. It was For these reasons, the insulated gate field effect semiconductor device having the structure shown in FIG. 1 was not suitable for industrial use.

The present invention has been made to solve the above problems, and prevents leakage due to pinholes between the gate electrode and the channel forming region, and also prevents the reaction between the channel forming region and silicon. It is an object of the present invention to provide an insulated gate field effect semiconductor device capable of preventing deterioration of the film quality or characteristics of a gate insulating film based on the above.
Further, in addition to the above-mentioned object, the present invention can reduce the parasitic capacitance between the gate electrode and the drain region and prevent short circuit between the gate electrode and the drain region.
An object is to provide an insulated gate field effect semiconductor device. Further, in addition to the above objects, the present invention can improve the reliability of the film quality and characteristics of the channel formation region.
An object is to provide an insulated gate field effect semiconductor device.

[0014]

According to another aspect of the present invention, there is provided an insulated gate field effect semiconductor device including a gate electrode (20) formed on an insulating substrate and the gate which surrounds an upper surface and a side surface of the gate electrode (20). The electrode (20) is plasma-oxidized
A gate insulating film (21) having a multilayer film structure of an insulating oxide film and a silicon nitride film thus formed, and the gate.
Formed by sandwiching the insulating film (21) and the gate electrode (20)
Source region made of a single conductivity type non-single crystal semiconductor
(29) and the drain region (30) and the gate isolation
Edge film (21), source region (29), and drain region
A planar structure in which the upper surface of the area (30) is smooth,
A channel formation region (27) made of a non-single crystal semiconductor to which true or substantially true hydrogen is added is in contact with the planar structure .

Insulated gate type field effect semiconductor device of the present invention
In the planar structure in, the upper surface of the gate insulating film (21) and the upper surfaces of the pair of one conductivity type semiconductor regions forming the source region (29) and the drain region (30) have smooth continuous surfaces .

[0016]

The gate insulating film of the work for the present invention, without performing the formation of a film by deposition, such as CVD method, the surface itself of the gate electrode plasma oxidation, obtained by oxidizing.
Therefore, although the gate insulating film of the present invention can be formed thinner than that formed by the deposition method, a dense film quality can be obtained on the surface of the gate electrode itself. Therefore, the gate insulating film of the present invention reduces pinholes generated between the gate electrode and the channel formation region,
Leakage between the gate electrode and the channel formation region can be prevented.

In order for the channel formation region to be composed of a non-single crystal semiconductor, it is necessary to add hydrogen to make it structure sensitive. However, hydrogen added to the non-single crystal semiconductor and oxygen in the oxide insulating film chemically react with each other, which causes deterioration of the insulated gate field effect semiconductor device.
Therefore, the gate insulating film of the present invention is formed by the plasma oxidation method.
Since a silicon nitride film is formed between the oxide insulating film thus obtained and the non-single-crystal semiconductor as the channel formation region, this silicon nitride film has a multi-layer structure including hydrogen and oxygen. Blocking is performed to prevent a chemical reaction between the gate insulating film and the channel formation region.

The insulated gate film of the present invention has a dense film quality.
Therefore, there is no leakage between the gate electrode and the channel formation region, and the characteristics of the film quality are not deteriorated, so that the device can be formed thin, and thus low voltage driving of the insulated gate field effect semiconductor device can be realized. For example, an insulated gate field effect semiconductor device has been driven at a low gate voltage in the range of 1.5 [V] to 5 [V].

As the gate electrode, P having heat resistance is used.
If the type or N-type impurities using the polycrystalline silicon semiconductor which are added in large amounts (PCS), a silicon oxide film which is oxidized by plasma oxidation method on the upper surface and side surfaces of the gate electrode is formed. Then, a silicon nitride film is formed on the surface of the silicon oxide film, and the gate insulating films made of the silicon oxide film and the silicon nitride film interpolate with each other to form a dense structure without pinholes.

The gate electrode of the present invention comprises a P-type or N-type conductivity type non-single-crystal semiconductor, or a metal conductor or a compound conductor, and these materials are formed by a plasma oxidation method.
Since the gate insulating film is obtained by oxidation by means of oxidation, a dense structure without pinholes can be obtained as compared with the one obtained by the deposition method. Also, to prevent entry of hydrogen from the channel forming region through a multi-layer structure of the gate insulating film and a silicon nitride film.

The gate insulating film is formed on the upper surface and the side surface of the gate electrode, and the source region and the drain region are formed on both sides of the gate electrode with the gate insulating film interposed therebetween. The source region and the drain region are formed by aligning one end of the gate electrode with one end of the source region and the other end of the drain region with one end of the gate electrode. It is formed by self-alignment.

Since there is no overlapping portion between the gate electrode and the source and drain regions, the channel length of the insulated gate field effect semiconductor device is formed to be a short channel. For example, the insulated gate field effect semiconductor device can have a very short channel length of 1 [μm] to 10 [μm]. Since the overlap between the gate electrode and the source and drain regions, especially the drain region, can be reduced, the parasitic capacitance added to the drain region can be reduced and the drain voltage can be reduced. For example, the insulated gate field effect semiconductor device of the present invention has a conventional drain voltage of 40 [V] to 80.
What was [V] could be lowered to the range of 5 [V] to 10 [V].

Further, if the short channel is used, the resistance of the channel forming region can be reduced, so that the insulated gate field effect semiconductor device of the present invention can obtain high frequency characteristics. For example, the insulated gate field effect semiconductor device of the present invention is
In driving at 1.5 [V], a high frequency characteristic of 10 [MHz] to 40 [MHz] was obtained when an amorphous silicon semiconductor having a microcrystalline property was used in the channel formation region. Further, the insulated gate field effect semiconductor device of the present invention uses 10 [MHz] to 30 [MHz] when an amorphous silicon semiconductor is used in the channel formation region.
A high frequency characteristic of [MHz] was obtained.

In the insulated gate field effect semiconductor device of the present invention, the positions thereof are brought close to each other so that the upper surface of the gate electrode is flush with the upper surfaces of the source region and the drain region. That is, in the insulated gate field effect semiconductor device of the present invention, the upper surface of the gate electrode, the upper surface of the source region, and the upper surface of the drain region, which are the bases of the channel formation region, are smoothly continuous, and the planar structure (planarized structure) is obtained. Is formed.

In the insulated gate field effect semiconductor device of the present invention, a source region and a drain region are formed in advance on both ends of the gate electrode, and thereafter, the upper surface of the gate electrode, the upper surface of the source region and the upper surface of the drain region are respectively formed. Since the channel forming region is formed in the channel forming region, the resistance of the source region and the drain region can be controlled independently of the channel forming region. For example, in the insulated gate field effect semiconductor device of the present invention, the source region and the drain region are formed of a P-type or N-type non-single-crystal semiconductor, particularly a polycrystalline silicon semiconductor, so that the electric conduction of the polycrystalline silicon semiconductor is improved. degrees 1 ohms cm ^{- 1]} to 100 ohms c
m ⁻¹ ].

After forming the gate electrode, the source region and the drain region, as the final step, the channel forming region is formed on each of the upper surface of the gate electrode, the upper surface of the source region and the upper surface of the drain region. Even when is formed of an intrinsic or P-type or N-type non-single-crystal semiconductor having structure sensitivity, it is possible to reduce deterioration of the film quality and change of characteristics due to heat treatment during manufacturing as much as possible. The thickness of the non-single-crystal semiconductor used as the channel forming region is, for example, in the range of 0.05 [μm] to 5 [μm], and typically 0.1 [μm] to 1
A thickness of [μm] is used.

[0027]

EXAMPLES Examples of the present invention will be described below. (First Embodiment) FIG. 2 is a vertical end view of an insulated gate field effect semiconductor device according to the first embodiment of the present invention. FIG. 3 is a vertical sectional view of an insulated gate field effect semiconductor device according to the second embodiment of the present invention. FIG. 4 is a vertical sectional view of an insulated gate field effect semiconductor device which is a third embodiment of the present invention. FIG. 5A is a vertical sectional view of an insulated gate field effect semiconductor device according to a fourth embodiment of the present invention. FIG. 5B is a vertical sectional view of an insulated gate field effect semiconductor device which is a fifth embodiment of the present invention. FIG. 6 is a block circuit diagram of an image sensor according to a fourth embodiment of the present invention. In FIG. 2, of the total manufacturing steps from the substrate preparation step to the step of completing the insulated gate field effect semiconductor device, the former manufacturing method from the substrate preparation step to the step of forming the gate insulating film will be described. First, as shown in FIG. 2A, a substrate 1 having an insulating surface is prepared. Then, as shown in FIG. 2A, the gate electrode 20, the gate insulating film 21, and the mask forming layer (protective layer) 220 are sequentially formed on the insulating surface of the substrate 1.

As the substrate 1, a quartz glass substrate having an insulating property and a light transmitting property is used. Also, the substrate 1
For this, an insulating ceramic substrate is used. The gate electrode 20 is formed by a plasma vapor phase method. That is, the gate electrode 20 is formed of a non-single-crystal semiconductor deposited on the insulating surface (formation surface) of the substrate 1 by the plasma vapor phase method. In the plasma vapor phase method, silane (monosilane or polysilane) or silicon fluoride is used as the reactive gas. Helium or hydrogen is used as a carrier gas for diluting the reactive gas. In the plasma vapor phase method, first, a reactive gas is diluted with a carrier gas, the reactive gas and the carrier gas are introduced into a reaction furnace, and the reactive gas and the carrier gas are turned into plasma in the reaction furnace to generate the reactive gas. Is decomposed and reacted to form a non-single crystal semiconductor on the insulating surface of the substrate 1.

The plasma vapor phase method uses 0.01 [tor]
r] to 10 [torr], for example 0.3 [tor]
The pressure in the reaction furnace is set to r]. The substrate 1 placed in the reaction furnace is heated to 100 [° C.] to 400 [° C.], for example 300 [° C.]. The reactive gas and the carrier gas are converted into plasma by direct current or 500 [KH
z] to 50 [MHz], for example 13.5 [MHz]
It is performed by arc discharge or glow discharge by the high frequency of. Further, the plasma conversion is performed by applying the direct current or the high frequency to 1 [GHz] to 10 [GHz], for example, 2.
The electromagnetic energy of the microwave of 45 [GHz] is 5 [W]
Alternatively, the discharge may be performed by arc discharge or glow discharge applied as an output of 200 [W]. By the plasma vapor phase method under such conditions, an intrinsic or substantially intrinsic non-single-crystal semiconductor having microcrystallinity is formed on the insulating surface of the substrate 1. This non-single crystal semiconductor is, for example, 0.
It is formed with a thickness of 1 [μm] to 1 [μm].

As is apparent from the completed view shown in FIG. 4C, the current flowing between the source region 29 and the drain region 30 flows in the direction parallel to the insulating surface of the substrate 1. Therefore, in this example, when the non-single crystal semiconductor is produced, the insulating surface of the substrate 1 is arranged in parallel with the surface of the electrode of the glow discharge or the arc discharge, and the electric conductivity in the lateral direction is set to be large. In the reactor of the same plasma CVD apparatus used in this example, the non-single crystal semiconductor is
Although it depends on the generation temperature, for example, in the case of a microwave output of 5 [W] to 20 [W], it is formed as an amorphous silicon semiconductor. Further, the non-single-crystal semiconductor is formed as an amorphous silicon semiconductor having microcrystallinity which is an intermediate region, that is, a semi-amorphous silicon semiconductor in the case of a microwave output of 20 [W] to 50 [W].

Further, the non-single crystal semiconductor is formed as a polycrystalline silicon semiconductor in the case of a microwave output of 80 [W] to 200 [W]. Furthermore, the non-single crystal semiconductor has a generation temperature of 400 [° C.] or higher and 50 [W].
In the case of the above microwave output, it is formed as a polycrystalline silicon semiconductor. The amorphous silicon semiconductor is
Has short-range ordering (some form of regularity) but no crystallinity. In addition, an amorphous silicon semiconductor having a microcrystalline property, that is, a semi-amorphous silicon semiconductor is 5 [Å] to 1
It has microcrystallinity with a lattice strain of the order of 00 [Å] short range.

Each of these amorphous silicon semiconductors and semi-amorphous silicon semiconductors contains 0.01 [mol%] or less of a recombination center neutralizing agent with a halogen element such as hydrogen or fluorine for neutralizing dangling bonds of silicon. 5
[Mole%] is added. Further, in the semi-amorphous silicon semiconductor, in order to neutralize dangling bonds that cannot be offset by the neutralizing agent, an alkali metal such as lithium, sodium, or potassium is used in an amount of 1%.
The radiation resistance frequency characteristics may be improved by adding it at a concentration of 0 ¹⁴ [cm ⁻³ ] to 10 ¹⁸ [cm ⁻³ ]. In the semi-amorphous silicon semiconductor,
1 × 10 ⁻⁶ [1 / ohm cm] to 3 × 10
The dark conductivity of ⁻³ [1 / ohm cm] is 1 × 10 ⁻³ [1 / ohm cm] to 8 × 10 under the condition of AM1.
^A photoconductivity of ⁻² [1 / ohm cm] was obtained experimentally.

The amorphous silicon semiconductor has 1
The dark conductivity of 0 ⁻¹⁰ [1 / ohm cm] to 10 ⁻⁶ [1 / ohm cm] is 10 ⁻⁶ [1 / ohm cm] to 3 × 10 ⁻⁴ [1 / ohm cm]. Were experimentally obtained, respectively. Each of these amorphous silicon semiconductors and semi-amorphous silicon semiconductors is practically used according to the application. When a non-single-crystal semiconductor is formed as a P-type or N-type conductive semiconductor layer as the gate electrode 20, in the plasma vapor phase method, a III-valent impurity or a V-valent impurity is added to the reactive gas. To be As the III-valent impurity, for example, diborane (B ₂ H ₆ ) is used. Diborane is added in a ratio of 0.2% to 2% with respect to silane which is a reactive gas. As the V-valent impurity, phosphine (PH ₃ ) is used, for example. Phosphine is added in a ratio of 0.2% to 2% with respect to silane.

The P-type or N-type conductive semiconductor layer is not formed as an amorphous silicon semiconductor, but is formed as a semi-amorphous silicon semiconductor or a polycrystalline silicon semiconductor. Each of these semi-amorphous silicon semiconductors and polycrystalline silicon semiconductors has an electric conductivity of 0.1 to 100 [1 / ohm cm] and an activation energy of 0.02 [eV]. Can all be acceptors or donors. Note that the non-single crystal semiconductor may be formed by using a low pressure vapor phase method. as a result,
The gate electrode 20 of this embodiment is formed of a P + type or N + type conductivity type semiconductor layer, that is, a semi-amorphous silicon semiconductor or a polycrystalline silicon semiconductor. The film thickness of the gate electrode 20 is formed in the range of 0.1 [μm] to 0.5 [μm]. The gate length of the gate electrode 20 is 1 [μm] to 30 [μm], typically 5 [μm] to 10 [μm]. The patterning of the gate electrode 20 is performed by an etching method using a mask formed by a photolithography technique.

The gate electrode 20 may be formed of a heat resistant metal conductor such as molybdenum or tungsten, or a heat resistant metal silicide conductor such as molybdenum silicide or tungsten silicide. The gate insulating film 21
Is composed of an oxide film of a gate electrode material formed on the upper and side surfaces of the gate electrode 20, and a multilayer film of a nitride film formed on the surface of this oxide film. The oxide film of the gate insulating film 21 is formed by a thermal oxidation method or a plasma oxidation method. That is, in this embodiment, since the gate electrode 20 is formed of either a semi-amorphous silicon semiconductor or a polycrystalline silicon semiconductor, the oxide film is formed of a silicon oxide film. This silicon oxide film is, for example, 1
It is formed with a film thickness of 0 [nm] to 100 [nm].

The silicon nitride film is, for example, 200 [° C.].
Formed in microwave-excited ammonia in a state of being heated to 1100 ° C. The silicon nitride film is formed to have a film thickness of, for example, 2 [nm] to 5 [nm]. Further, the silicon nitride film may be formed using a reduced pressure vapor phase method to have a film thickness of, for example, 10 [nm] to 150 [nm]. In this way, the gate insulating film 21
Is formed of a multi-layer structure including a silicon oxide film obtained by oxidizing the surface of the gate electrode 20 and a silicon nitride film formed on the surface of the silicon oxide film. Each of the silicon oxide film and the silicon nitride film of the gate insulating film 21 is selectively formed on the upper surface and the side surface of the gate electrode 20. As a result, the gate insulating film 21 has few pinholes in the silicon oxide film itself. In particular, it is extremely unlikely that pinholes will be generated at the same place on each of the silicon oxide film and the silicon nitride film. That is, in the gate insulating film 21 of the present embodiment, the generation of pinholes is reduced as compared with the gate insulating film having a single layer structure formed by the vapor phase method.

When the gate insulating film 21 is formed of a conventional single-layered silicon nitride film and the silicon nitride film is formed by the low pressure vapor phase method, the coverage of the corner portion of the gate electrode 20 is reduced. Since it is bad, pinholes are easily generated in this part, which causes leakage. In this respect as well, the gate insulating film 21 of the present embodiment is equivalent to the gate electrode 20.
Since a silicon oxide film with extremely few pinholes is previously formed on the surface of the gate electrode by an oxidation method, leakage between the gate electrode 20 and a channel formation region 27 (see FIG. 4B) formed later is prevented. You can In addition, the silicon nitride film forming the gate insulating film 21 has a property of not passing hydrogen. That is, the silicon nitride film forming the gate insulating film 21 blocks the passage of hydrogen between the silicon oxide film below the gate insulating film 21 and the channel forming region 27 formed on the surface of the gate insulating film 21. To be done.

Even when there are no pinholes in the silicon oxide film forming the gate insulating film 21, oxygen, which is a constituent element of the silicon oxide film, is converted into silicon containing hydrogen forming the channel forming region 27. If they come into direct contact with each other, they react with each other and cause deterioration of the film quality and characteristics of the silicon oxide film. That is, since the silicon nitride film forming one layer of the gate insulating film 21 blocks hydrogen and oxygen, the deterioration of the film quality of the silicon oxide film forming the other layers of the gate insulating film 21 is prevented. You can The mask forming layer 220 formed on the surface of the gate insulating film 21 is formed of a silicon oxide film deposited by a low pressure vapor phase method or a heat resistant polyimide resin (PIQ) film applied by a spin coating method. The silicon oxide film or the heat-resistant polyimide resin film as the mask forming layer 220 has a thickness of 0.5 [μm] to 3 [μm], typically 0.1 [μm] to 1.5 [μm]. Form.

Next, as shown in FIG. 2B, a photoresist film (not shown) is applied to the entire surface of the mask forming layer 220. Then, this photoresist film is patterned to form a mask 24 from the photoresist film. A negative photoresist film is used as the photoresist film. The photoresist film is exposed to ultraviolet rays 23 from the lower side of the substrate 1 and exposed using the gate electrode 20 as a mask. That is, when the photoresist film is subjected to the developing process and the rinsing process after the exposure, it is exposed to the gate electrode 20.
Is left as the mask 24 only on the upper surface, and the other regions are removed. Moreover, the mask 24 is formed by self-alignment with the gate electrode 20.

Next, as shown in FIG. 2C, the mask 2
4, the mask forming layer 220 is patterned, and the mask 22 is formed from the mask forming layer 220. Then, the mask 24 is removed. When a silicon oxide film is used as the mask forming layer 220, patterning is performed by ablation using a hydrofluoric acid-based etchant. When a heat-resistant polyimide resin film is used as the mask forming layer 220, patterning is performed by evaporating with a hydrazine-based etching solution. The mask 22 is formed in self alignment with respect to the gate electrode 20 because the mask 24 for patterning the mask 22 is formed in self alignment with the gate electrode 20. As shown in FIG. 2C, according to this embodiment, the upper surface 25 and the side surface of the gate electrode 20 formed on the insulating surface of the substrate 1 are surrounded by the gate insulating film 21. Further, the upper surface 25 of the gate electrode 20 has a structure in which masks 22 of the same shape which are substantially aligned with both ends of the gate electrode 20 are formed.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to the vertical sectional view of FIG. The present embodiment is a method of forming the gate electrode 20 and the mask 22 by using one mask 24 as in the manufacturing method of the first embodiment. It is a method of being exposed.
First, as shown in FIG. 3A, the substrate 1 is prepared, and the gate electrode forming layer 200, the gate insulating film forming layer 210, and the mask forming layer 220 are sequentially formed on the insulating surface of the substrate 1. Next, as shown in FIG. 3A, the mask 24 is selectively formed on the surface of the mask forming layer 220. As the substrate 1, a quartz glass substrate or a ceramic substrate is used as described above.

As the gate electrode forming layer 200, a non-single crystal semiconductor, for example, a P-type or N-type conductivity type semiconductor layer is used as described above. In addition, the gate electrode formation layer 2
For 00, a heat resistant metal conductor or a heat resistant metal silicide conductor is used. The gate insulating film forming layer 210 is, as described above, a silicon oxide film (or a metal oxide film) formed by oxidizing the surface of the gate electrode forming layer 200, and a nitride film formed on the surface of the silicon oxide film. It has a multi-layered structure including a silicon film. A silicon oxide film or a heat-resistant polyimide resin film is used for the mask forming layer 220, as described above.

For the mask 24, the photoresist film coated on the entire surface of the mask forming layer 220 by the spin coating method is sequentially subjected to the exposure process, the development process, and the rinse process, and the size of the gate electrode 20. And patterned. The photoresist film may be either negative or positive (active type). To expose the photoresist film, ultraviolet rays are applied from above the substrate 1. Next, as shown in FIG. 3B, using the mask 24, the mask forming layer 220, the gate insulating film forming layer 210, and the gate electrode forming layer 200 are sequentially patterned to form the mask 22 and the gate insulating film 21. And the gate electrode 20 is formed. That is, the mask 22,
Each of the gate insulating film 21 and the gate electrode 20 is patterned using one mask 24 as a reference and is formed by self-alignment with the mask 24.

Next, the mask 24 is removed. Then, as shown in FIG. 3C, an insulating film 26 is formed on the exposed side surface of the gate electrode 20. The insulating film 2
Similar to the gate insulating film 21, 6 has a multilayer film structure including a silicon oxide film and a silicon nitride film formed on the surface of this silicon oxide film. The silicon oxide film of the insulating film 26 is formed by a thermal oxidation method or a plasma oxidation method. The oxidation temperature by the plasma oxidation method is 100 [° C.] to 300
In the range of [° C.], a heat resistant polyimide resin film can be used as the mask 22. Also, the oxidation temperature is 600
A silicon oxide film formed by the CVD method is used as the mask 22 because the heat resistance is exceeded in the range of [° C.] or higher, particularly in the range of 1000 [° C.] to 1150 [° C.] used for manufacturing.

The silicon nitride film forming the insulating film 26 is
It is formed by the plasma nitriding method. When this plasma nitriding method is performed, the exposed surface of the mask 24 is also nitrided,
This nitride film can be easily removed in a later process. According to the present embodiment, as shown in FIG.
Similar to the first embodiment, the gate electrode 20 formed on the insulating surface of the substrate 1 has an upper surface surrounded by the gate insulating film 21 and side surfaces surrounded by the insulating film 26. In addition, a mask 22 having the same shape is formed on the upper surface of the gate electrode 20 so as to be substantially aligned with both ends of the gate electrode 20.

Further, in this embodiment, as shown in FIG.
After forming the mask 22 shown in FIG.
Side mask 2 may be selectively etched to form the mask 22 in a slim shape. The mask 22 formed in the slim shape is formed by a post-process (see FIG. 4C of the third embodiment).
In the reference), the removal by the lift-off method can be easily performed. Further, in the present embodiment, the film thickness of each of the gate insulating film 21 on the upper surface of the gate electrode 20 and the insulating film 26 on the side surface can be independently controlled. That is, the gate insulating film 21
Is thin, for example, 10 [nm] to 100 [n
If the thickness is set to m], the insulated gate field effect semiconductor device can be driven at a low voltage. On the other hand, the insulating film 26 has a large thickness, for example, 200 [nm] to 400 [n
If the film thickness is set to m], the parasitic capacitance generated between the gate electrode 20 and especially the drain region 30 can be reduced.

(Third Embodiment) In this embodiment, the manufacturing method from the step of forming the gate insulating film 21 to the step of completing the insulated gate field effect semiconductor device will be described with reference to the vertical sectional view of FIG. Explain.
This embodiment will be described from the steps after the step shown in FIG. 3C which is the second embodiment. The manufacturing method of the present embodiment is the same even if it is performed from the step after the step shown in FIG. 2C of the first embodiment. FIG. 3C showing the second embodiment.
Process, ie, the gate electrode 20 and the gate insulating film 2
After the step of forming the mask 1, the mask 22 (first mask), and the insulating film 26, as shown in FIG. 4A, the semiconductor layer 270 and the mask 28 (second mask) are sequentially formed. .

The semiconductor layer 270 is formed so as to cover the surfaces of the mask 22, the insulating film 26, etc., that is, at least the portions where the source region 29 and the drain region 30 are formed at both ends of the gate electrode 20, respectively. .
The semiconductor layer 270 is formed by the same formation method as the gate electrode 20. The semiconductor layer 270 is added with an N-type impurity in the case of an N-channel type insulated gate field effect semiconductor device and with a P-type impurity in the case of a P-channel type insulated gate field effect semiconductor device. The semiconductor layer 270 is formed with a film thickness of 0.1 [μm] to 0.5 [μm]. The mask 28 is formed on the semiconductor layer 2 at the portion where the source region 29 and the drain region 30 are formed.
It is formed on the surface of 70. In this mask 28, a hole 37 is formed in a portion where the mask 22 is formed, that is, a portion where the gate electrode 20 is formed. Mask 28
Is formed of a photoresist film.

Next, using the mask 28, the semiconductor layer 270 is selectively patterned. Then, the source region 29 and the drain region 30 are formed on the remaining semiconductor layer 270, respectively. Then, the mask 28 is removed. Next, the source region 29 and the drain region 30 are each used as a mask, and in particular, a portion of the mask 28 patterned with reference to the holes 37 is used as a mask, and the mask 22 is ablated. When the mask 22 is ablated, the ablated portion becomes a hole. When the silicon oxide film is used, the mask 22 is removed by a hydrofluoric acid-based etching solution. Further, the mask 22 is removed by evaporation with a hydrazine-based etching solution when a heat resistant polyimide resin film is used.

When the mask 22 is melted off,
Light ultrasonic vibration is applied in combination with etching.
The adhesive strength between the mask 22 and the underlying surface of the gate insulating film 21 is weaker than the adhesive strength between the source region 29 and its underlying surface and the adhesive strength between the drain region 30 and its underlying surface. Therefore, the mask 22 is entirely removed by the combined use of ultrasonic vibration. in this way,
Since the mask 22 is selectively removed, the mask 22 is eventually removed by the lift-off method.

The above-mentioned source region 29 and drain region 30 are formed separately at both ends of the gate electrode 20, respectively. Further, the source region 29 and the drain region 30 are formed as a pair of impurity regions. One side surface of each of the source region 29 and the drain region 30 on the gate electrode 20 side is covered with the insulating film 26 (first
In the case of the embodiment, it is adjacent to the side surface of the gate electrode 20 via the gate insulating film 21). That is, the gate electrode 20
One side surface of the source region 29
It is formed so as to be substantially in agreement with one side surface. Similarly, the other side surface of both side surfaces of the gate electrode 20 is formed so as to substantially coincide with one side surface of the drain region 30.
As a result, each of the source region 29 and the drain region 30 is formed in self-alignment with the gate electrode 20. Moreover, the manufacturing alignment between the gate electrode 20 and the source region 29 and the drain region 30 is
Substantially one mask 22 (first mask) is used.

Further, this mask 22 is formed on the basis of one mask 24 as described in the above-mentioned first embodiment (see FIG. 2), and is formed by self-alignment with respect to this mask 24. . Through the steps up to this point, the gate electrode 20, the gate insulating film 21, the insulating film 26,
The source region 29 and the drain region 30 are formed.
As described above, the gate insulating film 21 is formed on the upper surface of the gate electrode 20. The insulating film 26 is formed on the side surface of the gate electrode 20. Source region 29 and drain region 3
Each of 0s is formed by the semiconductor layer 270 which is intrinsic according to the plasma vapor phase method shown in the first embodiment, or is substantially intrinsic but has conductivity type and structure sensitivity. Each of the source region 29 and the drain region 30 is formed in close contact with each of the gate insulating film 21 and the insulating film 26, particularly the silicon nitride film.

Further, each of the source region 29 and the drain region 30 is formed on the insulating surface of the substrate 1 at both ends of the gate electrode 20. next,
As shown in FIG. 4B, a channel forming region 27 is formed on the upper surface of each of the gate electrode 20, the source region 29 and the drain region 30. Channel formation region 2
7 is formed on the upper surface of the gate electrode 20 via the gate insulating film 21. In addition, the channel forming region 27 is formed in direct contact with the upper surfaces of the source region 29 and the drain region 30, respectively. The channel forming region 27 is shown in FIG.
Patterning is performed using the photomask (third mask) shown in FIG. The channel forming region 27 is preferably formed of a semi-amorphous silicon semiconductor layer having microcrystalline properties. The channel formation region 27 formed of this semi-amorphous silicon semiconductor layer can realize high-speed operation of the insulated gate field effect semiconductor device.

The photomask (third mask)
An insulating film may be formed on the surface of the channel formation region 27 before the patterning by. This insulating film can prevent deterioration of the characteristics of the channel formation region 27. Also,
The patterning with the photomask (third mask) can simultaneously remove the end portion of the gate insulating film 21 on the upper surface of the gate electrode 20, and together with the source region extraction electrode 38 and the drain region extraction electrode 39, the gate extraction electrode 36.
Is formed. By performing the above steps, the insulated gate field effect semiconductor device is formed on the insulating surface of the substrate 1 using the three masks, that is, the first mask, the second mask, and the third mask. Moreover, the insulated gate field effect semiconductor device has a planar structure.

Next, as shown in FIG. 4C, the interlayer insulating film 6 is formed on the upper surface of the insulated gate field effect semiconductor device.
5 is coated. Then, the interlayer insulating film 65
An electrode hole 66 is formed in the. After that, the electrodes 67, 68
And 69 are formed. The interlayer insulating film 65 uses, for example, a heat resistant polyimide resin. The electrode 69 is connected to the source region extraction electrode 38 at the contact portion 41. The electrode 67 is connected to the drain region extraction electrode 39 at the contact portion 40. The electrode 68 is connected to the gate extraction electrode 36.

As described above, the substrate 1 is used in this embodiment.
A step of forming a gate electrode 20 on the insulating surface of, a step of forming a gate insulating film 21 surrounding the gate electrode 20,
A step of forming a pair of source region 29 and drain region 30 in a planar structure that is self-aligned with the gate electrode 20 and is in close contact with the insulating surface of the substrate 1, in the final step, from the semiconductor layer having the most structure sensitivity to the channel forming region. 27 is provided. The insulated gate field effect semiconductor device is obtained by sequentially performing the above steps.

In the above process, an insulated gate field effect semiconductor device having a planar structure can be obtained with three photomasks (first mask, second mask, and third mask).
Further, by adding two photomasks (masks for forming the pattern and in FIG. 4C) to the above process, the two-layer wiring in the insulated gate field effect semiconductor device is adopted. In addition, the insulated gate field effect semiconductor device (also referred to as a thin film transistor)
Gate electrode 20, source region 29, drain region 30 of
Since each of them is formed by self-alignment with respect to the mask 24, the channel length of the insulated gate field effect semiconductor device can be reduced to the range of 1 [μm] to 10 [μm]. Further, in the insulated gate field effect semiconductor device, since the amorphous silicon semiconductor having a microcrystalline property is used for the channel forming region 27 and a lateral current can be passed, the frequency characteristic can be improved. For example,
When an 11-stage ring oscillator is prototyped with an insulated gate field effect semiconductor device, 10 [MHz] to 100
The frequency characteristic of [MHz] was obtained.

(Fourth Embodiment) This embodiment uses the insulated gate field effect semiconductor device of the third embodiment to obtain the maximum packaging density. A vertical cross-sectional structure of the insulated gate field effect semiconductor device according to this embodiment will be described with reference to FIG. In this embodiment, as shown in FIG. 5A, one insulated gate field effect semiconductor device 40 is provided on the insulating surface of the substrate 1.
And another insulated gate field effect semiconductor device 41 are arranged adjacent to each other. No isolation region is provided between each of the insulated gate field effect semiconductor devices 40 and 41. The one insulated gate field effect semiconductor device 40 is composed of a gate electrode 20, a gate insulating film 21, a source region 29, a drain region 30, and a channel formation region 27. Another insulated gate field effect semiconductor device 41 is a gate electrode 20 ′, a gate insulating film 21 ′, a source region 29 ′, a drain region 3
0 and a channel forming region 27 '.

The drain region 30 of the one insulated gate field effect semiconductor device 40 is shared with the drain region 30 of the other insulated gate field effect semiconductor device 41. Similarly, the source region 29 of one insulated gate field effect semiconductor device 40 is also shared with the source region 29 of the adjacent insulated gate field effect semiconductor device 43. Source region 29 'of another insulated gate field effect semiconductor device 41
Is an insulated gate field effect semiconductor device 4 next to
It is shared with the second source region 29 '. Then, on each of the gate electrodes 20 and 20 ', a gate extraction electrode and a lead are formed in a direction perpendicular to the paper surface. Similarly,
In each of the source regions 29 and 29 ', a source region extracting electrode and a lead are formed in a direction perpendicular to the paper surface and in parallel with the gate extracting electrode and the lead.

On the other hand, in the figure, the drain regions 30 of a plurality of insulated gate field effect semiconductor devices, which are illustrated in the left-right direction, respectively, are arranged in other columns adjacent to each other in the direction perpendicular to the plane of the drawing. Is electrically isolated from each drain region 30 of the other insulated gate field effect semiconductor device. In one row, the drain regions 30 of the plurality of insulated gate field effect semiconductor devices are connected by the leads 50 extending in the left-right direction. The leads 50 are formed on the surface of the interlayer insulating film 65. In this way, the plurality of insulated gate field effect semiconductor devices are arranged in a matrix structure and form a close-packed mounting arrangement.

FIG. 6 is a circuit block diagram showing an integrated structure of the insulated gate field effect semiconductor device having the closest packing arrangement. The reference numeral attached to FIG.
It corresponds to the reference numeral given in FIG. As shown in FIG. 6, the matrix structure has three rows and four columns.
A total of 12 cells, each of which is composed of an insulated gate field effect semiconductor device, are arranged. In FIG. 6, the decoder and driver 73 in the X direction (row) are arranged on the left side.
In FIG. 6, a decoder and driver 74 in the Y direction (column) are arranged on the upper side. Area 7 surrounded by a broken line in FIG.
The vertical sectional structure of No. 2 is shown as a vertical sectional view in FIG.

The circuit block diagram shown in FIG. 6 shows an image sensor. As this image sensor, a substrate 1 having translucency is used. In the image sensor, the electric signal obtained by the incident light is laterally transferred by the control signals of the decoder and the drivers 73 and 74, and the transferred signal is output as a detection signal. For example, in the cell (1, 1), photodetection is selectively performed by the control signals 75 and 75 'of the decoder and driver 74, respectively. In the cell (2, 1), the decoder and driver 74
The light detection is selectively performed by the control signals 76 and 76 '.

As described in each of the first to third embodiments, the channel forming region 27 of the insulated gate field effect semiconductor device is made of a non-single crystal semiconductor. The mobility of this non-single crystal semiconductor is not as high as that of the single crystal semiconductor. Therefore, for example, the field insulator between the cell (1, 2) composed of the insulated gate field effect semiconductor device 40 and the cell (2, 2) composed of another insulated gate field effect semiconductor device is eliminated. it can. Furthermore, the number of manufacturing steps can be reduced by the elimination of this field insulator. Further, since the occupied area of the field insulator is not added to one cell size, one cell size can be reduced as a result. When performing photodetection, the image sensor directly irradiates the channel formation region (active semiconductor layer) 27 of the cell from above, not from below, to improve the photodetection sensitivity of the cell. May be.

(Fifth Embodiment) In this embodiment, a nonvolatile memory is constructed by using the insulated gate field effect semiconductor device of the third embodiment. A vertical cross-sectional structure of the insulated gate field effect semiconductor device according to this embodiment will be described with reference to FIG.
As shown in FIG. 5B, the non-volatile memory has an insulated gate field effect semiconductor device 40, 4 on the insulating surface of the substrate 1.
Each of the 1 is arranged. Similar to the fourth embodiment,
The drain regions 30 of the insulated gate field effect semiconductor devices 40 and 41 are shared. Further, the source region 29 of the insulated gate field effect semiconductor device 40 is shared by the source region 29 of the adjacent insulated gate field effect semiconductor device, and the source region 29 ′ of the insulated gate field effect semiconductor device 41 is further adjacent. It is also used as the source region 29 'of the insulated gate field effect semiconductor device.

Insulated gate type field effect semiconductor device 4
In each of 0 and 41, the charge trapping central layer 91 in which the gate insulating film 21 is formed of an insulator, and the charge trapping central layer 9
1. An insulating film 90 surrounding the lower surface of No. 1 and a charge trapping central layer 91
Is formed of an insulating film 92 that surrounds the upper surface and the side surface of the device. Instead of an insulating film, the charge trapping central layer 91 may be made of a semiconductor, in particular, a silicon semiconductor having a non-single crystal structure (non-single crystal semiconductor), germanium, or a metal cluster or thin film. The nonvolatile memory includes one insulated gate field effect semiconductor device 4
Each of 0 and 41 is configured as a 1-bit memory cell.

As described above, according to this embodiment, an integrated nonvolatile memory can be obtained as in the nonvolatile memory having the insulated gate field effect semiconductor device mainly composed of single crystal silicon. Further, the gate insulating film 21 shown in FIG. 5B may be formed in the same manner as the step of forming the gate insulating film 21 shown in FIG. 3 of the second embodiment. That is, in the gate insulating film 21, first, the first insulating film 90, the semiconductor layer (charge trapping central layer) 91, and the second insulating film 92 are sequentially laminated in the same manner as shown in FIG. 3A. Then, in the step shown in FIG. 3C, the side surface of the semiconductor layer 92 is oxidized and an insulating film is formed around the side surface of the semiconductor layer 92.

Although the embodiments of the present invention have been described in detail above, the present invention is not limited to the above embodiments. And
Various design changes may be made without departing from the invention as set forth in the claims. For example, although the present invention has been mainly described with respect to a silicon semiconductor, the silicon semiconductor is replaced with Si _x C _1-x (0
≦ x <1), SiN _4-x (0 <x <4) may be used. Further, in the present invention, a germanium or a group III-V compound semiconductor may be used instead of the silicon semiconductor.

As described above, according to the embodiment of the present invention, the following effects can be obtained. The insulated gate field effect semiconductor device includes a gate electrode 20 formed on the insulating surface of the substrate 1, a silicon oxide film formed on the surface of the gate electrode 20 by an oxidation method, and a silicon oxide film formed on the surface of the silicon oxide film. A gate insulating film 21 having a multilayer film structure including the formed silicon nitride film.
And a channel forming region 27 made of a non-single-crystal semiconductor in which hydrogen is added in close contact with the silicon nitride film of the gate insulating film 21. With this configuration, the gate insulating film 2
Since the silicon nitride film is interposed between the silicon oxide film of No. 1 and the channel forming region 27, it is possible to prevent the reaction of reliability deterioration mediated by hydrogen.

Further, since the dense silicon oxide film is formed on the surface of the gate electrode 20, even if a pinhole is generated in the corner portion of the silicon nitride film, especially the gate electrode 20 of the silicon nitride film, the gate electrode 20 is not formed. A short circuit with the channel forming region 27 can be prevented. Since the silicon oxide film of the gate insulating film 21 is formed by the oxidation method, it is formed with the same thickness on any of the upper surface, the side surface, and the corner portion of the gate electrode 20, and has the same ability to prevent pinholes in any of them. be able to.

The insulated gate field effect semiconductor device is formed such that one ends of the source region 29 and the drain region 30 are substantially aligned with both ends of the gate electrode 20 with the gate insulating film 21 interposed therebetween. The insulated gate field effect semiconductor device can share the source region 29 or the drain region 30 of each of the plurality of insulated gate field effect semiconductor devices by devising the circuit configuration and utilizing the characteristics of the non-single crystal semiconductor. Moreover, the surrounding isolation region can be reduced. By sharing the source region 29 and the drain region 30, the integration density of the insulated gate field effect semiconductor device can be improved.

Since the insulated gate field effect semiconductor device has a plane structure in which the end of the gate electrode is in contact with the ends of the source region and the drain region through the gate insulating film, the channel length can be formed to be a short channel. Therefore, both reduction of the gate voltage and reduction of the drain voltage can be realized. For example, the insulated gate field effect semiconductor device can have a channel length of 1 [μm] to 10 [μm]. Further, in the insulated gate field effect semiconductor device, both the gate voltage and the drain voltage can be lowered from the conventional 40 [V] to 80 [V] to 5 [V] to 10 [V].

[0072]

According to the present invention, since the gate insulating film has a multi-layered structure including an oxide film oxidized by the plasma oxidation method of the gate electrode itself and a silicon nitride film formed on the surface thereof, the gate electrode It is possible to prevent leakage due to pinholes between the channel formation region and the channel formation region, and at the same time prevent deterioration of the film quality or characteristics of the gate insulation film due to the reaction between hydrogen in the channel formation region and oxygen in the gate formation film. An insulated gate field effect semiconductor device can be provided. According to the present invention, the gate electrode itself made of a P-type or N-type conductivity type non-single-crystal semiconductor, or a metal conductor or a compound conductor is a gate insulating film oxidized by a plasma oxidation method. Compared with the gate insulating film obtained by the deposition method, a dense film without pinholes can be obtained, and the multi-layer structure with the silicon nitride film makes it sensitive to oxygen in the gate insulating film. The bond with hydrogen in the formed channel formation region layer was eliminated. According to the invention,
Since the end of the source region is aligned with one of the ends of the gate electrode through the gate insulating film and the end of the drain region is aligned with the other of the gate electrode, a smooth continuous surface is formed, resulting in a planar structure. It is possible to provide an insulated gate field effect semiconductor device which has a short length and which can reduce the parasitic capacitance between the gate electrode and the drain region and at the same time improve the reliability of the characteristics.

[Brief description of drawings]

FIG. 1 is a vertical cross-sectional view of a conventional semiconductor device.

FIG. 2 is a vertical end view of the insulated gate field effect semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a vertical cross-sectional view of an insulated gate field effect semiconductor device which is a second embodiment of the present invention.

FIG. 4 is a vertical sectional view of an insulated gate field effect semiconductor device according to a third embodiment of the present invention.

FIG. 5A is a vertical sectional view of an insulated gate field effect semiconductor device according to a fourth embodiment of the present invention. (B) is a longitudinal sectional view of an insulated gate field effect semiconductor device according to a fifth embodiment of the present invention.

FIG. 6 is a block circuit diagram of an image sensor according to a fourth embodiment of the present invention.

[Explanation of symbols]

 1 ... Substrate 20, 20 '... Gate electrode 21, 21' ... Gate insulating film 22, 24, 28 ... Mask 23 ... Ultraviolet 26 ... Insulating film 27 ... Channel formation Region 29 ... Source region 30 ... Drain region 40, 41 ... Insulated gate type field effect semiconductor device 200 ... Gate electrode forming layer 210 ... Gate insulating film forming layer 220 ... Mask forming layer

Claims (1)

[Claims] 1. A multi-layer film of a gate electrode formed on the insulating substrate, the upper and side surfaces of the enclosing said gate electrode an insulating oxide film formed by plasma oxidizing method and a silicon nitride film of the gate electrode Formed by sandwiching the gate insulating film having the structure and the gate insulating film and the gate electrode.
A source region and a source region made of a non-single-crystal semiconductor of one conductivity type.
Of the rain region and the gate insulating film, the source region, and the drain region.
A planar structure in which the smooth upper surface, an insulated gate field effect, wherein the channel forming region of non-single-crystal semiconductor authenticity or substantially authenticity of hydrogen has been added adjacent to the planar structure, in that it consists of Semiconductor device.