JPH0573068B2 - - Google Patents

Description

[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to a semiconductor device.

(Conventional technology and its problems) In the case of a MOS type semiconductor device, as shown in Figure 3,
The higher the impurity concentration implanted into the field, the higher the field inversion voltage and the lower the junction breakdown voltage. That is, the concentration of the impurity to be implanted under the field oxide film is determined within a range in which the field inversion voltage shown by the solid line in the figure matches the field edge junction breakdown voltage.

Therefore, in the gate region of the MOS type semiconductor device,
As shown in FIG. 4, a high concentration impurity region 1 is formed in a slightly larger region. That is, the impurities forming the high concentration impurity region 1 also diffuse into the edge portion 1a of the field oxide film 2.
Therefore, considering the portion where the high concentration impurity region 1 extends to the edge portion 1a, as shown in FIG. A region 4 is formed in which the impurities in region 3 overlap. As a result, when the impurity concentration implanted into the gate region increases, the impurity concentration at the edge portion 1a of the field oxide film 2 increases as a result.
Therefore, the field inversion voltage increases and the junction breakdown voltage decreases. That is, since the field inversion voltage shown in FIG. 3 increases and the field edge junction breakdown voltage decreases, the relationship between the two and the impurity concentration under the field oxide film 2 is shown by the broken line in the figure. For this reason, the impurity concentration under the field oxide film 1 where both voltages can be matched is
It decreases by the amount moving from the solid line intersection a ₂ to the broken line intersection a ₁ in the figure. In other words, with the miniaturization of devices, the concentration of impurities implanted into the gate region increases, and as a result, the field inversion voltage becomes higher than the concentration of the impurity region 3 under the field oxide film 2. This largely depends on the concentration of the high concentration impurity region 1. Therefore, a region 1b in which the high concentration impurity region 1 does not extend to the edge portion 1a.
Considering that, the high concentration impurity region 1 under the gate region
The edge part of the field oxide film 2 where only the impurity region 3 under the field oxide film 2 exists without
1b (see Fig. 4), the field reversal voltage becomes low. Therefore, it is conceivable to form a high concentration impurity region not only under the gate region but also over the entire region where the source/drain impurity regions are to be formed. However, if a highly concentrated impurity region is formed throughout the device region consisting of the gate region and source/drain region in this way, the following problems will occur as the device becomes smaller and the impurity regions that make up the source and drain become shallower. .

That is, as the impurity regions of the source and drain become shallower, the high concentration impurity region 1 extends directly below the source/drain impurity regions, thereby increasing the impurity concentration on the substrate 5 side. In other words, the sauce has become shallower.
The PN junction formed by the drain impurity region and the high concentration impurity region 1 that extends along with it is the same as the PN junction formed with the substrate 5 directly below the source/drain impurity region if it is deep enough. It is pulled up closer to the main surface than in the case of Therefore, the depletion layer does not spread in the direction of the substrate 5, and the capacitance of the depletion layer increases, resulting in failure to sufficiently improve device characteristics.

[Structure of the invention]

(Means for Solving the Problems) The present invention includes an element region provided in a predetermined region of a semiconductor substrate of one conductivity type, and an impurity region of the opposite conductivity type that is divided into two parts via a gate region. a source region and a drain region formed by the semiconductor substrate; and a high concentration impurity region of the same conductivity type extending from the main surface into the semiconductor substrate.

(Function) According to the semiconductor device according to the present invention, the depletion layer capacitance can be reduced because the high concentration region is provided in the portion where the gate region, the source region, and the drain region are in contact with the field oxide film. Therefore, it is possible to suppress a decrease in field inversion voltage and junction breakdown voltage, and improve device characteristics.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 is an explanatory diagram showing a schematic configuration of an embodiment of the present invention. In the figure, 10 is a P conductivity type semiconductor substrate. An element region surrounded by a field oxide film 11 is provided in a predetermined region of the semiconductor substrate 10 . A P-type impurity region 12 is formed directly under the field oxide film 11 . A gate electrode 14 is formed in a predetermined region on the element region with a gate oxide film 13 interposed therebetween. A P-type high concentration impurity region 15 is formed in the semiconductor substrate 10 directly under the gate electrode 14 to be slightly larger than the gate region, and this high concentration impurity region 15 is located between the field oxide film 11 and the element region. Extends into the area containing the border. In addition, in the part of the element region divided into two by the gate region under the gate electrode 14,
N-type impurity regions 16, which serve as source and drain regions, are formed with a shallower diffusion depth than the high concentration impurity regions 15. In other words, impurity region 16
The peripheral region is included in the high concentration impurity region 15.

Here, the formation of the high concentration impurity region 15 is performed in the second
As shown in Figures A and B, a resist film 17 with a shape slightly smaller than this is placed on the portion where the impurity region that will become the source/drain region in the element region is to be formed, and this resist film 17 is used as a mask. It can be easily formed by implanting an impurity 18 such as boron into the semiconductor substrate 10.

According to the semiconductor device 20 configured in this manner, channel ion implantation is no longer performed in most of the impurity regions 16 constituting the source and drain regions, and the impurity concentration of the semiconductor substrate 10 is not increased. , an increase in depletion layer capacitance can be prevented. In addition, since the channel ion implantation is performed evenly at the edge portion of the field oxide film 11,
Due to the miniaturization of devices, the impurity concentration implanted into the channel increases, and even if the impurity concentration implanted into the field oxide film 11 side decreases, the field inversion voltage and junction breakdown voltage at the edge portion of the field oxide film 11 decrease. By ensuring consistency, it is possible to prevent both voltages from dropping.

As a result, by applying the present invention to a transistor that selects a column, access time can be shortened by reducing the depletion layer capacitance of the transistor while maintaining consistency with peripheral transistors without lowering the field inversion voltage. be able to. Furthermore, in cases where the contact can be made only in part of the source and drain regions, it is necessary to increase the area of the source and drain in order to reduce the diffusion resistance, but by applying the present invention, the area of the diffusion region The increase in depletion layer capacitance due to the increase in can be suppressed to a small level.

〔Effect of the invention〕

As explained above, according to the semiconductor device according to the present invention, the depletion layer capacitance can be reduced and the device characteristics can be improved without lowering the field reversal voltage and the junction breakdown voltage.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing a schematic configuration of an embodiment of the present invention, FIG. 2 is an explanatory diagram showing a method of forming a high concentration impurity region of the same embodiment, and FIG. Characteristic diagrams showing the relationship with the impurity concentration under the film, FIGS. 4 and 5, are explanatory diagrams showing problems with conventional semiconductor devices. 10... Semiconductor substrate, 11... Field oxide film, 12... P-type impurity region, 13... Gate oxide film, 14... Gate electrode, 15... High concentration impurity region, 16... Impurity region, 17... ...Resist film, 18... Impurity, 20 ... Semiconductor device.

Claims (1)

[Claims] 1. A semiconductor substrate of a first conductivity type, a field insulating film selectively formed on the surface of the semiconductor substrate, an element region surrounded by the field insulating film, and a semiconductor substrate of the field insulating film. a first conductivity type inversion prevention layer formed below; a gate electrode provided on the surface of the element region with a gate insulating film interposed therebetween so as to divide the element region into two; and the element region and the field insulating film. a first conductivity type high concentration impurity region selectively and continuously formed at a predetermined diffusion depth under the gate electrode in the element region and at the boundary with the first conductivity type; Each of the divided element regions includes a second conductivity type impurity region formed with a side surface in contact with the high concentration impurity region, the diffusion depth of which is shallower than that of the high concentration impurity region, and a bottom surface of the second conductivity type impurity region. A semiconductor device comprising a source region and a drain region that are in contact with a first conductivity type region of the semiconductor substrate. 2. A step of selectively doping a first conductivity type impurity into a portion of a semiconductor substrate of a first conductivity type where a field region is to be formed to form an inversion prevention region of a first conductivity type; a step of forming a field insulating film and isolating a device region surrounded by the field insulating film; and a step of selectively forming an ion implantation shielding film covering a planned source region and a planned drain region of the device region. Using the ion implantation shielding film as a blocking mask, high concentration ions of first conductivity type impurities are implanted into the boundary between the field region and the device region and into the planned channel region in the device region. , forming a continuous high-concentration impurity region of the first conductivity type at a predetermined diffusion depth; forming a gate electrode on the planned channel region via a gate insulating film; and forming a gate electrode in the planned case region. forming a source region and a drain region having a shallower diffusion depth than the high concentration impurity region by selectively doping the region and the planned drain region with a second conductivity type impurity. A method for manufacturing a featured semiconductor device.