JPH056995A - High melting point metal silicide film and its formation method - Google Patents
High melting point metal silicide film and its formation methodInfo
- Publication number
- JPH056995A JPH056995A JP15656691A JP15656691A JPH056995A JP H056995 A JPH056995 A JP H056995A JP 15656691 A JP15656691 A JP 15656691A JP 15656691 A JP15656691 A JP 15656691A JP H056995 A JPH056995 A JP H056995A
- Authority
- JP
- Japan
- Prior art keywords
- silicide film
- melting point
- high melting
- point metal
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、トランジスタ等に使わ
れる高融点金属シリサイド膜とその形成方法に関するも
のである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a refractory metal silicide film used in transistors and the like and a method for forming the same.
【０００２】[0002]
【従来の技術とその課題】従来、電極として用いられて
いた多結晶Ｓｉ膜は最も安定で特性に優れた電極材であ
ったが、ＬＳＩの微細化高集積化が進展するに従い、細
く長い多結晶Ｓｉを伝播する電気信号のスピードが、高
い層抵抗のために急激に低下してＬＳＩの高速動作を妨
げるため、比抵抗が１桁低い高融点シリサイド膜が有効
である。図２に高融点シリサイド膜の一例を示す。２は
Ｓｉ層、３はＴｉシリサイド層である。しかし、高融点
金属シリサイド膜を電極として用いた場合、Ｓｉリッチ
（ダイシリサイド）にすると膜としての安定性がよくな
るが、層抵抗値が高くなってしまう。また、メタルリッ
チ（メタルリッチシリサイド）にしてしまうと層抵抗値
は低くなるが、膜としての安定性がよくない（Ｓｉリッ
チになろうとする）という問題がある。2. Description of the Related Art Conventionally, a polycrystalline Si film used as an electrode has been the most stable and excellent electrode material, but as the miniaturization and high integration of LSI progresses, it becomes thin and long. Since the speed of the electric signal propagating through the crystalline Si is drastically reduced due to the high layer resistance and the high speed operation of the LSI is hindered, a high melting point silicide film having a specific resistance lower by one digit is effective. FIG. 2 shows an example of a high melting point silicide film. 2 is a Si layer and 3 is a Ti silicide layer. However, when a refractory metal silicide film is used as an electrode, if it is made Si-rich (disilicide), the stability of the film is improved, but the layer resistance value is increased. Further, if the layer is metal-rich (metal-rich silicide), the layer resistance value becomes low, but there is a problem that the stability as a film is not good (it tends to become Si-rich).
【０００３】本発明の目的は、このような問題を解決し
た高融点金属シリサイド膜とその形成方法を提供するこ
とにある。An object of the present invention is to provide a refractory metal silicide film and a method for forming the same, which solves the above problems.
【０００４】[0004]
【課題を解決するための手段】本発明の高融点金属シリ
サイド膜は、高融点金属とＳｉとＧｅが混在することを
特徴とする。The refractory metal silicide film of the present invention is characterized in that refractory metal, Si and Ge are mixed.
【０００５】また本発明の高融点金属シリサイド膜の形
成方法は、ＳｉＧｅ混晶層上に高融点金属を堆積し、熱
処理することを特徴とする。The method of forming a refractory metal silicide film of the present invention is characterized in that a refractory metal is deposited on the SiGe mixed crystal layer and heat-treated.
【０００６】また本発明の高融点金属シリサイド膜の形
成方法は、高融点金属とＳｉとＧｅを同時に堆積させる
ことを特徴とする。The method of forming a refractory metal silicide film of the present invention is characterized in that the refractory metal, Si and Ge are simultaneously deposited.
【０００７】[0007]
【作用】Ｓｉリッチにした高融点金属ダイシリサイド膜
中に均一にＧｅを混ぜることにより、安定でしかも層抵
抗値が低い電極が形成できる。By uniformly mixing Ge into the Si-rich refractory metal disilicide film, a stable electrode having a low layer resistance value can be formed.
【０００８】[0008]
【実施例】図１に本発明の高融点金属シリサイド膜構造
を示す。この高融点金属シリサイド膜は、次のようにし
て形成される。まず、図３に示すように、Ｓｉ（１０
０）基板上にＳｉＧｅ混晶（Ｇｅ＝３０％）を固体ソー
スＭＢＥによりエピタキシャル成長する。２はＳｉ層、
５はＳｉＧｅ層である。EXAMPLE FIG. 1 shows a refractory metal silicide film structure of the present invention. This refractory metal silicide film is formed as follows. First, as shown in FIG. 3, Si (10
0) SiGe mixed crystal (Ge = 30%) is epitaxially grown on the substrate by solid source MBE. 2 is a Si layer,
5 is a SiGe layer.
【０００９】次に、ＨＦ処理により自然酸化膜を除去し
た後、ＳｉＧｅ混晶上にスパッタ蒸着法によりＴｉを堆
積する。この基板を断面ＳＥＭ観察し、図３のような構
造になっていることを確認した。４はＴｉ層である。Next, after removing the natural oxide film by HF treatment, Ti is deposited on the SiGe mixed crystal by the sputter deposition method. This substrate was observed by cross-section SEM, and it was confirmed that it had a structure as shown in FIG. 4 is a Ti layer.
【００１０】この構造の基板を、６００℃で２０分間の
熱処理する。この熱処理した基板を断面ＳＥＭ観察、ス
パッタオージェ電子分光法により、図１のような構造に
なっていることを確認した。１はＴｉＳｉＧｅ混在層で
ある。The substrate having this structure is heat-treated at 600 ° C. for 20 minutes. It was confirmed by a cross-sectional SEM observation and a sputter Auger electron spectroscopy of this heat-treated substrate that the structure was as shown in FIG. 1 is a TiSiGe mixed layer.
【００１１】また、図４に熱処理前と熱処理後のスパッ
タオージェ電子分光のＧｅのＰＥＡＫ−ＴＯ−ＰＥＡＫ
の結果を示す。この結果から、熱処理前はＳｉＧｅ層５
のみにＧｅが存在しているのに対し、熱処理後は層１中
に均一に存在していることがわかる。このような方法で
形成した膜の層抵抗値を測定してみると８〜１０μΩｃ
ｍであり、Ｔｉダイシリサイドの層抵抗値１３〜１６μ
Ωｃｍに比べ低くなっていた。FIG. 4 shows the PEAK-TO-PEAK of Ge by sputter Auger electron spectroscopy before and after the heat treatment.
The result is shown. From this result, before the heat treatment, the SiGe layer 5 was formed.
It can be seen that Ge is present only in the layer 1, whereas it is uniformly present in the layer 1 after the heat treatment. When the layer resistance value of the film formed by such a method is measured, it is 8 to 10 μΩc.
m, and the layer resistance value of Ti disilicide is 13 to 16 μm.
It was lower than Ωcm.
【００１２】以上のように形成される高融点金属シリサ
イド膜を用いて、図５に示す様な構造をもったＰＮ接合
のダイオードを作成した。８はＮ型Ｓｉ層、９はＰ型Ｓ
ｉ層、１はＴｉＳｉＧｅ混在層、７はＳｉＯ2 層、６は
Ａｌ層である。このダイオードは正常にオーミックがと
れており、正常なダイオード特性を示した。Using the refractory metal silicide film formed as described above, a PN junction diode having a structure as shown in FIG. 5 was prepared. 8 is an N-type Si layer, 9 is a P-type S layer
i layer, 1 is a TiSiGe mixed layer, 7 is a SiO 2 layer, and 6 is an Al layer. This diode was normally ohmic and showed normal diode characteristics.
【００１３】次に、本発明の他の形成方法について説明
する。この方法では、Ｓｉ（１００）基板上にＴｉ，Ｓ
ｉ，Ｇｅを同時に蒸着する共蒸着法によって形成した。
この基板の断面ＳＥＭ観察、スパッタオージェ分光法に
より、図１のような構造になっていることを確認した。
Ｔｉ，Ｓｉ，Ｇｅ原子の存在比はそれぞれ３５％，６０
％，５％であった。また、図６にＧｅのスパッタオージ
ェ電子分光のＰＥＡＫ−ＴＯ−ＰＥＡＫの結果を示す。
この結果から、Ｇｅが膜中に均一に存在していることが
わかる。この時の層抵抗値を測定してみると、Ｔｉダイ
シリサイドの層抵抗値１３〜１６μΩｃｍに比べ低くな
っていた。Next, another forming method of the present invention will be described. In this method, Ti, S is deposited on a Si (100) substrate.
It was formed by a co-evaporation method in which i and Ge are simultaneously vapor-deposited.
It was confirmed by a cross-sectional SEM observation and sputter Auger spectroscopy of this substrate that the structure was as shown in FIG.
The abundance ratios of Ti, Si, and Ge atoms are 35% and 60, respectively.
% And 5%. Moreover, the result of PEAK-TO-PEAK of sputter Auger electron spectroscopy of Ge is shown in FIG.
From this result, it can be seen that Ge is uniformly present in the film. When the layer resistance value at this time was measured, it was lower than the layer resistance value of Ti disilicide of 13 to 16 μΩcm.
【００１４】実際に共蒸着法によって形成する高融点金
属シリサイド膜を用いて、図５に示す様な構造をもった
ＰＮ接合のダイオードを作成した。このダイオードは正
常にオーミックがとれており、正常なダイオード特性を
示した。A PN junction diode having a structure as shown in FIG. 5 was prepared by using a refractory metal silicide film actually formed by the co-evaporation method. This diode was normally ohmic and showed normal diode characteristics.
【００１５】また、Ｔｉ以外に高融点金属であるＷ，Ｍ
ｏについても行ったが、Ｔｉと同じく層抵抗値の低い膜
を得ることができた。In addition to Ti, W and M which are refractory metals
As for Ti, a film having a low layer resistance value like Ti was obtained.
【００１６】[0016]
【発明の効果】本発明の高融点金属シリサイド膜は安定
した膜で、従来の安定な高融点金属ダイシリサイド膜よ
り層抵抗値を低くすることが可能である。従ってＬＳＩ
の配線、コンタクト電極、ＳｉＧｅＨＢＴのベース電極
等に用いれば著しい効果がある。The refractory metal silicide film of the present invention is a stable film and can have a lower layer resistance value than the conventional stable refractory metal disilicide film. Therefore, LSI
If it is used for the wiring, the contact electrode, the base electrode of SiGe HBT, and the like, a remarkable effect is obtained.
【図１】本発明の一実施例の構造断面図である。FIG. 1 is a structural cross-sectional view of an embodiment of the present invention.
【図２】従来の高融点金属シリサイド膜の構造断面図で
ある。FIG. 2 is a structural cross-sectional view of a conventional refractory metal silicide film.
【図３】熱処理前の構造断面図である。FIG. 3 is a structural cross-sectional view before heat treatment.
【図４】熱処理で形成されたシリサイド膜のオージェ電
子分光ＧｅピークのＰＥＡＫ−ＴＯ−ＰＥＡＫの結果を
示す図である。FIG. 4 is a diagram showing the result of PEAK-TO-PEAK of Auger electron spectroscopy Ge peak of a silicide film formed by heat treatment.
【図５】ＰＮ接合ダイオードの断面図である。FIG. 5 is a sectional view of a PN junction diode.
【図６】同時蒸着で形成されたシリサイド膜のオージェ
電子分光ＧｅピークのＰＥＡＫ−ＴＯ−ＰＥＡＫの結果
を示す図である。FIG. 6 is a diagram showing a result of PEAK-TO-PEAK of Auger electron spectroscopy Ge peak of a silicide film formed by simultaneous vapor deposition.
１ Ｔｉ，Ｓｉ，Ｇｅ混在層（Ｓｉリッチ） ２ Ｓｉ層 ３ Ｔｉシリサイド層 ４ Ｔｉ層 ５ ＳｉＧｅ層 ６ Ａｌ層 ７ ＳｉＯ2 層 ８ Ｎ型Ｓｉ層 ９ Ｐ型Ｓｉ層1 Ti, Si, Ge mixed layer (Si rich) 2 Si layer 3 Ti silicide layer 4 Ti layer 5 SiGe layer 6 Al layer 7 SiO 2 layer 8 N-type Si layer 9 P-type Si layer
Claims (3)
特徴とする高融点金属シリサイド膜。1. A refractory metal silicide film in which refractory metal, Si and Ge are mixed.
熱処理することを特徴とする高融点金属シリサイド膜の
形成方法。2. A refractory metal is deposited on the SiGe mixed crystal layer,
A method of forming a refractory metal silicide film, characterized by heat treatment.
ることを特徴とする高融点金属シリサイド膜の形成方
法。3. A method for forming a refractory metal silicide film, which comprises depositing a refractory metal, Si and Ge at the same time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15656691A JPH056995A (en) | 1991-06-27 | 1991-06-27 | High melting point metal silicide film and its formation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15656691A JPH056995A (en) | 1991-06-27 | 1991-06-27 | High melting point metal silicide film and its formation method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH056995A true JPH056995A (en) | 1993-01-14 |
Family
ID=15630587
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15656691A Pending JPH056995A (en) | 1991-06-27 | 1991-06-27 | High melting point metal silicide film and its formation method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH056995A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5644166A (en) * | 1995-07-17 | 1997-07-01 | Micron Technology, Inc. | Sacrificial CVD germanium layer for formation of high aspect ratio submicron VLSI contacts |
| US6093968A (en) * | 1996-06-26 | 2000-07-25 | Micron Technology, Inc. | Germanium alloy contact to a silicon substrate |
| US6239029B1 (en) | 1995-07-17 | 2001-05-29 | Micron Technology, Inc. | Sacrificial germanium layer for formation of a contact |
| US6541336B1 (en) | 2002-05-15 | 2003-04-01 | International Business Machines Corporation | Method of fabricating a bipolar transistor having a realigned emitter |
| US6903462B2 (en) | 1998-02-25 | 2005-06-07 | Micron Technology, Inc. | Chemical vapor deposition of titanium |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62143461A (en) * | 1985-12-18 | 1987-06-26 | Hitachi Ltd | N-type gaas ohmic electrodes |
| JPS6396965A (en) * | 1986-10-14 | 1988-04-27 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| JPS6489446A (en) * | 1987-09-30 | 1989-04-03 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
-
1991
- 1991-06-27 JP JP15656691A patent/JPH056995A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62143461A (en) * | 1985-12-18 | 1987-06-26 | Hitachi Ltd | N-type gaas ohmic electrodes |
| JPS6396965A (en) * | 1986-10-14 | 1988-04-27 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| JPS6489446A (en) * | 1987-09-30 | 1989-04-03 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5644166A (en) * | 1995-07-17 | 1997-07-01 | Micron Technology, Inc. | Sacrificial CVD germanium layer for formation of high aspect ratio submicron VLSI contacts |
| US6239029B1 (en) | 1995-07-17 | 2001-05-29 | Micron Technology, Inc. | Sacrificial germanium layer for formation of a contact |
| US6309967B1 (en) | 1995-07-17 | 2001-10-30 | Micron Technology, Inc. | Method of forming a contact |
| US6597042B1 (en) | 1995-07-17 | 2003-07-22 | Micron Technology, Inc. | Contact with germanium layer |
| US6093968A (en) * | 1996-06-26 | 2000-07-25 | Micron Technology, Inc. | Germanium alloy contact to a silicon substrate |
| US6229213B1 (en) | 1996-06-26 | 2001-05-08 | Micron Technology, Inc. | Germanium alloy electrical interconnect structure |
| US6331482B1 (en) | 1996-06-26 | 2001-12-18 | Micron Technology, Inc. | Method of VLSI contact, trench, and via filling using a germanium underlayer with metallization |
| US6903462B2 (en) | 1998-02-25 | 2005-06-07 | Micron Technology, Inc. | Chemical vapor deposition of titanium |
| US6940172B2 (en) | 1998-02-25 | 2005-09-06 | Micron Technology, Inc. | Chemical vapor deposition of titanium |
| US6541336B1 (en) | 2002-05-15 | 2003-04-01 | International Business Machines Corporation | Method of fabricating a bipolar transistor having a realigned emitter |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4398341A (en) | Method of fabricating a highly conductive structure | |
| JPH03133176A (en) | Silicon carbide semiconductor device and manufacture thereof | |
| JPH088224B2 (en) | Method of forming contact and internal connection line of integrated circuit | |
| EP1754253A2 (en) | A method of base formation in a bicmos process | |
| JPH056995A (en) | High melting point metal silicide film and its formation method | |
| JPS63318779A (en) | Manufacture of semiconductor device | |
| JP2001518716A (en) | Heterojunction bipolar transistor with wide bandgap low interdiffusion base-emitter junction | |
| KR940004450B1 (en) | Method of making semiconductor device | |
| JP2955814B2 (en) | Silicide plug formation method | |
| JP2797200B2 (en) | Polycrystalline silicon electrode and method of manufacturing the same | |
| JP2702293B2 (en) | Method for manufacturing semiconductor device | |
| JPH02106971A (en) | Semiconductor integrated circuit device and manufacture thereof | |
| JPH01124253A (en) | Semiconductor device | |
| JPH0684926A (en) | Bipolar transistor and its production | |
| JPS63198373A (en) | Semiconductor device and its manufacture | |
| JPH08306913A (en) | Manufacture of semiconductor device | |
| JPH0242719A (en) | Manufacture of semiconductor device | |
| JP2650972B2 (en) | Method for manufacturing semiconductor device | |
| JPH0653234A (en) | Manufacture of semiconductor device | |
| JPS6038026B2 (en) | Manufacturing method of semiconductor device | |
| JPH10223561A (en) | Manufacture of semiconductor device | |
| JPS6032349B2 (en) | Manufacturing method of semiconductor device | |
| JP3131986B2 (en) | Bipolar transistor | |
| JPS58166739A (en) | Semiconductor device and its manufacture | |
| JPH05160023A (en) | Manufacture of semiconductor device |