JPH056754B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention provides a method for recording a digital signal modulated with defined maximum and minimum level inversion intervals for levels corresponding to "1" and "0" at a constant recording density. The present invention relates to a clock reproducing circuit for obtaining a bit clock pulse for a read and reproduced signal in a disc player for reproducing signals from a disc such as a digital audio disc having recorded tracks.

BACKGROUND TECHNOLOGY AND PROBLEMS Digital audio signals are recorded on a rotating disk using a pulse code modulation (PCM) technique at a constant recording density, forming a spiral recording track.
On a disk, the digital signals recorded have a predetermined format. For example, each frame is made up of consecutive frame units, and each frame is formed of, for example, 588 channel bits, and a frame synchronization signal section is provided at the beginning, followed by a data section. . When recording such digital signals, a run length limited code modulation method is used. This modulation method is based on the minimum level inversion interval (the distance between two adjacent signal level inversion parts) between the signal level transitions corresponding to "0" and "1" with respect to "0" or "1" data. interval, i.e., the smallest of the level reversal intervals)
The purpose is to increase the recording efficiency by increasing the time interval, and to shorten the maximum level inversion interval (the largest of the level inversion intervals) to facilitate self-clock operation during playback. For example, the maximum level inversion interval is defined to be 11 channel bits long, and the minimum level inversion interval is defined to be 3 channel bits long. In addition, the fact that modulation output does not normally appear for the data part in which the maximum level inversion interval is continuous is utilized, and the frame synchronization signal part corresponds to the maximum level inversion interval of "1" and "0", respectively. The modulated output waveform pattern is made to have two consecutive modulated output waveform patterns at the same level.

Such a run-length limited code modulation method is adopted, and the maximum level inversion interval and minimum level inversion interval for the levels corresponding to "1" and "0" are defined, and the modulated digital signal is recorded at a constant level. Digital density recorded
In a disk player that reproduces signals from a disk such as an audio disk, the relative moving speed between the recording track of the disk and the signal reading means in the disk player, that is, the linear speed is constant. It is rotated so that
The digital signal recorded on the disk is read and a reproduced signal is obtained. In the case of a digital audio disk, the recorded digital signal is modulated as described above, so the reproduced signal obtained by reading is divided into 11 channels as shown as S in FIG. 1A.・
Maximum level reversal interval corresponding to length of bit
A frame period in which T _nax starts with two consecutive frame synchronization signal parts FS, followed by a level inversion interval according to the data of the recorded digital signal.
FR becomes a rectangular wave signal that appears repeatedly.

To demodulate the read and reproduced signal thus obtained, a bit clock pulse BC as shown in FIG. 1B is required, corresponding to each channel bit of the recorded digital signal. For this reason, the disk player is provided with a clock recovery circuit that generates a bit clock pulse BC based on the read and playback signal. Conventionally, the clock reproduction circuit in such a disk player is constructed using a phase locked loop (hereinafter referred to as PLL) as shown in FIG. In the configuration shown in FIG. 2, information is obtained from the information reading means 1. For example, the read output from a digital audio disk is
The signal is amplified to a predetermined level by an amplifier 2 and supplied to a waveform shaping section 3, from which a read reproduction signal S having a rectangular waveform as shown in FIG. 1A is obtained. Then, this read reproduction signal S is supplied to an edge detection section 4, and edge pulses corresponding to the rising and falling edges of the rectangular waveform of the read reproduction signal S are obtained at its output terminal, and a phase comparator 6 forming a PLL 5 is supplied to one input terminal of The PLL 5 is configured such that the oscillation frequency is controlled by the phase comparator 6, the low-pass filter 7 to which the output thereof is supplied, and the output voltage of the low-pass filter 7, and the oscillation output is supplied to the other input terminal of the phase comparator 6. An output terminal 9 is formed from the output terminal of the voltage controlled oscillator 8. As a result, the edge detection section 4
Based on the result of the phase comparison between the edge pulse and the oscillation output of the voltage-controlled oscillator 8, the oscillation frequency of the voltage-controlled oscillator 8 is such that the phase difference between the edge pulse and the oscillation output of the voltage-controlled oscillator 8 is constant. The oscillation output of the voltage controlled oscillator 8 is taken out from the output terminal 9 and used as a bit clock pulse BC.

In this way, bit clock pulses are obtained based on the read and reproduced signal, and clock recovery is performed. Since the phase lock range is usually narrow, when the rotational speed of a digital audio disk or other disk changes from the normal rotational speed, the length of each level inversion interval of the read and reproduced signal is no longer the normal length. , the phase difference between the edge pulse from the edge detection section and the oscillation output of the voltage controlled oscillator becomes too large for the PLL,
There is a problem in that the PLL is no longer able to perform a phase lock operation, and as a result, a situation easily arises in which the necessary bit clock pulses cannot be obtained. For this reason, in order to reproduce the clock, digital players using conventional clock regeneration circuits must keep the disk rotational speed within a relatively narrow specific rotational speed range that ensures correct phase locking by the PLL. It is necessary to provide a rotational pull-in circuit to pull the signal in and hold it there, and in the case of a disk player that plays back signals from a digital audio disk, the pitch of the reproduced audio signal can only be changed within an extremely narrow range. Moreover, it has disadvantages such as the inability to reproduce the clock when the disc player is in a high-speed search operation mode.

OBJECTS OF THE INVENTION In view of the above, the present invention provides a method for recording data from a disk having a track on which a digital signal modulated using a run-length limited code modulation method and having specified maximum and minimum level inversion intervals is recorded. Even if the length of each level inversion interval of the reproduced signal read from the disc changes significantly from the normal length, it will follow that change and read the signal at that time. It is an object of the present invention to provide a digitized clock recovery circuit capable of generating bit clock pulses necessary for demodulating a reproduced signal.

SUMMARY OF THE INVENTION The clock reproduction circuit for a disk player according to the present invention provides a clock reproducing circuit for a disc player that uses a rotation clock in which a digital signal modulated with defined maximum and minimum level inversion intervals with respect to levels corresponding to "1" and "0" is recorded. A reproduction signal obtained by reading from the disk is supplied to the master clock pulse generator and the master clock pulse generator from the master clock pulse generator.
The clock pulse is divided by 1/K.M (where K is the normal number of bit clock pulses that should correspond to the maximum level inversion interval in the reproduced signal mentioned above, and M
is a positive integer), a first counter that counts the pulse output from the first frequency divider at each level inversion interval of the above-mentioned reproduced signal, and a maximum value holding section that holds the maximum count value of the first counter; and a second pulse that generates one pulse every time a master clock pulse is counted for the maximum count value held in the maximum value holding section. 1/M pulse output from the counter and the second counter
and a second frequency dividing section for dividing the frequency of the master clock pulse, so that the frequency of the master clock pulse is equal to the maximum level inversion interval in the reproduced signal obtained when the rotary disk is rotated at a normal rotation speed. The count value of the first counter is selected to be K.multidot.M, so that the bit clock pulse is obtained from the second frequency divider. By doing this, even if the length of each level inversion interval of the read and reproduced signal from the disk changes significantly from the normal length due to reasons such as the rotation speed of the disk not being normal, , a bit clock pulse is obtained which always corresponds with a normal number (K) to the maximum level inversion interval. That is,
Even if the length of each level inversion interval of the read reproduction signal from the disk changes significantly from the normal length, the frequency will change to follow the change, and the frequency required for demodulating the read reproduction signal at that time will change. This results in a bit clock pulse that is similar to the one shown below.

Example Examples of the present invention will be described below.

FIG. 3 shows an example of a clock regeneration circuit for a disk player according to the present invention. In this example, the present invention is applied to a disc player that reproduces signals from the aforementioned digital audio disc. In the configuration shown in FIG. 3, the same information reading means 1, amplifier 2, waveform shaping section 3, and edge detection section 4 as in the configuration shown in FIG.
are arranged. The output terminal of the edge detection section 4 is 6
It is connected to the clear terminal CLR of the bit counter 10, and the maximum count value of the 6-bit counter 10 is set to 6 on the output side of the 6-bit counter 10.
a maximum value holder 11 that holds the shape of the bit output;
A latch section 12 for the 6-bit output of the maximum value holder 11 and a presettable down counter 13 whose output end of the latch section 12 is connected to a preset terminal PS are successively connected in cascade. Then, the output terminal of the presettable down counter 13 is 1/2
It is connected to the input terminal of the frequency divider 14, and the 1/2 frequency divider 14
Output terminal 15 is led out from the output end of.

The output terminal of the edge detection section 4 and the presettable
The output terminal of the down counter 13 is the OR gate 16
The output terminal of this OR gate 16 is connected to the load terminal L of the presettable down counter 13. Further, the output terminal of the edge detection section 4 is also connected to the input terminal of a 1/256 counter 17, and the output terminal of the 1/256 counter 17 is connected to the clear terminal CLR of the maximum value holder 11 and the latch section 12, respectively.

Further, a master clock pulse generator 18 is provided, and its output terminal is connected to the countdown terminals CD and 1/2 of the presettable down counter 13.
It is connected to the input end of the frequency divider 19. The output terminal of the edge detection section 4 is connected to the load terminal L of this 1/22 frequency dividing section 19, and "11" is connected to the preset terminal PS.
A binary code generator 20 generates a binary code representing
The output end of is connected. And 1/22 frequency division part 19
The output terminal of the 6-bit counter 10 is connected to the count-up terminal CU.

Based on the above-mentioned configuration, a clock reproduction operation is performed based on the reproduction signal obtained by reading from the digital audio disk.
The digital signal recorded on the disk is 1
The frame is formed of 588 channel bits,
For modulation, if the maximum level inversion interval is specified to be 11 channel bits long and the minimum level inversion interval is specified to be 3 channel bits long, then Therefore, it is required to obtain bit clock pulses such that 11 pulses correspond to the maximum level inversion interval in the reproduced signal obtained by the method.

The information reading means 1 obtains the read output from the rotating digital audio disk, which is amplified to a predetermined level by the amplifier 2 and supplied to the waveform shaping section 3, and the output terminal of the waveform shaping section 3. A read reproduction signal S is obtained. The read reproduction signal S is a rectangular wave signal as shown in FIG. 1A, and FIG. 4A shows frame synchronization in which the maximum level inversion interval T _nax in the read reproduction signal S is two consecutive times. The signal section FS and its vicinity are shown. The read reproduction signal S is supplied to the edge detection section 4, and the edge detection section 4 generates an edge pulse Pe as shown in FIG. is obtained.

On the other hand, a master clock pulse P _n of frequency f is obtained from the master clock pulse generator 18 and supplied to the 1/22 frequency divider 19 . The 1/22 frequency divider 19 receives "11" from the binary code generator 20 every time the edge pulse P _e is supplied to its load terminal L.
``11'' is loaded based on the _binary code representing
When the count value reaches "22", it emits one pulse and is reset. After that, the master clock pulse P _n
Each time the counted value reaches "22", one pulse is generated and the operation of being reset is repeated. As a result, the 1/22 frequency divider 19 outputs the master signal at each pulse interval of the edge pulse P _e .
A pulse P _f as _{shown in} FIG. 6-bit counter 10
is cleared every time an edge pulse P _e is supplied to its clear terminal CLR, and counts pulses P _f . That is, the 6-bit counter 10 calculates a pulse at each pulse interval of the edge pulse P _e , in other words, at each level inversion interval of the read reproduction signal S.
Counting of P _f will be performed starting from the count value "1". At this time, when the read reproduction signal S is obtained by reading the digital audio disk while it is being rotated at a regular rotation speed, and each level inversion interval is of a regular length, The frequency f of the master clock pulse P _n is selected such that the final count of the 6-bit counter 10 at the maximum level inversion interval T _nax is "22". That is, in this example, as shown in FIG. 4C, 22 pulses P _f are inserted in the period corresponding to the maximum level inversion interval T _nax , which is the normal length.
The frequency f of the master clock pulse P _n is selected.

The maximum count value of the count values of the 6-bit counter 10 is held in the form of a 6-bit binary code in the maximum value holder 11, and the maximum count value held in the maximum value holder 11 (for example,
"22") is latched into latch 12 as a binary code, e.g., 0 1 0 1 1 0 representing "22" as shown in FIG. 4D. This maximum value holder 11 is cleared by the pulse P _g shown in FIG. 4E from the 1/256 counter 17 being supplied to the clear terminal CLR.
generates one pulse P _g every time it counts "256" edge pulses P _e . Here, the number 256 is an example chosen so that the pulse interval T _g of the pulse P _g is longer than one frame period FR of the read reproduction signal S. That is, one frame period FR of the read reproduction signal S corresponds to the length of 588 channel bits, and the minimum level inversion interval corresponds to the length of 3 channel bits, so the edge pulse P _e is ” The counting period, in other words, the pulse interval T _g of the pulse P _g is always one frame period.
The period is longer than FR. Of course, a number other than "256" may be selected so that the pulse interval T _g of the pulses P _g is longer than one frame period FR.
In this way, the maximum value holder 11 is cleared by the pulse P _g having a pulse interval T _g longer than one frame period FR, so the maximum value holder 11 is cleared with a hold period longer than one frame period FR. (T _g ) each maximum value hold operation is performed, and in one frame period FR,
Since there is always a frame synchronization signal section FS in which the maximum level inversion interval T _nax is two consecutive times, the maximum value holder 11 always has 6 times in each hold period.
Of the counted values of the bit counter 10, the maximum counted value, which is the final counted value obtained at the maximum level inversion interval T _nax of the read reproduction signal S, is held. Then, the pulse P _g is also supplied to the clear terminal CLR of the latch section 12 to clear the latch section 12, and the latch section 12 clears the maximum value held in the maximum value holder 11 within one hold period. Pulse the number further
Hold until P _g arrives. As a result, the latch unit 12 always has the 6-bit signal obtained at the maximum level inversion interval T _nax of the read and reproduced signal S.
The maximum count value, which is the final count value of the counter 10, is held.

The maximum count value held in the latch section 12 is the preset terminal of the presettable down counter 13.
When the edge pulse P _e is supplied to the load terminal L of the presettable down counter 13 via the OR gate 16, the maximum count value supplied to the preset terminal PS is loaded. Presettable down counter 13
When the maximum count value is loaded, the master clock pulse P _n supplied to the countdown terminal CD is subtracted from the loaded maximum count value (countdown), and when the count value reaches zero, it outputs one pulse. Occur. This pulse is supplied to the load terminal L via the OR gate 16, whereby the presettable down counter 13 is again loaded with the maximum count value from the latch section 12 and is again loaded with the maximum count value of the master clock pulse _Pn . Performs subtraction counting from , and when the counted value becomes zero, one pulse is generated. That is, the presettable down counter 13 generates one pulse every time it counts as many master clock pulses P _n as the maximum count value held in the latch section 12.
An output pulse P _h is obtained at its output end.

If each level inversion interval of the read reproduction signal S has a regular length, the 6-bit counter 1 at the maximum level inversion interval T _nax
The final count value of 0 is "22", so latch part 1
The maximum count value held in 2 is "22", and the presettable down counter 13 is
An output pulse P _h is generated every time 22 clock pulses P _n are counted. Therefore, the output pulse P _h is 1/2
It has the same frequency as the pulse P _f from the frequency divider 19, and 22 pulses are included in the period corresponding to the maximum level inversion interval T _nax of the read reproduction signal S, as shown in FIG. becomes. This output pulse P _h is supplied to the 1/2 frequency divider 14, and the output terminal thereof is a 1/2 frequency divided output of the output pulse P _h , for example, a duty 50 as shown in FIG. 4G.
% pulse output is obtained, which is derived as bit clock pulse BC from output terminal 15. This bit clock pulse BC is
It has a frequency that is 1/2 of the frequency of the output pulse P _h from the presettable down counter 13, and has a maximum level inversion interval of the read reproduction signal S.
Eleven pulses correspond to T _nax , and the bit clock pulses necessary for demodulating the read and reproduced signal S are obtained.

In this way, the clock is regenerated based on the read and reproduced signal S. In this example, if the rotational speed of the digital audio disk is the normal rotational speed, The cases where the maximum level inversion interval T nax in the read and reproduced signal S is taken up and considered will be discussed in the case where the maximum level inversion interval T _nax in the read reproduction signal S is doubled and the case where it is 1/2, respectively.

First, the case where the digital audio disk is rotating at the normal rotation speed will be described with reference to FIG.

When the digital audio disk is rotating at a normal rotational speed, the length of the maximum level inversion interval T _nax1 from the rising edge to the falling edge in the read reproduction signal S ₁ is shown in FIG. 5A. The length is the regular length, so 6 bits.
The final count value of the counter 10 at the maximum level inversion interval T _nax1 becomes "22". That is, 11 counting from the rising edge of the maximum level inversion interval T _nax1 of the master clock pulse P _n shown in FIG. 5B.
The first one is obtained for each pulse, and then the second, third, etc. for every 22nd master clock pulse P _n , and so on.
The pulse P _f from the 1/22 frequency divider 19 that sequentially obtains
As shown in FIG. 5C, there are 22 in the maximum level inversion interval T _nax1 . This results in
The maximum count value held in the latch section 12 is "22", and the presettable down counter 13 receives "22" every time an edge pulse P _e or an output pulse P _h is supplied from the OR gate 16 to the load terminal L of the presettable down counter 13. is loaded. Therefore, Figure 5D
As shown in , after the edge pulse P _e is supplied to the load terminal L, the presettable down counter 13 changes the master clock pulse P _n to "22".
Since an output pulse P _h is generated every time it is counted, the frequency of the output pulse P _h is equal to the frequency of the pulse P _f , and the maximum level inversion interval in the read reproduction signal S ₁
In the period corresponding to T _nax1 , 22 output pulses P _h are input. Therefore, the bit clock pulse obtained by dividing this output pulse P _h by 1/2 is
As shown in FIG. 5E, BC is 11 for the maximum level inversion interval T _nax1 in the read and reproduced signal _S1 .
pulses correspond to each other.

Next, the case where the digital audio disk is rotated at twice the normal rotation speed will be described with reference to FIG.

If the rotational speed of the digital audio disk is twice the normal rotational speed, Fig. 6A
The maximum level inversion interval T _nax2 from the rising edge to the falling edge in the read reproduction signal S ₂ shown in
The length of is 1/2 of the regular length. Therefore, the sixth
The master clock pulse P _n shown in Figure B is counted and the pulse P _f obtained from the 1/22 frequency divider 19 is
As shown in _FIG .
The final count value of the counter 10 at the maximum level inversion interval T _nax2 is "11". As a result, the maximum count value held in the latch section 12 becomes "11", and as shown in FIG. 6D, the presettable
The down counter 13 generates an output pulse P _h every time the master clock pulse P _n is counted by 11 after the edge pulse P _e is supplied to the load terminal L, so the frequency of the output pulse P _h is equal to the pulse P _f
, and 22 output pulses P _h enter in the period corresponding to the maximum level inversion interval T _nax2 in the read reproduction signal S ₂ . Therefore, in this case as well, the bit clock pulse BC obtained by dividing the output pulse P _h by 1/2 is equal to the maximum level inversion interval T _nax2 in the read reproduction signal _S2 , as shown in FIG. 6E. There are 11 pulses corresponding to .

Furthermore, the case where the digital audio disk is rotated at half the normal rotation speed will be described with reference to FIG.

If the rotational speed of the digital audio disk is 1/2 of the normal rotational speed, Fig. 7A
The maximum level reversal interval T _nax3 from the rising edge to the falling edge in the read reproduction signal S ₃ shown in
The length is twice the normal length. Therefore, the seventh
The master clock pulse P _n shown in Figure B is counted and the pulse P _f obtained from the 1/22 frequency divider 19 is
As shown in FIG. 7C, there are 44 of them in the maximum level inversion interval T _nax3 , and the final count value of the 6-bit counter 10 at the maximum level inversion interval T _nax3 is "44". . As a result, the maximum count value held in the latch section 12 is "44",
As shown in FIG. 7D, the presettable down counter 13 receives an edge pulse at the load terminal L.
After P _e is supplied, the master clock pulse
Since an output pulse P _h is generated every time P _n is counted by 44, the frequency of the output pulse P _h is 1/2 of the frequency of the pulse P _f , and the maximum level inversion interval T _nax3 in the read reproduction signal S ₃ In the period corresponding to , 22 output pulses P _h will be input. Therefore, in this case as well, the bit clock pulse BC obtained by dividing the output pulse P _h by 1/2 corresponds to 11 pulses, as shown in FIG. 7E.

As is clear from the above, not only when the rotation speed of the digital audio disk is the normal rotation speed, but also when it is twice the normal rotation speed or when it is 1/2 the normal rotation speed. , a bit clock pulse is obtained in which 11 pulses correspond to the maximum level inversion interval in the read and reproduced signal, and as a result, the digital audio
Even if the disk rotation speed is normal,
Even when the rotational speed is significantly changed from the normal rotational speed, the bit clock pulses necessary for demodulating the read and reproduced signal at that time can be obtained.

In the above example, the 1/2 frequency divider 14 is provided at the output end of the presettable down counter 13, but the 1/2 frequency divider 14 is not limited to this, and generally 1/M A 1/M frequency dividing section that performs frequency dividing operation (where M is a positive integer) can be used. In that case, in place of the 1/22 frequency divider 19 provided at the output end of the master clock pulse generator 18, a 1/11/M frequency divider that performs a 1/11/M frequency divider operation is provided. is provided, and the binary code generating section 20 is assumed to generate a binary code representing "11·M/2".

Furthermore, in the above example, a signal is reproduced from a digital audio disk on which a digital signal with a maximum level inversion interval of 11 channel bits is recorded for modulation, and the read and reproduced signal is The normal number of bit clock pulses that should correspond to the maximum level reversal interval in The master clock pulse At the output end of the generating section 18, a 1/K.M frequency divider that performs a 1/K.M frequency division operation is provided in place of the 1/11.M frequency division section, and the binary code generation section 20 is It is sufficient to generate a binary code representing "K.M/2", and furthermore, the frequency f of the master clock pulse P _n can be read and obtained when the disk is being rotated at the normal rotation speed. It is sufficient if the final count value of the 6-bit counter 10 at the maximum level inversion interval in the read and reproduced signal is selected to be K.multidot.M. The clock regeneration circuit according to the present invention can be used with devices other than digital audio disks.
Of course, the present invention can also be applied to a disc player that reproduces signals from a disc on which digital signals are recorded using the run-length limited code modulation method.

Effects of the Invention As is clear from the above explanation, according to the clock regeneration circuit for a disk player according to the present invention,
Of course, if the length of each level inversion interval of the read and reproduced signal from a disk on which a digital signal modulated using the run-length limited code modulation method is recorded is a regular length, Even if the length changes significantly from the normal length, the change can be followed and the bit clock pulse required for demodulating the read and reproduced signal at that time can be appropriately obtained. Therefore, even when the disc player is in the high-speed search operation mode, clock reproduction is performed based on the read reproduction signal.
The necessary bit clock pulses can be obtained to demodulate the read and reproduced signal, and there is no need to provide a rotation pulling circuit to pull the disk rotation speed into a relatively narrow specific rotation speed range and hold it there. Clock regeneration can be performed.

Furthermore, a disk player using the clock reproduction circuit according to the present invention can change the pitch of the reproduced audio signal over a wide range when reproducing an audio signal from a digital audio disk. It is possible to have the function of freely changing the pitch of the .

In addition, each part of the clock reproduction circuit for a disc player according to the present invention is digitized, and is suitable for forming as a digital integrated circuit.

[Brief explanation of the drawing]

FIG. 1 is a waveform diagram showing read reproduction signals and bit clock pulses from a digital audio disk, FIG. 2 is a block connection diagram showing a clock reproduction circuit of a conventional disc player, and FIG. 3 is a diagram showing a clock reproduction circuit of a conventional disc player. Block connection diagram showing an example of a clock regeneration circuit of a disc player, No. 4
5, 6, and 7 are waveform diagrams for explaining the operation of the example shown in FIG. 3, respectively. In the figure, 4 is an edge detection section, 10 is a 6-bit counter, 11 is a maximum value holder, 12 is a latch section, 13 is a presettable down counter, 1
4 is a 1/2 frequency divider, 15 is an output terminal, 17 is a 1/256 counter, 18 is a master clock pulse generator, and 19 is a 1/22 frequency divider.

Claims (1)

[Claims] 1. A reproduced signal obtained by reading from a rotating disk on which a digital signal modulated with defined maximum and minimum level inversion intervals for levels corresponding to "1" and "0" is recorded. supplied,
A master clock pulse generator and a 1/K·M frequency division of the master clock pulse from the master clock pulse generator (where K is a regular bit clock pulse that should correspond to the maximum level inversion interval in the above reproduced signal). (M is a positive integer); and a first counter that counts pulse outputs from the first frequency dividing section at each level inversion interval of the reproduced signal. and,
a maximum value holding section that holds the maximum count value of the first counter within a predetermined period; and a maximum value holding section that holds the maximum count value of the first counter within a predetermined period; comprising a second counter that generates a pulse, and a second frequency dividing section that divides the pulse output from the second counter by 1/M,
The final count value of the first counter at the maximum level inversion interval in the reproduced signal obtained by reading the frequency of the master clock pulse when the rotary disk is rotated at a normal rotation speed is K. A clock recovery circuit for a disk player, wherein the bit clock pulses are obtained from the second divider section.