JPH0567171A - Logic circuit generating system - Google Patents

Abstract

PURPOSE:To simplify the processing in the case of insertion of a logic circuit. CONSTITUTION:This logic circuit generating system is provided with a logic circuit read means 1 which reads in a logic circuit file 7, a macro circuit inserting means 2 which inserts another logic circuit (macro circuit) to the read-in logic circuit, a connection information designating means 3 which designates connection information of the original circuit and the inserted macro circuit, a connection destination deleting means 4 which deletes the circuit made unnecessary by macro insertion from the original circuit, a macro circuit connecting means 5 which connects the macro circuit to the original circuit based on connection information, and a logic circuit means 6 which writes a generated logic circuit in the file.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of making a logic circuit, and more particularly to a method of making a logic circuit when another logic circuit is inserted in a certain logic circuit.

[0002]

2. Description of the Related Art When a circuit is logically synthesized, the electrical characteristics may not be satisfied even if the logical specifications are satisfied.
For example, the clock signal and the like become the same signal. Therefore, it is necessary to insert a distribution circuit that distributes a clock signal or the like after the logic synthesis processing.

Conventionally, in this type of logic circuit creation, when inserting a logic circuit, the circuit diagram had to be modified using a logic circuit diagram creation editor. In particular, when a logic circuit is automatically synthesized by an automatic logic synthesizer, it may not have graphic information, so the circuit diagram of the automatically synthesized logic circuit must be generated and then the circuit diagram must be modified. .

[0004]

In the above-mentioned conventional logic circuit creation method, when inserting a logic circuit, the circuit diagram must be manually corrected by using an editor, and mistakes at the time of correction are mixed. There was a problem that it was easy.

Further, in a logic circuit such as a logic-synthesized circuit that does not have graphic information, the circuit diagram must be generated after the circuit diagram is generated by the circuit diagram generator, and the operation becomes complicated. However, there is also a problem that it is difficult to find a correction part because the circuit diagram is automatically generated.

[0006]

A method of creating a logic circuit according to the present invention comprises a logic circuit reading means for reading a logic circuit file and a macro circuit inserting means for inserting another logic circuit (macro circuit) into the read logic circuit. , Connection information specifying means for specifying connection information of the original circuit and the inserted macro circuit, connection destination deleting means for deleting the unnecessary circuit from the original circuit by inserting the macro, and connection information Originally, it has macro circuit connecting means for connecting the macro circuit to the original circuit, and logic circuit writing means for writing the created logic circuit in a file.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the present invention.

The logic circuit reading means 1 is a means for reading a manually designed or logic synthesized logic circuit file 7. The macro logic circuit inserting means 2 is means for reading the macro logic circuit file 8 and inserting it into the circuit read by the logic circuit reading means 1.

The connection information designating means 3 designates the connection information file 9 in which the connection information between the logic circuit read by the logic circuit reading means 1 and the macro circuit is stored, and the net at the cut portion of the macro circuit is set as the logic circuit This is a means for drawing to the upper hierarchy with the same signal name as the connection portion with the logic circuit read by the reading means 1.

The connection destination deleting means 4 is means for deleting an unnecessary circuit from the logic circuit read by the logic circuit reading means 1 by inserting a macro circuit.

The macro logic circuit connecting means 5 is means for connecting the net of the cut portion generated in the macro circuit inserted by the macro logic circuit inserting means 2 to the circuit read by the logic circuit reading means 1. Logic circuit writing means 6
Is a means for writing the logic circuit created by the above method into the logic circuit file 7.

FIG. 2 is a process flow showing a process of reading the connection information, generating a net in the upper layer of the inserted macro circuit, and connecting the net, and has the following procedure.

A file in which the correspondence of the connection between the macro circuit and the original logic circuit is described is read.

A net is generated in the upper layer from the inter-layer connector of the macro circuit corresponding to the signal name of the logic circuit of the connection destination.

By inserting the macro circuit, the unnecessary circuit is deleted from the original logic circuit.

The net of the macro circuit generated in the net of the connected logical circuit is connected.

FIG. 3 is a process outline showing a process for inserting a circuit.

That is, when an attempt is made to insert the logic circuit shown in FIG. 3B into the logic circuit shown in FIG.
3B is inserted as the macro of FIG. 3A (FIG. 3C).

On the basis of the connection information file 9, a net corresponding to the cut-out net of B is generated in the higher order of the macro circuit (FIG. 4 (A)).

Since a, b, c and d are connected to the macro circuit, the circuit originally connected to a, b, c and d becomes unnecessary and is deleted from FIG. 3 (A) (FIG. 4 ( B)).
The net generated from the macro circuit is connected to the figure in FIG. 3 (A) (FIG. 5).

[0022]

As described above, according to the present invention, when another logic circuit is inserted into one logic circuit, the logic circuit can be inserted without modifying the circuit diagram. The connection process has the effect of eliminating mistakes. Further, there is an advantage that even a logic circuit having no graphic information such as a logic circuit by logic synthesis can be inserted without generating graphic information.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 shows a processing flow of the embodiment shown in FIG.

FIG. 3 shows a state of processing when a circuit is inserted.

FIG. 4 shows a processing state when a circuit is inserted.

FIG. 5 shows a state of processing when a circuit is inserted.

[Explanation of symbols]

 1 logic circuit reading means 2 macro logic circuit inserting means 3 connection information designating means 4 connection destination deleting means 5 macro logic circuit connecting means 6 logic circuit file writing means 7 logic circuit file 8 macro logic circuit file 9 connection information file

Claims (1)

[Claims] 1. A logic circuit reading means for reading a logic circuit file, a macro circuit inserting means for inserting another logic circuit (macro circuit) into the read logic circuit, and connection information of the original circuit and the inserted macro circuit. A connection information specifying means to specify, a connection destination deleting means to delete an unnecessary circuit from the original circuit by inserting the macro, and a macro to connect the macro circuit to the original circuit based on the connection information. A method of creating a logic circuit having circuit connection means and logic circuit writing means for writing the created logic circuit in a file.