JPH11219379A - Altering method for vhdl model - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate a new language model by generating a shell language model by covering a layer which is one layer above a specific language model with an ideal shell and altering into the shell language. SOLUTION: A very-high-speed integrated circuit hardware description language(VHDL) model read-in part 11 reads in a normal VHDL model 2. A shell VHDL generation part 12 automatically generates a shell VHDL model as a general model from the read-in normal VHDL model. The VHDL model is generated by covering the layer which is one layer above the normal VHDL model 2 with the ideal shell. Further, a specific alteration merging part 13 adds new specifications 3 to the shell VHDL. To add the new specifications 3, a function alteration part corresponding to the specification alteration of the new specifications 3 is merged with the shell VHDL model. Further, a normal model addition part 14 functions to add the normal model to the shell VHDL model of the generated new function. Consequently, the new VHDL model 4 is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to VHDL (Very H
igh Speed Integrated Circuit Hardware Description
Language) How to change the model
A method for modifying a VHDL model created by the HDL language.

[0002]

2. Description of the Related Art The VHDL language is a language used in a circuit design support apparatus such as an LSI. In this design support apparatus, a circuit such as an LSI is logically designed using a VHDL language instead of an actual circuit configuration. Thus, the operation of the LSI or the like can be logically confirmed.

The circuit design in the VHDL language includes an entity section for describing connection information (input / output pin information) between the circuit and the outside, an architecture section for describing the operation of the circuit, And a configuration unit that describes the correspondence between these entity units and the architecture unit. Then, the corresponding VHDL model of the circuit is created by describing the circuit in accordance with the VHDL format by the architecture unit, the entity unit, the configuration unit, and the like. Is being verified.

Further, in the prior art, V
When changing the function of an existing VHDL model created in the HDL language, a new model (similar model) is created by replacing the VHDL model according to the function change.
That is, as shown in FIG. 3, the circuit designer manually changes the existing model A31 to create a similar model B32, a similar model C33, a similar model D34, or the like.

[0005]

However, in the case of a method of creating a new VHDL model by changing an existing VHDL model as in the above-described conventional technique, a part of the existing VHDL model is changed or modified. It is necessary to reconfirm the quality and the like of the completed new VHDL model throughout, and it takes time to create it. Further, by modifying the existing VHDL model, mistakes and the like are likely to be mixed, and the quality of the new VHDL model may be deteriorated.

It is an object of the present invention to provide a method of changing a VHDL model that can easily create a new VHDL model from an existing VHDL model without the above-mentioned problems.

[0007]

According to a method of changing a VHDL model of the present invention, a shell VHDL model is created by putting a logical shell on one layer of an existing VHDL model, and
A new VHDL model is created by changing the DL model.

[0008] More specifically, the change of the shell VHDL model is performed by merging a function change portion corresponding to a desired specification change into the shell VHDL model. Further, the merging of the function changed portion is performed by optimizing by logic synthesis to eliminate unnecessary redundant circuits.

In the present invention, since the existing VHDL model is diverted by putting a shell over the existing VHDL model, logic verification of the shell VHDL model is not required at all. For this reason, it is easy to confirm the quality of the completed new VHDL model again.

[0010]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 shows a VHDL model creation system 1 for performing the VHDL model changing method of the present invention. This VHDL creation system 1 is a VHD
It comprises an L model reading unit 11, a shell VHDL creating unit 12, a specification change merging unit 13, an existing model adding unit 14, and the like.

Here, the VHDL model reading section 11 reads an existing VHDL model 2. Also shell V
The HDL creation unit 12 automatically creates a shell VHDL model as a general-purpose model from the existing VHDL model 2 that has been read. The VHDL model is created by putting a logical shell on one layer of the existing VHDL model 2. The specification change merge unit 13 adds the new specification 3 to the shell VHDL. The addition of the new specification 3 is performed by merging a function change portion corresponding to the specification change according to the new specification 3 into the shell VHDL model. Further, in this case, merging of the function changed portions is performed by optimizing by logic synthesis to eliminate unnecessary redundant circuits. Further, the existing model adding unit 14 includes the new function shell VHD thus created.
Functions to add an existing model to the L model. Thus, the VHDL model creation system 1 creates a new VHDL model 4 from the existing VHDL model 2.

Next, a specific example of creating a new VHDL model from an existing VHDL model will be described with reference to FIG. First, in FIG. 2, an existing VHDL model 21 is covered with a logical shell, and a shell model 22 serving as a general-purpose model is created. More specifically, the shell model 22 is created as follows, for example. First, using the description of the VHDL language in the existing VHDL model 21, the external connection information is described by the entity unit. That is, the shell model "k
ara ", input terminals a, b, c, d, e, output terminals f,
If g, h, i, and j are used, the entity unit is as follows.

[0013]

(Equation 1)

The operation is described by the architecture section. Here, the input / output terminals of the existing model kizon are described as components, and the terminals described in the entity part are mapped in the port map description as follows.

[0015]

[Equation 2] architecture arc_kara of kara is component kizon port (signal a, b, c, d, e: in std_logic; signal f, g, h, i, j: out std_logic); end component; begin kizon_C0: kizon port map (a, b, c, d, e, f, g, h, i, j); end arc_kara;

Then, in the configuration section, the entity section of the kara model is associated with the architecture section and the kizon model. In the case of this example, it is as follows.

[0017]

[Equation 3] configuration cfg_kara of kara is for arc_kara for kizon_C0: kizon use configuration work.cfg_kizon; end for; end for; end cfg_kara;

Then, the shell model of the entity unit, the architecture unit, and the configuration unit created as described above is output. Next, similar models 23, 24, and 25, which are new VHDL models, are created by appropriately inputting and merging a function change portion with respect to the shell model E.

[0019]

As described above, according to the VHDL model changing method of the present invention, since the existing VHDL model is not changed at all, the time for quality confirmation is shortened.
A new VHDL model can be easily created.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing a VHDL model creation system for executing a VHDL model changing method of the present invention.

FIG. 2 is an explanatory diagram showing an example of creating a new VHDL model from an existing VHDL model according to the method of the present invention.

FIG. 3 is an explanatory view showing a conventional technique.

[Explanation of symbols]

 1 VHDL model creation system 11 VHDL model reading unit 12 Shell VHDL creation unit 13 Specification change merge unit 14 Existing model addition unit

Claims (3)

[Claims] 1. A shell VHDL model is created by overlaying a logical shell on one layer of an existing VHDL model, and a new VHDL is created by changing the shell VHDL model.
A method for changing a VHDL model, comprising creating a model. 2. The method according to claim 1, wherein the change of the shell VHDL model is performed by merging a function change portion corresponding to a desired specification change into the shell VHDL model.
How to change the HDL model. 3. The changing method according to claim 2, wherein the merging of the function changed portions is performed by optimizing by logic synthesis to eliminate unnecessary redundant circuits.