JP2007011912A - Model generation system, model generation method and program therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide technology for reducing a creation time of an IBIS model and improving quality of the IBIS model. <P>SOLUTION: In this model generation system, a circuit inside an FPGA is produced by use of buffer information and pin assignment information to be produced in circuit design by a VHDL file, and the IBIS model is output by use of an arranging/wiring tool provided from each vendor on the basis of the circuit. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a technique for creating a model for analyzing device characteristics by simulation.

  Usually, an element model obtained by modeling a device such as a semiconductor element by a semiconductor vendor is provided. A circuit is designed and simulated using an element model provided by this semiconductor vendor (for example, Patent Document 1).

Conventionally, FPGA (Field
In the case of a programmable device such as a Programmable Gate Array, an IBIS model (Input / Output Buffer), which is a general element model
When creating Information Specification Models, buffer information and pin numbers had to be entered manually using a text file.

  In addition, when creating an IBIS model, the number of pins that must be manually input is also a large number of pins (up to 1500 pins), which requires a large number of production steps.

  Here, a procedure for creating an IBIS model according to the prior art will be described.

  In the prior art, it is created by manually editing a text file.

  FIG. 7 shows an IBIS model creation system in the prior art.

  The storage unit 5 includes pin assignment information 51 and input / output information 52.

  The pin assignment information 51 is information created at the time of circuit design.

  The input / output information 5 indicates the buffer type.

  First, pin numbers are manually added to the IBIS model one by one based on the pin assignment information 51.

  Next, buffer types are manually assigned one by one to this pin number at 62.

  If pin numbers and buffer models are allocated for the total number of pins of the FPGA, the process ends at 63.

  As described above, in the creation of the conventional IBIS model, in the case of a programmable device such as an FPGA, the IBIS model must be created based on the buffer model and the pin number set by each user. However, there are the following problems.

  The first problem is that a large number of man-hours are required for editing the IBIS model in the case of a multi-pin (up to 1500 pins).

The second problem is that mistakes are likely to occur because the IBIS model is created manually.
JP 2002-245112 A

  Therefore, the problem to be solved by the present invention is to solve the above-mentioned problems, and to provide a technique for realizing shortening of the creation time of the IBIS model and improvement of the quality of the IBIS model.

The first invention for solving the above-described problems is
A model generation system,
Creating means for creating circuit information and constraint information based on pin information indicating information about the pins of the device;
And generating means for generating a model based on the created circuit information and constraint information.

According to a second invention for solving the above-mentioned problem, in the first invention,
The creation means is means for creating constraint information from a buffer type and pin number of the pin information.

A third invention for solving the above-described problem is the invention described in the first or second aspect,
The creation means is means for creating circuit information from information on the direction of the pin information and signal information.

A fourth invention for solving the above-described problem is
A model generation method,
A creation step for creating circuit information and constraint information based on pin information indicating information about the pins of the device;
And generating a model based on the generated circuit information and constraint information.

A fifth invention for solving the above-mentioned problems is the above-mentioned fourth invention,
The creating step includes
It is a step of creating constraint information from the buffer type and pin number of the pin information.

A sixth invention for solving the above-described problem is the above-described fourth or fifth invention,
The creating step is a step of creating circuit information from direction information and signal information of the pin information.

The seventh invention for solving the above-mentioned problem is
A model generation system program comprising:
Creating means for creating circuit information and constraint information based on information about the pins of the device;
It is made to function as a production | generation means which produces | generates a model based on the created said circuit information and constraint information.

An eighth invention for solving the above-described problem is the seventh invention, wherein
The program is
The creation means functions as means for creating constraint information from the buffer type and pin number of the pin information.

A ninth invention for solving the above-described problems is the seventh or eighth invention, wherein
The program is
The creation means functions as means for creating circuit information from information on the direction of the pin information and signal information.

  The present invention uses a pin assignment information and buffer information that must be created at the time of circuit design to create a circuit in the FPGA as a VHDL file, and uses a placement and routing tool provided by each vendor based on this circuit. By outputting the IBIS model, it is not necessary to manually create the IBIS model. In addition, there is no human error that occurs when creating an IBIS model.

  According to the present invention, the following effects can be obtained.

  The first effect is that the IBIS model is created without human intervention, and therefore the man-hours can be reduced compared with the case where the IBIS model is created manually.

  The second effect is that human error is eliminated, so that the quality of the created model can be improved.

  The present invention is a system for creating an IBIS model used for transmission line simulation in multi-pin devices such as FPGA and PLD.

  First, the configuration of each part of the system of the present invention will be described.

  FIG. 1 is a block diagram of a model generation system as an embodiment of the present invention.

  The model generation system of the present invention includes a design information storage unit 1, a file generation unit 2, and a placement and routing tool 3.

  Here, each component will be described.

  The design information storage unit 1 includes pin information 11 and input / output information 12 as device design information.

  The pin information 11 stores a pin number necessary for creating an IBIS model. This pin number is a number that uniquely identifies a pin.

  The input / output information 12 stores various information related to the pins of the device. The pin number, signal name, direction, buffer type, and other information are stored in association with each other. Has been. An example of the input / output information 12 is shown in FIG. The input / output information 12 is data created when a device (circuit) is designed.

  The pin number is a number for uniquely identifying the pin, and corresponds to the pin number stored in the pin information 11.

  The signal name indicates the type of signal input to or output from the pin.

  The direction indicates the input / output direction of the pin, that is, input, output, and bidirectional.

  The other information is various information related to the pin other than the signal name, direction, and buffer type.

  The buffer type indicates the buffer type of the pin.

  The file generation unit 2 includes a circuit creation unit 21.

The circuit creation unit 21 reads the pin information 11 and the input / output information 12. Then, based on the pin information 11, a circuit in the device that satisfies the input / output information 12 is created, and information regarding the function of the circuit is expressed as VHDL (Very High Speed Integrated Circuit Hardware).
Output as a Discription Language) file. FIG. 3 is an example of data when the information regarding the function of the circuit created by the circuit creation unit 21 is output as a VHDL file. The VHDL file is a type of HDL and has various functions for describing the operation of the electronic circuit. Furthermore, a device having a complicated operation such as a microprocessor can be described, and a circuit diagram can be created from VHDL by using synthesis software.

  Further, the circuit creation unit 21 generates a restriction file having a format as shown in FIG. 4 from the pin number and buffer type of the input / output information.

  Here, creation of a circuit in the device will be described in detail with reference to FIG. Here, description will be made using an OR circuit.

  Based on the pin number described in the pin information 11, the circuit creation unit 21 searches the input / output information 12 for information on the direction associated with the pin number. Then, a pin number whose pin direction is input is connected to the logic circuit, and a signal associated with this pin is input. A circuit is created by connecting the output from this logic circuit to all the pin numbers whose pin directions of the pin information 11 are outputs. The circuit creation unit 21 outputs information regarding the function of the created circuit as a VHDL file.

  The place and route tool 3 is a tool provided by each device vendor. Further, the placement and routing tool 3 generates an IBIS model based on the constraint file 21 and the VHDL file 22. Note that any method may be used to generate the IBIS model based on the constraint file 21 and the VHDL file 22.

  Next, the operation of the present invention will be described.

  FIG. 6 is a flowchart for explaining the operation of the present invention.

  The circuit creation unit 21 reads the pin number, signal name, buffer type, and pin direction (step S1).

  The circuit creation unit 21 generates a constraint file from the pin number and the buffer type (step S2).

  Further, the circuit creation unit 21 connects the pin number whose pin direction of the pin information 11 is input to the logic circuit, and inputs a signal corresponding to the pin number (step S3).

  Then, the output from this logic circuit is connected to all the pin numbers in which the pin direction of the pin information 11 is the output (step S4).

  It is confirmed whether all types of logic circuits, for example, AND, OR, NOT, etc. are connected (step S5).

  It is confirmed whether steps S3 to S5 have been performed for all input pins (step S6).

  As described above, the present invention uses the input / output information (pin assignment information and buffer information) that must be created at the time of circuit design to create a circuit in the FPGA as a VHDL file, and each vendor based on this circuit. Since the configuration is such that the IBIS model is output using the place-and-route tool provided from the above, it is not necessary to manually create the IBIS model. In addition, there is no human error that occurs when creating an IBIS model.

  Note that the above-described circuit creation unit may realize the same functions and operations as those of the above-described embodiments by a processor that operates according to a program, a memory that stores information, and a storage medium.

FIG. 1 is a block diagram of the present invention. FIG. 2 is an example of data. FIG. 3 is an example of a VHDL file. FIG. 4 is an example of a constraint file. FIG. 5 is a diagram for explaining the circuit creation unit. FIG. 6 is a diagram for explaining the operation. It is a figure for demonstrating a prior art.

Explanation of symbols

11 Pin information 12 Input / output information 21 Circuit creation unit 22 VHDL file 23 Constraint file 31 FPGA design tool 33 IBIS model

Claims (9)

A model generation system,
Creating means for creating circuit information and constraint information based on pin information indicating information about the pins of the device;
A model generation system comprising generation means for generating a model based on the created circuit information and constraint information.   The model generation system according to claim 1, wherein the creation unit is a unit that creates constraint information from a buffer type and a pin number of the pin information.   The model generation system according to claim 1, wherein the creation unit is a unit that creates circuit information from direction information and signal information of the pin information. A model generation method,
A creation step for creating circuit information and constraint information based on pin information indicating information about the pins of the device;
A model generation method comprising: a generation step of generating a model based on the created circuit information and constraint information. The creating step includes
5. The model generation method according to claim 4, wherein the constraint information is created from a buffer type and a pin number of the pin information.   6. The model generation method according to claim 4, wherein the creation step is a step of creating circuit information from information on the direction of the pin information and signal information. A model generation system program, the program comprising:
Creating means for creating circuit information and constraint information based on information about the pins of the device;
A program that functions as a generation unit that generates a model based on the created circuit information and constraint information. The program is
The program according to claim 7, wherein the creating unit functions as a unit that creates constraint information from a buffer type and a pin number of the pin information. The program is
The program according to claim 7 or 8, wherein the creating means functions as means for creating circuit information from information on the direction of the pin information and signal information.

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