JP6968736B2 - Circuit analysis device and circuit analysis program - Google Patents

Description

The present invention relates to a circuit analysis device and a program for circuit analysis.

The schematic viewer of a conventional logic synthesizer that arranges cells on the screen displayed as a result of the floor plan and calculates the wiring delay from the actual electrical resistance and capacitance from the design rules is the wiring delay, cell delay, and wiring. It is possible to display the degree of congestion and the like. However, this information alone may not be sufficient to clarify the reason for the timing violation. For example, there are cases where physical factors are involved, such as cells being arranged far apart and wiring delays increasing. In such a case, it is necessary to analyze why the cells are placed far away. However, the reason cannot be understood only from the information of the above-mentioned logic synthesizer. In the present specification, an element such as a flip-flop included in one chip and a module in which elements are assembled are regarded as one unit defined by wiring rules and timing constraints, and are referred to as "devices in one chip".

Patent Document 1 introduces an input / output AC standard that is greatly affected by wiring delay as one of the test standards of a logic circuit generated by a logic synthesis system. This input / output AC standard relates to specifications such as rising and falling times of input / output waveforms, propagation delay time between input / output terminals, setup time, hold time, minimum clock pulse width, and operating frequency. However, in the conventional method, it is said that the problem cannot be solved even if a logic synthesis tool and a layout tool are used to satisfy the above input / output AC standard.

The optimization processing apparatus according to the invention of Patent Document 1 automatically corrects a logic synthesis script and automatically generates layout constraints at the time of timing analysis when the input / output AC standard is not satisfied. By using a rule base (rule-based storage device 19) that includes a circuit configuration example that is effective in improving input / output AC standard violations, the logic synthesis script is modified including not only optimization constraints but also circuit configuration change instructions. That is.

Further, Patent Document 2 discloses a device for automatically generating a layout and a schematic by arranging the layout of the basic cell and the schematic of the basic cell by batting. In this device, by changing the wiring connection on the schematic in response to the change of the wiring connection point on the layout, it is possible to automatically generate a schematic that matches the wiring connection on the layout. According to the apparatus described in Patent Document 2, it is not necessary to manually modify the schematic as in the conventional case, and the design period can be significantly shortened.

Further, in Patent Document 3, whether or not the logic circuit diagram data conforms to a predetermined design rule is verified, and verification data is received from a design rule check device that gives the verification result as verification data, and the verification data is used. An error verification device that analyzes and detects an error portion that violates the design rule in the logic circuit diagram data for each error content and gives it as error analysis data is disclosed.

The device of Patent Document 3 receives the error analysis data, and when the error part is expressed in a function description language for showing a logical connection relationship and when the error part is expressed in a drawing format. Each of them is provided with a function description language and an error display means for displaying the error portion on a display device in a drawing format.

According to the device of Patent Document 3, since the error part contrary to the design rule is automatically detected and displayed, the error part confirmation work that relies on human hands becomes easy, and the time spent for DRC error verification is shortened. Therefore, the design efficiency can be improved.

Japanese Unexamined Patent Publication No. 2000-322458 Japanese Unexamined Patent Publication No. 2000-323574 Japanese Unexamined Patent Publication No. 07-141404

The one described in Patent Document 1 is not intended to be modified by stepping into physical factors or timing factors even if the logic synthesis script is automatically modified and layout constraints are automatically generated. , Was inadequate. Further, the one described in Patent Document 2 is intended to automatically generate a schematic that matches the wiring connection of the layout, and is not intended to optimize the logic circuit. Further, although an error part contrary to the design rule is automatically detected and displayed, as in the invention of Patent Document 1, the correction is not made by stepping into the physical factor and the timing factor, and the timing violation. It could not be used to elucidate the cause of.

The present invention has been made in view of the current state of design of such semiconductor devices, and an object thereof is to be able to perform an analysis that goes into physical factors and timing factors, and to deal with the causes. It is an object of the present invention to provide a circuit analysis device and a circuit analysis program capable of obtaining a synthesis constraint for the above at an early stage.

The circuit analysis device according to the present invention is a circuit analysis device that performs logic synthesis based on logic circuit design information, creates a netlist, further performs a floor plan, and executes circuit analysis, and the physical constraint information of the logic circuit design. Based on the above, there is a detour degree calculation means that calculates the detour degree, which is the degree to which the wiring distance under design between two devices in one chip detours with respect to the shortest distance, and one chip has a connection relationship. Two 1-chips corresponding to the 1-chip margin calculation means for calculating the 1-chip margin, which is the margin between 1-chip devices for all pairs, and the detour degree calculated by the detour degree calculation means. In addition to creating the detour degree display data that is the basis of the image representing the inner device, the distribution of the margin in one chip is calculated based on the magnitude of the margin in one chip calculated by the margin calculation means in one chip. For the display data creating means for creating the margin distribution display data that is the source of the image to be visually displayed and the display means for displaying the image, the detour display data and the margin distribution created by the display data creating means. It is characterized by comprising a display control means for displaying an image based on display data.

In the circuit analysis apparatus according to the present invention, the detour degree calculating means is characterized in that the ratio or difference between the shortest distance and the wiring distance under design is calculated as the detour degree.

The circuit analysis apparatus according to the present invention includes a margin calculation means for calculating a margin for a transmission time to be satisfied by a signal transmission time between two devices in one chip based on the timing constraint information of the logic circuit design. The display data creating means creates the margin display data that is the source of the image representing the calculated margin and the corresponding two devices in one chip.

The circuit analysis apparatus according to the present invention includes a margin calculation means for calculating a margin for a transmission time to be satisfied by a signal transmission time between two devices in one chip based on the timing constraint information of the logic circuit design. The display data creating means superimposes the margin display data, which is the source of the image representing the calculated margin and the corresponding two devices in one chip, on the detour display data, and displays the detour / margin. It is characterized by creating data.

The circuit analysis apparatus according to the present invention is characterized in that the margin calculation means calculates the time of the difference between the signal transmission time between two devices in one chip and the transmission time to be satisfied as the margin.

In the circuit analysis apparatus according to the present invention, the display data creating means is characterized in that the margin distribution display data which is the basis of an image for visually displaying the margin distribution in one chip is created by changing the color. do.

The circuit analysis program according to the present invention uses the computer in a circuit analysis apparatus provided with a computer that performs logic synthesis based on logic circuit design information, creates a netlist, further performs a floor plan, and executes circuit analysis. Based on the physical constraint information of the logic circuit design, the detour degree calculation means for calculating the detour degree, which is the degree to which the wiring distance under design between the two devices in one chip detours with respect to the shortest distance, is used for one chip. The 1-chip margin calculation means for calculating the 1-chip margin, which is the margin between 1-chip devices for all pairs that exist and have a connection relationship, and the detour degree calculated by the detour degree calculation means. In addition to creating detour degree display data that is the basis of an image representing two corresponding devices in one chip, in one chip based on the magnitude of the margin in one chip calculated by the margin calculation means in one chip. The detour display data created by the display data creating means for the display data creating means for creating the margin distribution display data which is the source of the image for visually displaying the margin distribution and the display means for displaying the image. It is characterized in that it functions as a display control means for displaying an image based on the margin distribution display data.

The circuit analysis program according to the present invention is characterized in that the computer is used as the detour degree calculating means to calculate the ratio or difference between the shortest distance and the wiring distance under design as the detour degree.

In the circuit analysis program according to the present invention, the computer is calculated with a margin for calculating the margin for the transmission time to be satisfied by the signal transmission time between two devices in one chip based on the timing constraint information of the logic circuit design. To function as a means, and to make the computer function as the display data creating means to create a margin display data which is a source of an image representing the calculated margin and the corresponding two devices in one chip. It is characterized by.

In the circuit analysis program according to the present invention, the computer is calculated with a margin for calculating the margin for the transmission time to be satisfied by the signal transmission time between two devices in one chip based on the timing constraint information of the logic circuit design. The computer is made to function as a means, and the computer is used as the display data creating means. It is characterized by having it function to create detour degree / margin degree display data again.

In the circuit analysis program according to the present invention, the computer is made to function as the margin calculation means to calculate the time of the difference between the signal transmission time between the two devices in one chip and the transmission time to be satisfied as the margin. It is characterized by that.

In the circuit analysis program according to the present invention, the computer is used as the display data creating means to create the margin distribution display data which is the source of the image for visually displaying the margin distribution in one chip by changing the color. It is characterized by making it function as such.

According to the present invention, it is possible to perform an analysis that goes into physical factors and timing factors, and it is possible to obtain synthetic constraints for dealing with the causes at an early stage.

The functional block diagram of the embodiment of the circuit analysis apparatus which concerns on this invention. The block diagram of the computer system which realizes the embodiment of the circuit analysis apparatus which concerns on this invention. The flowchart which shows the operation of embodiment of the circuit analysis apparatus which concerns on this invention. The figure of the display example which shows the content of one screen when the detour degree is displayed by the embodiment of the circuit analysis apparatus which concerns on this invention. The figure of the display example which shows the arrangement density of a device which can be imagined from the display of FIG. 4, and the figure of the display example which shows the arrangement density of the device which improved this. The figure of the display example which shows the content of one screen when the margin degree is displayed by the embodiment of the circuit analysis apparatus which concerns on this invention. The figure of the display example which shows the content of one screen when the detour degree and the margin degree are displayed by the embodiment of the circuit analysis apparatus which concerns on this invention. The figure of the display example which shows the content of one screen when the margin distribution is displayed by the embodiment of the circuit analysis apparatus which concerns on this invention.

Hereinafter, embodiments of the circuit analysis device and the circuit analysis program according to the present invention will be described with reference to the accompanying drawings. In each figure, the same components are designated by the same reference numerals, and duplicate description will be omitted. FIG. 1 shows a functional block diagram showing an embodiment of the circuit analysis apparatus according to the present invention. This device is composed of a computer system such as a personal computer or a workstation.

The circuit analysis device according to the embodiment includes an input unit 11 for inputting information, a file, or a command, a logic synthesis unit 12, a floor plan processing unit 13, and a circuit analysis unit 14. Logic circuit design information 21 is input from the input unit 11. The logic circuit design information 21 may be, for example, an RTL description of a logic circuit, and various constraints such as physical constraint information such as the physical length of wiring and timing constraint information such as transmission time and delay between wirings. Information (layout rules) etc. shall also be included.

The logic circuit design information 21 is sent to the logic synthesis unit 12. The logic synthesis unit 12 generates a netlist 22 by performing a logic total based on the logic circuit design information 21. The logic synthesis unit 12 has a function of modifying the created netlist 22 several times, but since it is not directly related to the present invention, it will not be described in detail here.

The floor plan processing unit 13 executes the floor plan based on the netlist 22 and obtains the floor plan result information 23. The floor plan result information 23 is composed of information such as the position of the device in each chip, the position of the wiring, and the delay of the wiring. In the present embodiment, physical constraint information such as the physical length of wiring and constraint information (layout rule) such as timing constraint information such as transmission time and delay between wirings, which are included in the logic circuit design information 21, are transmitted. Therefore, it is assumed that it is included in the floor plan result information 23.

The circuit analysis unit 14 includes a known timing analysis tool and the like, and in addition to analyzing the transmission time between paths to determine whether or not the circuit is a MET, the circuit analysis unit 14 has a detour degree calculation means 31, a margin calculation means 32, and a chip. The internal margin calculation means 33 is provided. The delay information and the like evaluated by the timing analysis tool are passed to the logic synthesis unit 12, and are used because it is necessary to optimize both the logic function and the layout in a well-balanced manner.

The detour degree calculating means 31 is the degree to which the wiring distance under design between two devices in one chip detours with respect to the shortest distance based on the physical constraint information of the logic circuit design based on the logic circuit design information 21. It calculates the degree of detour. The detour degree calculating means 31 may calculate the ratio or difference between the shortest distance and the wiring distance under design as the detour degree.

The margin calculation means 32 calculates the margin for the transmission time to be satisfied by the signal transmission time between the two devices in one chip based on the timing constraint information of the logic circuit design. The margin calculation means 32 may calculate the time of the difference between the signal transmission time between the two devices in one chip and the transmission time to be satisfied as the margin.

The in-chip margin calculation means 33 calculates the in-chip margin, which is the margin between the in-chip devices of all the pairs existing in one chip and having a connection relationship.

An output function unit 40 is connected to the circuit analysis unit 14. The output function unit 40 includes a display data creating means 41, a display control means 42, and a display means 43. The display means 43 is a display unit for displaying an image or the like, and the display control means 42 displays an image based on the display data created by the display data creation means 41 on the display means 43.

The display data creating means 41 creates the detour degree display data which is the source of the image representing the detour degree calculated by the detour degree calculating means 31 and the corresponding two devices in one chip. Further, the display data creating means 41 creates the margin display data which is the source of the image representing the margin calculated by the margin calculating means 32 and the corresponding two devices in one chip.

The display data creating means 41 superimposes the margin display data, which is the source of the image representing the calculated margin and the corresponding two devices in one chip, on the detour display data, and the detour / margin. It creates degree display data. The display data creating means 41 is a margin that is the basis of an image that visually displays the distribution of the margin in one chip based on the magnitude of the margin in one chip calculated by the margin calculation means 33 in one chip. It creates distribution display data. The range of one screen to be displayed can be a unit of partition described later, and when displaying the distribution of the margin in one chip, the inside of one chip is divided into several areas and displayed. You can do it.

The circuit analysis device configured as described above is configured by the computer system shown in FIG. That is, it is a device having a configuration in which an external storage device 52, a display device 53, and an input device 54 are connected to a computer main body 51 provided with a CPU or the like.

The computer main body 51 realizes the detour degree calculation means 31, the margin degree calculation means 32, the one-chip margin degree calculation means 33, and the display data creation means 41 by a program by the CPU.

The netlist 22 and the floor plan result information 23 are stored in the external storage device 52. The input device 54 corresponds to the input unit 11 and realizes a function of inputting the logic circuit design information 21. The logic circuit design information 21 may also be stored in the external storage device 52, and in this case, it can be configured to be taken out in response to an instruction from the input device 54. The display device 53 corresponds to the display control means 42 and the display means 43 in the output function unit 40.

The circuit analysis device configured as described above executes the program according to the flowchart of FIG. 3 and operates as each means of the computer main body 51. Hereinafter, the operation will be described with reference to this flowchart.

At the start, the logic circuit design information is taken in (S11), and the logic synthesis is performed based on the logic circuit design information to create the netlist 22 (S12). Next, the floor plan is performed based on the netlist 22, and the floor plan result information 23 is obtained (S13).

Next, circuit analysis (particularly timing analysis) is performed based on the floor plan result, and the request for the analysis result is taken in (S14). The analysis result requirements include a detour degree request, a margin degree request, a detour degree and margin degree request, and a one-chip margin margin request. Regarding the request for detour degree, the request for margin, and the request for detour and margin, information that can identify one device in one chip, such as the identification name of two devices in one chip or the device name of the device in one chip, is available. Entered. This information can be configured to be displayed with the device.

Following step 14, it is detected whether or not the detour degree request has been made (S21), and if YES, the detour degree calculation, the detour degree display data creation, and the detour degree display are performed (S22). Based on the physical constraint information of the logic circuit design, the detour degree, which is the degree to which the wiring distance under design between two devices in one chip detours with respect to the shortest distance, is calculated and corresponds to the calculated detour degree. The detour degree display data that is the source of the image representing the two devices in one chip is created. Here, the ratio or difference between the shortest distance and the wiring distance under design is calculated as the detour degree. Further, an image based on the display data created by the display data creating means is displayed to the display means for displaying the image.

As described above, the display as shown in FIG. 4 is performed. In the present embodiment, in displaying the image, the area of the required area in one chip is displayed as one partition. This one partition may be a unit of compilation. In FIG. 4, the timing path from the device B to the device C is shown, and the solid line is the wiring path of the synthesis result. Further, the numbers shown in the upper part of the solid line in FIG. 4 indicate that they are twice as long as the shortest path shown by the broken line. By displaying the detour degree, it is possible to know that the timing path forms a detour (detour) route instead of the shortest route. From this information, it can be inferred that wiring congestion or device placement congestion is occurring around the timing path. For example, since a large number of devices are densely arranged between the device B and the device C as shown in FIG. 5 (a), it is necessary to derive a constraint for relaxing the device density as shown in FIG. 5 (b). Can be done.

When the branch is made to NO in step 21 and when step S22 is completed, it is detected whether the request for the margin is made (S23), and if YES, the margin is calculated, the margin display data is created, and the margin is displayed. Do (S24). Based on the timing constraint information of the logic circuit design, the margin for the transmission time to be satisfied by the signal transmission time between the two devices is calculated, and it becomes the source of the image showing the calculated margin and the corresponding two devices. Create margin display data. Here, the time of the difference between the signal transmission time between the two devices and the transmission time to be satisfied is calculated as the margin. Further, an image based on the display data created by the display data creating means is displayed to the display means for displaying the image.

As described above, the display as shown in FIG. 6 is performed. The margin here is a numerical value of how much the delay can be maintained in the timing path even if the delay increases. MET calculates the transmission time (Arrival Time) actually required from the start point to the end point of the path and the specified time (Required Time) to be satisfied, and if the difference (Slack) is positive, it is determined to be MET, and if it is negative, it is determined to be VIOLATED. In the case, it is MET.

FIG. 6 displays the timing margin before and after the timing path in the timing path from the device B to the device C. In the example of FIG. 6, the timing path from device A to device B represents MET even if the delay of 0.543 is further increased, and the timing path from device C to device D is further increased by 0.230. Also indicates that it is a MET.

By displaying these margins, it is possible to know that there is a margin in the timing path before and after the timing violation, and it is sufficient to strengthen the timing optimization from device B to device C from this information. I understand. In order to strengthen the timing optimization of the path, it is easy to derive a constraint that weights the optimization priority for each timing path, and the design time can be shortened.

When branching to NO in step 23 and when step S24 is completed, it is detected whether the request for the detour degree and the margin degree has been made (S25), and if YES, the detour degree and the margin degree calculation, the detour degree and the margin degree are detected. Degree display data creation, detour degree and margin degree display are performed (S26). Based on the physical constraint information of the logic circuit design, the detour degree, which is the degree to which the wiring distance under design between the two devices detours with respect to the shortest distance, is calculated, and based on the timing constraint information of the logic circuit design, 2 The margin for the transmission time to be satisfied by the signal transmission time between two devices is calculated, and the margin display data that is the source of the image representing the calculated margin and the corresponding two devices is added to the detour display data. Create detour / margin display data by overlapping.

As a result, the display as shown in FIG. 7 can be performed. That is, it is possible to create a more accurate logic synthesis constraint by combining the detour degree and the margin degree as shown in FIG. 7, instead of using the detour degree and the margin element individually. For example, when a path having a high degree of detour is displayed even with a margin, it can be seen that the route from the device B to the device E is affected and the detour path is formed as shown in FIG. 7A. In this case, instead of controlling at a ratio that can be arranged as shown in FIG. 4, it is possible to derive a method of duplicating the device and avoiding the detour route as shown in FIG. 7 (b). The example of FIG. 7 (b) shows that it is possible to create a constraint that duplicates one device B of FIG. 7 (a).

When branching to NO in step 25 and when step S26 is completed, it is detected whether the request for the margin in one chip is made (S27), and if YES, the margin in one chip is calculated and the margin in one chip is calculated. Degree display data creation, 1 chip margin degree display is performed (S28).

The margin within one chip, which is the margin between devices in one chip for all pairs existing in one chip and having a connection relationship, is calculated, and within one chip based on the calculated magnitude of the margin within one chip. Create the margin distribution display data that is the basis of the image that visually displays the margin distribution of. Further, an image based on the display data created by the display data creating means is displayed to the display means for displaying the image.

FIG. 8 shows a display example of a margin distribution image. In the timing map of FIG. 8, the paths with strict timing are color-coded and displayed. That is, the margin distribution display data that is the basis of the image that visually displays the margin distribution in one chip is created by the color change. Here, the numerical value (unit is nanosecond) indicating the degree of timing violation is associated with the color, and the correspondence table is displayed on the screen. In this timing map, it is possible to know the tendency of timing violation in block units instead of displaying in timing path units such as detour degree and margin degree.

FIG. 8 shows that the area displayed in red or yellow color is wide in the arrangement area of the module modX, and there are relatively many paths causing timing violations of about −0.5 ns to -1 ns. There is. From this information, for example, a synthesis constraint that raises the priority of timing optimization can be derived for the arrangement region of the module modX shown in FIG.

When step S28 is completed, it is determined whether to end the process (S29), and if NO, the process returns to step S15 to continue the process, and if it branches to YES in step S29, the process ends.

11 Input unit 12 Logic synthesis unit 13 Floor plan processing unit 14 Circuit analysis unit 21 Logic circuit design information 22 Netlist 23 Floor plan result information 31 Detour degree calculation means 32 Margin calculation means 33 1 Chip in-chip margin calculation means 40 Output function Unit 41 Display data creation means 42 Display control means 43 Display means 51 Computer main unit 52 External storage device 53 Display device 54 Input device

Claims (12)

In a circuit analysis device that performs logic synthesis based on logic circuit design information, creates a netlist, performs a floor plan, and executes circuit analysis.
A detour degree calculation means for calculating the detour degree, which is the degree to which the wiring distance under design between two devices in one chip detours with respect to the shortest distance, based on the physical constraint information of the logic circuit design.
A means for calculating the margin in one chip, which is a margin between devices in one chip for all pairs existing in one chip and having a connection relationship, and a means for calculating the margin in one chip, which calculates the margin in one chip.
The detour degree display data that is the source of the image representing the detour degree calculated by the detour degree calculation means and the corresponding two devices in one chip is created, and the detour degree display data calculated by the one chip margin calculation means is created. A display data creation means for creating margin distribution display data that is the basis of an image that visually displays the distribution of margins in one chip based on the magnitude of margins in one chip.
A circuit analysis characterized in that the display means for displaying an image is provided with a display control means for displaying an image based on the detour degree display data created by the display data creation means and the margin distribution display data. Device. The circuit analysis apparatus according to claim 1, wherein the detour degree calculating means calculates the ratio or difference between the shortest distance and the wiring distance under design as the detour degree. A margin calculation means for calculating a margin for the transmission time to be satisfied for the signal transmission time between two devices in one chip based on the timing constraint information of the logic circuit design is provided.
The display data creating means according to claim 1 or 2, wherein the display data creating means creates margin display data which is a source of an image representing the calculated margin and the two devices in one chip corresponding to the margin. Circuit analysis device. A margin calculation means for calculating a margin for the transmission time to be satisfied for the signal transmission time between two devices in one chip based on the timing constraint information of the logic circuit design is provided.
The display data creating means superimposes the margin display data, which is the source of the image representing the calculated margin and the corresponding two devices in one chip, on the detour display data, and the detour / margin. The circuit analysis apparatus according to any one of claims 1 to 3, wherein display data is created. The circuit analysis apparatus according to claim 3 or 4, wherein the margin calculating means calculates the time of the difference between the signal transmission time between two devices in one chip and the transmission time to be satisfied as the margin. Any of claims 1 to 5, wherein the display data creating means creates margin distribution display data which is a source of an image for visually displaying the margin distribution in one chip by changing the color. The circuit analysis apparatus according to item 1. The computer in a circuit analysis device provided with a computer that performs logic synthesis based on logic circuit design information, creates a netlist, performs a floor plan, and executes circuit analysis.
A detour degree calculation means for calculating a detour degree, which is the degree to which the wiring distance under design between two devices in one chip detours with respect to the shortest distance based on the physical constraint information of the logic circuit design.
A means for calculating the margin in one chip for calculating the margin in one chip, which is the margin between devices in one chip for all pairs existing in one chip and having a connection relationship.
The detour degree display data that is the source of the image representing the detour degree calculated by the detour degree calculation means and the corresponding two devices in one chip is created, and the detour degree display data calculated by the one chip margin calculation means is created. A display data creation means for creating margin distribution display data that is the basis of an image that visually displays the distribution of margins in one chip based on the magnitude of margins in one chip.
For circuit analysis, the display means for displaying an image is made to function as a display control means for displaying an image based on the detour degree display data and the margin distribution display data created by the display data creation means. program. The circuit analysis program according to claim 7 , wherein the computer functions as the detour degree calculating means to calculate the ratio or difference between the shortest distance and the wiring distance under design as the detour degree. The computer is made to function as a margin calculation means for calculating a margin for the transmission time to be satisfied by the signal transmission time between two devices in one chip based on the timing constraint information of the logic circuit design.
Claims, wherein said computer as said display data creating means, be made to function so as to create the underlying margin display data of an image representing the said margin calculated and the corresponding two 1 chip device Item 7. The circuit analysis program according to Item 7. The computer is made to function as a margin calculation means for calculating a margin for the transmission time to be satisfied by the signal transmission time between two devices in one chip based on the timing constraint information of the logic circuit design.
Using the computer as the display data creating means, the detour degree display data is superimposed on the margin display data that is the source of the image representing the calculated margin and the two devices in one chip corresponding to the margin, and the detour degree is superimposed. The circuit analysis program according to any one of claims 7 to 9 , wherein the program is made to function to create margin display data. 9. The circuit analysis program described in. Claims as the display data creating means the computer, the color change, characterized in that to function distribution of margin in 1 chip to create the underlying margin distribution display data of an image to be visually displayed Item 4. The circuit analysis program according to any one of Items 7 to 11.

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