JP2864686B2 - Printed circuit board design method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to an improvement in a printed board design method for designing a single printed board by dividing it into a plurality of pattern blocks.

<Prior Art> Conventionally, in order to increase the efficiency in designing a printed circuit board, as shown in FIG. 11, a single printed circuit board is divided into, for example, pattern blocks A ₁ , A ₂ , and A _3. There is a design method in which the design block is divided and the designed blocks are edited and synthesized and integrated into one printed circuit board.

<Problems to be Solved by the Invention> However, in such a design method, each block pattern is often individually designed and synthesized in the form of an artwork, and always coincides with the connection information on the circuit diagram. These are not always the case, and there are many things that do not match.

Further, even when the design is made based on the connection information of the circuit diagram, similar mismatching occurs because many subsequent design changes are made on the actual board.

Furthermore, as shown in FIG. 12 to reuse pattern block A ₁ of Figure 11 as the standard circuit, the pattern block
If combined with B ₁ is the same.

The present invention has been made to solve such a problem, and even when the substrate is divided into pattern blocks and designed, the pattern of each block is consistent with the circuit diagram of the substrate and can be easily obtained. It is an object of the present invention to realize a method of designing a printed circuit board that can be integrated into a single board by combining blocks.

<Means for Solving the Problems> The present invention relates to a printed circuit board design method in which a printed circuit board is divided into a plurality of pattern blocks and designed, each block is edited and synthesized, and integrated into one printed circuit board. A net extraction step of extracting net information indicating the type of circuit element and the connection state from the pattern diagram of each pattern block, and net information of external terminals connecting pattern blocks in the extracted net information. A merge process to reduce the net information in a representation format in which the circuit elements are directly connected between the pattern blocks without passing through the net information of the external terminals, and the connection information obtained from the circuit diagram of the printed circuit board, The net information after the merge process is compared, and if there is a logically inconsistent part in consideration of pin exchange and gate exchange, one of the Comparing step of modifying the information, a printed circuit board design method characterized by comprising the.

<Operation> In the present invention, when editing and synthesizing a pattern block, the net information of the external terminal at the boundary between the blocks is deleted to reduce the net information, and the information is obtained from the circuit diagram of the printed circuit board. The printed circuit board is designed by comparing the connection information with the net information after the merge process, and matching them.

<Example> Hereinafter, the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a configuration example of a system for implementing a method according to the present invention.

In FIG, 1 ₁ and 1 ₂ is a pattern data input unit reads the pattern diagram of the pattern block A and pattern block B bisecting a printed board, respectively, enter the graphic data for these patterns in the system I do.

2 is a net extraction unit, which is a pattern data input device
1 ₁ and 1 lead data extracting means 21 ₁ for extracting connection data showing the connection how the pattern on the basis of the graphic data inputted from ₂ and 21 _2, connection data storage for storing the extracted connection data It is composed of parts 22 ₁ and 22 ₂ .

31 ₁ and 31 ₂ are net information creating means creates the net information from the data stored in the connection data memory unit 22 _1, 22 _2. 32 ₁ and 32 ₂ are net information storage unit for storing the net information created.

4 the pattern data input device 1 _1, 1 ₂ of the graphic data and the net information storage unit 32 ₁ and 32 ₂ of merged means for aligning the net information, Internet information stored net information after the matching 5 A storage unit 6 is an editing / synthesizing unit that edits and combines the pattern blocks A and B using the graphic data after the matching, and a board pattern storage unit 7 stores the combined board pattern.

8 ₁ and 8 ₂ are circuit diagram input devices for reading circuit diagrams of printed circuit boards, 9 is connection information extracting means for extracting connection information from the read data of the circuit diagram input devices 8 ₁ and 8 ₂ , and 10 is the extracted connection information. This is a connection information storage unit to be stored. Numeral 11 denotes comparison means for comparing the contents of the net information storage unit 5 and the contents of the connection information storage unit 10 to compare the connection on the substrate pattern with the connection on the circuit diagram. Numeral 12 is a difference data detecting means for detecting the difference obtained from the comparing means 11. The detection result back annotation is performed by being fed back to the circuit diagram input device 8 ₁ and 8 _2.

Reference numeral 13 denotes a pattern correction unit for correcting a board pattern diagram edited and synthesized based on the detection result of the difference data detection unit 12.

The printed circuit board is designed by the following procedure using the system configured as described above.

 The design procedure is divided into the following three steps.

(1) Step of extracting net from block (2) Step of matching net information and pattern (3) Step of comparing net between circuit diagram and pattern These steps will be specifically described.

(1) net extraction step pattern data input device 1 _1, 1 ₂ from block reads the substrate pattern, based on the graphic data is loaded, the lead data extracting means 21 _1, 21 ₂ shown in FIG. 2 In such a connection table, attribute data such as coordinate data, line width, and signal level are written for each portion of the substrate pattern. At this time, the net ID column is left blank.

Where all the attribute data is written, the lead data extracting means 31 _1, 31 _2, coordinate data written in connection table, line width, and check the connection of the signal level, etc. on the basis of the connection data Extract. The same net ID is given to the connection table for data existing on the same connection in the figure.

When the net ID is written in the connection table,
Net information creating means 31 _1, 31 _2, to create a net information on the basis of the contents of the connection table.

For example, in a pattern block as shown in FIG. 3, the net information is as shown in FIG.

Here, an external terminal is provided for a signal extending between the pattern blocks. An external terminal is provided with the same reference indicating the same signal between blocks.

When the net is extracted, the external terminals have data as if they were component pins.

The external terminal may be described as a component on the circuit diagram, but may be added as a terminator for arcwork imaging when designing the pattern / block.

(2) Step of Matching Net Information and Pattern This step consists of two steps: pattern merging and net information merging.

Pattern Merging Only the pattern data in a plurality of pattern blocks necessary to make one board data is synthesized.

External terminals used for each pattern block are excluded from the target of synthesis. That is, the reference of the signal handled by the external terminal or the identification ID of the external terminal is input to the merging means 4 and automatically deleted.

Merging of Net Information In this step, net information extracted from each pattern block is synthesized.

At this time, the net information of each block extracted in the step (1) is set as one net information using the external terminal as a key.

Specifically, the net information of each pattern block obtained from the connection table and the reference or identification ID of the external terminal are input to the merging means 4, the external terminal is deleted from the component name, and the same external terminal is connected to the net configuration. Merge the nets with each other and delete the external terminals from the net information.

For example, as shown in Fig. 5, SIGN (N is an integer)
In the pattern blocks A and B having the external terminals having the reference as the reference, the net information is merged as shown in FIG.

That is, the extracted net information is as shown in FIG. The merging means 4 merges the net information by performing the following processing.

(I) The component data $ COMP deletes a symbol having SIGN (N is an integer) as a reference.

(Ii) Net data $ NETS collects nets having the same external terminal into one and deletes the external terminal.

Thus, the net information becomes as shown in FIG. 6 (b). As a result of the merge, SIG1 and SIG2 are deleted, and the net information is rewritten into an expression format in which circuit elements are directly connected between the pattern blocks A and B.

At this time, the correspondence between the net name in the merged net information and the net name of the net information of each pattern block is output, and graphic data is created based on the connection table of each pattern block created in (1). Name the.

For example, the net names in the merged net information are as shown in FIG. In this figure, the net name is NET001, N
They are 1, 2, and 3 of ET002 and NET003. The net names are changed to A, B, and C according to the correspondence table shown in FIG. 8 for such a pattern, and the pattern is made as shown in FIG.

The pattern in FIG. 7 is as shown in FIG. 10 when the connection table is written.

(3) In the circuit diagram and the pattern of the net comparison step This step compares the connection information extracted from the circuit diagram input device 8 _1, 8 _2, the net information obtained in the step (2), of the component data deficiency And a difference between net data.

Based on the detected difference, the circuit diagram or the pattern is corrected so that both are matched.

In this way, the pattern blocks A and B are edited and combined, and integrated on one printed circuit board.

<Effects> According to the present invention, in the process of designing a block pattern, even if a mismatch occurs between the pattern of each block and the circuit diagram, the pattern is merged and the net information obtained from the pattern is merged. This unifies the substrate data. Thus, even when the board is divided into pattern blocks and designed, the pattern of each block matches the circuit diagram of the board, and the blocks can be easily combined and integrated into one board.

In addition, an already designed block can be easily combined with another block as a standard block and designed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration example of a system for implementing a method according to the present invention, FIGS. 2 to 10 are diagrams showing procedures of a method according to the present invention, FIGS. 11 and 12 FIG. 2 is a diagram showing a procedure of a conventional printed circuit board design method. 1 _1, 1 ₂ pattern data input device, 21 _1, 21 ₂ ...... connection data extracting means, 22 _1, 22 ₂ ...... connection data storage unit, 31 _1, 31 ₂ ...... net information creating unit, 32 _1, 32 ₂ , 5 ……
... Net information storage unit, 4... Merge means, 6... Edit / synthesis unit, 7... Substrate pattern storage unit, 8 ₁ , 8 ₂ ... Circuit diagram input device, 9. Information storage unit, 11... Net comparison means, 12... Difference data detection means, 13.

Claims (1)

(57) [Claims] 1. A method of designing a printed circuit board in which a printed circuit board is divided into a plurality of pattern blocks for design, each block is edited and synthesized, and integrated into one printed circuit board. A net extraction step of extracting net information indicating the type and connection state of the circuit element, and, in the extracted net information, deleting net information of an external terminal connecting between the pattern and the block to obtain a net of the external terminal. A merging step of reducing net information in a representation format in which circuit elements are directly connected between pattern blocks without passing through information, connection information obtained from a circuit diagram of a printed circuit board, and a net after the merge step Comparing information, and if there is a logically inconsistent part in consideration of pin exchange and gate exchange, a comparison step of correcting one of the information, A method for designing a printed circuit board, comprising: