JPH07239870A - Circuit and system - Google Patents

Abstract

PURPOSE:To provide a circuit CAD system which efficiently and quickly extracts the difference of connection information between two circuits and makes the net ID match with either of two circuits. CONSTITUTION:Circuit information read processing parts 32 and 33 which read in respective information of first and second circuits, circuit tables where element IDs, element information, numbers of pins, and pin pointers out of read circuit information are stored, circuit information storage tables 34 and 35 consisting of pin tables where net IDs accessed by pin pointers are stored, ID conversion tables 40 and 50 where net IDs of one of first and second circuits can be drawn from net IDs of the other, and a conversion table generation processing part 36 which refers to circuit information storage tables 34 and 35 and net ID conversion tables 40 and 50 to define the net of one circuit and that of the other as the master side and the slave side respectively with respect to nets having the same connection relations and makes the net ID on the slave side coincide with that on the master side are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit CAD system, and more particularly to a system for efficiently extracting a difference in connection information between two circuits at high speed and matching a net ID with one of the circuits.

[0002]

2. Description of the Related Art A circuit design support system (C
When AD) is performed, the circuit input by CAD is the same as the previous one, or there is a difference due to revision of the circuit, rewriting the circuit diagram, re-inputting the circuit diagram to a different tool, etc. Often you need to check.

Further, in the CAD tool, in order to speed up the processing, only the part changed when the circuit data is revised is different from the previous net ID (individual connection information between elements constituting the circuit). Identification IDs of pins having the same net ID are electrically set to the same electric potential), and the same parts are often made to have the same net ID.

In recent years, the circuit scale of LSIs, printed boards, etc. has increased, and the number of elements constituting one circuit (LSI, printed boards, etc.) has increased. CAD processing time is becoming longer.

Therefore, the mounting design work is started before the circuit design is completely completed, and the circuit design and the mounting design are performed in parallel to shorten the total design period. In this case, it is necessary to re-implement the design when the circuit design is finally completed, but if there are few changes or the range is narrow, make a difference between the circuit designed previously and the final circuit. By extracting, the information of the previous packaging design can be utilized as it is for most of the range, and the packaging design can be redone only for the changed portion. Therefore, it is necessary to quickly extract the extent of the changed portion and the place where the change is made from the two pieces of circuit information.

FIG. 7 is a diagram showing a method of expressing circuit information.
This expression method relates to a method of expressing circuit information on a memory of a computer. The element table i and the element table j are linked. Element table i is element ID1
And element information 2. Then, it has a pin table 10 in which a net ID to be connected is stored for each pin of each element. In this pin table 10,
A net ID is stored for each pin number. For example, the pin number 1 is connected to the net IDi, and the pin number 2 is connected to the net IDj (hereinafter the same). Element table j
The same applies to the above, and has a pin table 11. Then, the pins having the same net ID between the respective elements are electrically connected.

FIG. 8 is a diagram showing another representation method of circuit information. This representation has a net ID table 20, all the net IDs are stored in this net ID table 20, and an element ID 21 and pin information (pin number) 22 connected to the net for each of these net IDs. It is linked.

[0008]

As described above, when the circuit information is handled by the computer, the net ID is used to identify the individual connection information (net) between the elements forming the circuit.
have. The net ID is given to the pin (electrical input / output terminal) of each element, and the pins having the same net ID are electrically connected.

In the CAD of the packaging design, in order to quickly determine the portion where the circuit has changed, a portion having the same net ID as that of the previous circuit is treated as having not been changed in many cases. . Therefore, the net IDs of the portions that have not changed between the two circuits must be the same. Conventionally, if only circuit revision processing is performed, the CAD tool on the circuit design side has a structure in which the net ID of the portion that does not change does not change, but the same circuit design CAD is always used.
It is not always necessary to use tools, but the net ID can be obtained with the circuit CAD.
Is no longer immutable.

Further, not only the revised version but also the case where the circuit designed by another CAD tool is re-input and designed, the two circuits are compared and the difference between them is shown in order to confirm whether the input is correct. It is necessary. However,
In the conventional CAD system, since the comparison is performed using the circuit information shown in FIGS. 7 and 8, there is a problem that it takes a lot of time to extract the difference in a large-scale circuit.

The present invention has been made in view of such a problem. In two circuits, the difference in connection information can be efficiently extracted at high speed, and the net ID can be matched with one of the circuits. It is an object of the present invention to provide a circuit CAD system that can be used.

[0012]

FIG. 1 is a block diagram showing the principle of the present invention. It is assumed that the system shown in the figure is a system for comparing two circuits A and B (the first circuit is the circuit A and the second circuit is the circuit B). In the figure,
30 is a file for storing the information of the circuit A, 31 is the circuit B
Is a file that stores the information of. Various information regarding CAD is stored in these files. Reference numeral 32 is a circuit A information reading processing unit that reads circuit A information from the circuit A file 30, and 33 is a circuit B information reading processing unit that reads circuit B information from the circuit B file 31.

Reference numeral 34 is a circuit A information storage table for storing information about the circuit A read by the circuit A information reading processing section 32, and 35 is a circuit for storing information about the circuit B read by the circuit B information reading processing section 33. It is a B information storage table. These circuit information storage tables 34,
Reference numeral 35 is composed of a circuit table for storing information about elements and a pin table for storing net IDs of the elements (details will be described later).

40 and 50 are net ID conversion tables in which the net IDs of the other circuits can be subtracted from the net IDs of the circuits A and B, and 36 is the circuit information storage tables 34 and 35 and the net ID conversion table 40. , 50, one of the circuits is a master side and the other circuit is a slave side for nets having the same connection relationship,
It is a conversion table creation processing unit that matches the net ID on the slave side with the net ID on the master side.

When the circuit A is the master side and the circuit B is the slave side, 37 is a net ID for reading out a net ID different from the master side from the slave side net ID conversion table 50 and rewriting the net ID. A rewrite processing unit, 38 is connected to the circuit B information storage table 35, a difference list output processing unit that outputs the difference of the net ID as a difference list, 60 is a difference list, 39 is connected to the circuit B information storage table 35, Net ID on the circuit B side
Is a circuit B information writing processing unit that rewrites the file 31 of the circuit B in order to match the net ID of the circuit A side.

[0016]

The conversion table creation processing section 36 compares the circuit information storage tables 34 and 35 of the circuits A and B with the net ID conversion tables 40 and 50 to detect the difference in the net IDs of both circuits, The net ID of the slave side circuit is matched with the net ID of the master side circuit.
Then, the difference between both circuits is output as a difference list by the difference list output processing unit 38. As described above, according to the present invention, in two circuits, the difference in connection information can be efficiently extracted at high speed, and the net ID can be matched with one of the circuits.

[0017]

Embodiments of the present invention will now be described in detail with reference to the drawings. Assuming that the net IDs of the two circuits are completely independent of each other, it is very troublesome and time-consuming to verify whether or not the circuit connection relationships are the same with the expression method of FIG. . Further, with the expression method of FIG. 8, it is easy to extract the difference and set the same connection point to the same net ID, but it is necessary to compare each net with all connections, and the number of nets is large. In that case, it takes a lot of time.

Therefore, in the present invention, a method of first matching the net ID of one (slave side) to the other (master side) of the two circuits whose connections are the same, rather than extracting the difference first, is provided. To take. Then, the net ID that is not finally matched with the other becomes the difference between the two circuits. Therefore, a table (net I
D conversion table) was prepared.

FIG. 2 is a diagram showing a configuration example of the net ID conversion table. (A) shows the net ID conversion table 40 on the master side (circuit A side), and (b) shows the slave side (circuit B).
The side) net ID conversion table 50 is shown. In the net ID conversion table 40 shown in (a), the net ID of the circuit A is given as a subscript of the array. Then, the net ID of the circuit B and the net ID use flag are written in each array number. Circuit I net I
D is written in the area 41, and the net ID use flag is written in the area 42. In the use flag, "1" is written when it is used and "0" is written when it is empty.

The net ID conversion table 50 of (b) is
The net ID of circuit B is given as a subscript of the array. The net I of the circuit is added to each array element number.
D and the non-correspondence flag are written. Circuit A net ID
Is written in the area 51, and the unsupported flag is written in the area 52. The unsupported flag is "1" when unsupported
However, "0" is written when they correspond.

As described above, when the net ID is represented by a numerical value, if the net ID is secured as a continuous area in the memory of the computer, the address can be obtained by the difference between the starting point and the net ID, and the access can be made at once. This table is generally called an array table, but it does not necessarily have to be an array table, and may be a hash table based on net IDs.

Here, two circuits are referred to as circuit A and circuit B.
Assuming that the circuit A is a master, the circuit B is a slave, and the net ID of the circuit B is matched with that of the circuit A. The description will be given assuming that the net ID is a numerical value and becomes a subscript of the array table. The circuit information is based on FIG. 7.

The net ID conversion table of FIG. 2 will be further described. The net ID conversion table A of (a) is a table used for the conversion work, and the net ID of the circuit A is
It is a table accessed by. This table has a used flag for each net ID. The used flag is used to search for a free ID and give it when no correspondence is established when matching net IDs.

The net ID conversion table B in (b) finally shows the net ID for each net ID of the circuit B.
Is a table that stores the results of how to change
The net ID of the circuit B is used for access.
This table has a non-correspondence flag, and "1" is given to the net ID that is not associated with the circuit A and "0" is given to the net ID that is associated with it.

FIG. 3 is a diagram showing a configuration example of the circuit information storage table. (A) is a circuit A information storage table, (b)
Is a circuit B information storage table. The circuit A side is the master side, and the circuit B side is the slave. The circuit A information storage table 34 includes a circuit table A 34a and a pin table 34b.
The circuit B information storage table 35 includes a circuit table 35a and a pin table 35b.

The circuit table A stores an element ID, element information, the number of pins, and a pin pointer. And
A pin pointer is used to access the pin table 34b. The pin table 34b stores net IDs corresponding to the pin numbers. Circuit table B contains
The element ID, the element information, the number of pins, and the pin pointer are stored. Then, the pin table 35b is accessed by the pin pointer. The pin table 35b stores net IDs corresponding to pin numbers. Further, the pin table 35b is provided with a net non-correspondence flag, and a mark (for example, "1" or "0") is attached to a pin having a different connection relationship with the circuit A. The difference information can be notified by outputting these pieces of information to a list.

The processing of the net ID is carried out from the circuit information storage table shown in FIG. 3 by the net I of the same pins of the same circuit (which can be confirmed by comparing the element IDs) in the two circuits.
Data is filled in the net ID conversion tables A and B (see FIG. 2) while referring to D.

FIG. 4 is a flow chart showing an example of the overall operation of the present invention. Here, the circuit A is the master side, and the circuit B is
Is the slave side. For example, the circuit A can be considered as the circuit design side, and the circuit B can be considered as the mounting design side. First, circuit A
The information read processing unit 32 reads the circuit A from the circuit A file (see FIG. 1) 30 and creates the circuit A information storage table 34 (S1). Next, the circuit B information read processing unit 33 reads the circuit B from the circuit B file 31 and creates the circuit B information storage table 35 (S2).
Next, the conversion table creation processing unit 36 initializes (clears 0) the net ID conversion table A and the net ID conversion table B (S3), and the net ID conversion table A has been used by the circuit A that is the master. For the net ID of
The net ID used flag “1” is set up (S
4). This is the preparation work.

Next, the conversion table creation processing unit 36 processes the pins of all the elements of the circuit B to create the net ID conversion table B (S5, which will be described later in detail). Net I
When the D conversion table B is completed, the net ID rewriting processing unit 37 uses this table to rewrite all the net IDs written in the pin table 35b of the circuit B,
At the same time, the unsupported flag is written (S6). Thus, the circuit B has the same net ID as the circuit A for the same connection as the circuit A.

Next, it is judged whether the processing for matching the net IDs is performed or the difference portion is listed (S7). When listing the difference portion, the portion of the circuit information storage table B to which the uncorresponding flag is added is added. Is processed by the difference list output processing unit 38, and the difference list 60 is output (S8). Net I
When D is matched, the circuit B information writing processing unit 3
7 outputs the information of the circuit information storage table B to the circuit B file 31 (S9).

FIG. 5 is a flowchart showing an example of a net ID conversion table B creation processing operation. The conversion table creation processing unit 36 extracts one net ID (i) from the circuit B information storage table 35 (S1), and checks the i-th state of the unsupported flag of the net ID conversion table B (S).
2). If the unsupported flag is "1", it means that the net has not been processed yet, and the process is terminated without performing the process for the net. When the unsupported flag is "0", the conversion processing is performed because the net ID of the corresponding circuit A has not been converted yet.

The conversion table creation processing unit 36 retrieves the net ID (j) of the element pin of the circuit A corresponding to (i) from the circuit information storage table A (S3). Here, if there is no corresponding element, it is determined that there is no corresponding relationship, and the processing from step S7 is started.

If there is a corresponding element, the j-th element in the net ID conversion table A is checked (S4). At that time, if the net ID use flag is other than “0”, that is, “1”, the net ID is already used (that is, the connection relationship is not associated), and thus the net is processed as a net having no association relationship. In other words, the processing after step S7 is started.

If the net ID use flag is "0", the net ID is unused and can be associated. At this time, the net ID (j) is stored in the place of the net ID (i) in the net ID conversion table B (S
5), the net ID (i) is written in the place of the net ID (j) in the net ID conversion table A (S6), and the process is completed. At this time, the i-th item in the net ID conversion table B and the j-th item in the net ID conversion table A correspond to each other.

Next, the processing when there is no corresponding element in step S3 and when the used flag is set in step S4 will be described. In this case, the conversion table creation processing unit 36 determines that the net ID conversion table A
Find a vacant place (unused net number) (S
7). At this time, enter the net ID of the place that was vacant
(K). Then, the net ID (k) is stored in the place of the net ID (i) in the net ID conversion table B (S
8) The unsupported flag is set to "1" (S9).

Further, the conversion table creation processing unit 36 is
The net ID (i) is stored in the place of the net ID (k) in the net ID conversion table A (S10), the net ID used flag is set to "1" (S11), and the process is ended.

FIG. 6 is a diagram showing how the specific net ID conversion table of the present invention is changed. Specifically, this operation is performed by the conversion table creation processing unit 36. In the figure, 34 and 35 are pin tables of corresponding elements, which respectively show a circuit table A and a circuit table B. Reference numerals 40 and 50 denote a net ID conversion table A and a net ID conversion table B, respectively.

Now, the net ID of the arrow (←) pin
A conversion table is created for "12". Next, based on this net ID, the twelfth net ID conversion table B is checked. Since the uncorresponding flag is “1” in the content, it means that the circuit A and the circuit B are not yet corresponding.

Next, the net ID of the circuit table B
When the circuit table A corresponding to "12" is checked, the net ID is "400". Then, the 400th ID of the net ID conversion table A is checked. Then, since the net ID used flag is "1" and the net ID "4" of the circuit B is stored, it is understood that the net ID "12" cannot be replaced with the net ID "400".

Since the net number corresponding to the net ID “12” does not correspond, the net ID conversion table A
Search for a space from the beginning. As a result, the 91st is the net I
It can be seen that the D used flag is "0" and is empty.

Therefore, “91” is stored at the 12th position in the net ID conversion table B, and the unsupported flag is set to “0”. Next, at the 91st position in the net ID conversion table A, "1"
2 "is stored and the used flag is set to" 1 ".

As a result of the above, the corresponding net IDs of the circuit table A and the circuit table B are both "91", which means that there is a correspondence.

[Detailed Description of the Invention] As described above in detail, according to the present invention, the conversion table creation processing unit 36 includes the circuit information storage tables 34 and 35 of the circuits A and B and the net ID conversion. The tables 40 and 50 are compared and referenced to detect the difference between the net IDs of both circuits, and the net ID of the slave side circuit is matched with the net ID of the master side circuit. Then, the difference between both circuits is output as a difference list by the difference list output processing unit 38. As described above, according to the present invention, it is possible to provide a circuit CAD system capable of efficiently extracting a difference in connection information between two circuits at high speed and matching a net ID with one of the circuits.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a diagram showing a configuration example of a net ID conversion table.

FIG. 3 is a diagram showing a configuration example of a circuit information storage table.

FIG. 4 is a flowchart showing an example of the overall operation of the present invention.

FIG. 5 is a flowchart showing an example of a net ID conversion table B creation processing operation.

FIG. 6 is a diagram showing how a specific net ID conversion table of the present invention is changed.

FIG. 7 is a diagram showing a representation method of circuit information.

FIG. 8 is a diagram showing another representation method of circuit information.

[Explanation of symbols]

 30 circuit A file 31 circuit B file 32 circuit A information read processing unit 33 circuit B information read processing unit 34 circuit A information storage table 35 circuit B information storage table 36 conversion table creation processing unit 37 net ID rewriting processing unit 38 difference list Output processing unit 39 Circuit B information writing processing unit 40 Net ID conversion table A 50 Net ID conversion table B 60 Difference list

Claims (4)

[Claims] 1. A circuit information read processing section (32), (3) for reading information of each of a first circuit and a second circuit.
3), and a circuit information storage table including a circuit table in which element IDs, element information, the number of pins, and pin pointers are stored from the read circuit information, and a pin table in which net IDs accessed by the pin pointers are stored ( 34), (3
5), net ID conversion tables (40) and (50) capable of subtracting the net ID of the other circuit from the net IDs of the first circuit and the second circuit, and the circuit information storage table (34), Referring to (35) and the net ID conversion tables (40) and (50), for the nets having the same connection relationship, one of the circuits is set as the master side and the other circuit is set as the slave side, and the net ID of the slave side is set. A circuit CAD system comprising a conversion table creation processing unit (36) for matching the net ID on the master side. 2. A difference list output processing unit (38) for outputting only a portion having a different net ID between the master side circuit and the slave side circuit, and a slave side net ID conversion table (5).
0) is provided with a net ID rewriting processing unit (37) for rewriting the net ID, and the difference output processing unit (38) is provided with the information from the net ID rewriting processing unit (37). 2. The circuit CAD system according to claim 1, wherein only the difference in net ID between the master side circuit and the slave side circuit is output as a difference list based on the above. 3. When the net ID is set as an address of the net ID conversion tables (40) and (50), the used flag of the net ID is set in the master side net ID conversion table (40) which refers to each other's net ID. The circuit CAD system according to claim 1, wherein the circuit CAD system is provided to extract a free net ID. 4. When the net ID is the address of the net ID conversion tables (40), (50), a flag indicating that the connection relationship is not supported is provided in the slave side net ID conversion table (50). 2. The circuit CAD system according to claim 1, wherein the mismatched connection between the two circuits is extracted.