JPH11102379A - Naming method for signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To automate naming for the signals of the pins of mounted ASI and PWB(printed wiring board). SOLUTION: Mounted ASIC design data 2 include information on the component names (symbol name) of the ASIC and the basic signal names of all the input/output pins. Mounted PWB design data 3 include information on the substrate name (symbol name) of the PWB and the basic signal names of the connector pins. A signal name conversion rule file 4 contains a conversion rule for the basic signal names of the respective pins of mounted articles based upon the mount positions as keys. A circuit diagram editor 7 automatically generates the signal names of the pins of the mounted PWB and ASIC on the basis of those pieces of information to generate the circuit diagram 5 of the PWB and the design data of the PWB.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for assigning signal names, and more particularly, to a circuit diagram editor for automatically assigning signal names on a circuit diagram of a printed circuit board or a back panel.

[0002]

2. Description of the Related Art Conventionally, on a circuit diagram, a multi-pin component such as an ASIC or a PWB (Pr.
A unique signal name is assigned to each wiring on the wiring on the integrated wiring board.

[0003] The assignment of signal names is performed when a circuit diagram is designed.
In general, a designer performs key input for each signal on a circuit diagram editor.

[0004]

In the above-described conventional method of assigning signal names, all signal names must be manually input during circuit diagram design. In this case, there is a disadvantage that a signal name is easily erroneously assigned due to an input error or an assignment error, and it takes a lot of time to manually input all signal names.

[0005]

According to a first aspect of the present invention, there is provided a method for assigning a signal name in a circuit diagram, wherein a signal name of each pin of the mounted article is automatically determined according to a symbol name of the mounted article and its mounting position. It is characterized by generating.

A second invention provides a method for assigning signal names in a circuit diagram, wherein the mounting data is provided according to design data including a basic signal name of each pin of the mounted product, a symbol name of the mounted product, and a mounting position thereof. A signal name change rule file holding a change rule for changing the signal name of each pin of the product is prepared in advance, and when the symbol name of the mounted product and its mounting position are input, the design data and the signal name are prepared. It is characterized in that a signal name of each pin of the mounted product is automatically generated by reading a change rule file and applying the change rule to the basic signal name of each pin of the mounted product.

Next, a third invention is characterized in that the design data in the second invention is ASIC design data.

Next, a fourth invention is characterized in that the design data in the second invention is PWB design data.

According to a fifth aspect of the present invention, when a symbol name of a mounted product and its mounting position are input, design data including a basic signal name of each pin of the mounted product prepared in advance and a symbol name of the mounted product And reading a signal name change rule file holding a change rule for changing a signal name of each pin of the mounted product according to the mounting position, and reading the change rule for the basic signal name of each pin of the mounted product. Is a recording medium on which a circuit diagram editor for automatically generating signal names of each pin of the mounted article is recorded.

[Operation] A design rule of a mounted ASIC or a mounted PWB including information of a component name and a basic signal name of all pins, and a conversion rule for converting the basic signal name of a pin according to a mounting position of a mounted product. When a mounting position of a mounted product is designated, a basic signal name is converted according to the signal name changing rule to generate a signal name of each pin, and the signal name and rat nest Is provided on the circuit diagram.

[0011]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a system configuration diagram showing a preferred embodiment of a signal name assigning method according to the present invention.

[1] Description of Configuration Referring to FIG. 1, a preferred embodiment of the present invention stores a component name (symbol name) and permanent information of all pins existing in the component at the time of creating a circuit diagram. Component library (1), ASIC component name (symbol name) and mounting ASIC design data including information on basic signal names of all input / output pins (2), PWB board name (symbol name) and basic signal of connector pins Mounting PWB design data including name information (3) When mounting a plurality of ASICs or PWBs of a single type, a signal name conversion rule file (4) necessary to change the signal names of pins is required. Read (This file stores the conversion rules for the basic signal names of each pin of the mounted product using the mounting position as a key. If conversion of signal names is not required, there is no need to read this file. ), Automatically generates a signal name of the pin mounting PWB or ASIC based on these information, the circuit diagram of the PWB (5), PW
Schematic editor (7) for creating design data (6) for B
Is provided.

The component library (1) is used for general purposes in PWB design, and the mounting ASIC design data (2) and the mounting PWB design data (3) are always created at the time of design using a circuit diagram editor or the like. Data.
The signal name conversion rule file (4) is a file in which, when conversion of a pin signal name is required, a conversion rule manually created for a pin requiring conversion is stored. Therefore,
The present invention is more effective and more reliable as the conversion of signal names is smaller.

[2] Description of Operation Next, the operation of the embodiment of the present invention will be described in detail with reference to FIG.

First, in process 11, designation of a symbol name and a location (mounting position) given by an external input is accepted. Next, in process 12, a component library is searched based on the symbol name received in process 11, and a symbol is added to the circuit diagram. Next, in decision 13, the design data of the mounted ASIC or PWB is searched based on the symbol name, and it is determined whether or not the design data of the added symbol exists. If there is, the process proceeds to processing 14. If not, the process ends. In the processing 14, the signal name conversion rule file is searched based on the symbol name and the location information to check the signal name conversion rule of the pin of the designated symbol, and the design data of each pin is referred to by referring to the design data of the designated symbol. The basic signal name is converted according to the conversion rule and a new signal name is given. Next, in judgment 15, it is checked for each pin whether a pin having the same signal name already exists on the circuit diagram being designed. If a pin having the same signal name exists, the process proceeds to step 16; otherwise, the process proceeds to step 17. In process 16, a rat nest (a straight line that is temporarily displayed to indicate that connection is necessary) is displayed between pins having the same signal name as the pin to be processed on the circuit diagram. In the process 17, the signal names assigned to the pins are displayed on the circuit diagram. The processing after judgment 15 is performed for all pins of the target symbol, and the processing is terminated.

[3] Description of Embodiment Configuration Next, an embodiment of the present invention will be described in detail with reference to the drawings. Referring to FIG. 3, according to the embodiment of the present invention, when creating a circuit diagram, first, a component library (1), mounting ASIC design data (2), mounting PWB design data (3), and a signal name conversion rule file (4) are stored. Reading and storage unit (10)
To store the information read. Thereafter, when an instruction to add a symbol is given, a symbol figure is displayed on the circuit diagram on the display unit (8) by referring to the library information in the storage unit (10) in accordance with the part name, symbol name and location designation of the symbol. At the same time, it is checked whether the design data of the symbol or the signal name conversion rule exists, and if so, the signal name conversion unit (9) generates the signal name of each pin based on the information, and the display unit ( In 8), a signal name is displayed on the circuit diagram, and a circuit diagram editor (7) for finally creating a PWB circuit diagram (5) and PWB design data (6) is provided.

[4] Description of Operation of Embodiment Next, the operation of the embodiment of the present invention will be described in detail with reference to FIGS.

FIG. 4 is a specification example of a "signal name conversion rule file". Part name, symbol name, location is 1
A record is specified, and the pin conversion rules for that symbol are described below for the required number of records. FIG. 5 shows an example of the "signal name conversion rule file". The fifth record indicates that no signal name is assigned to the pin having the signal name “HH” in the lower-order design data. Fig. 6 shows the "mounted ASI
C design data ". The first field of each record is a record identifier, and the 00 record is followed by a component name and a symbol name. The 30 records are followed by pin names and signal names.

FIG. 7 shows the present embodiment applied to the symbol having the symbol name “XYZ” and the location “P01” using the “signal name conversion rule file” in FIG. 5 and the “mounted ASIC design data” in FIG. FIG. A01 to B08 indicate pin names. Pins A01 to A08 have “D *:
A signal name converted according to the conversion rule of “D * 01” is given. Since there is no conversion rule for the signal names “CQFA” and “IFIF” on the design data of the pins B01 and B08, “CQFA” and “IFIF” are given as they are. B02 to B05 include “E *: E * 0” in FIG.
3 and B06 are given signal names converted according to the conversion rule of “FFF: GGG”. Further, since a conversion rule of “HH:” is applied to B07, no signal name is given.

In the above-described embodiment, the mounted ASIC
The same applies to the case of the mounted PWB.

Finally, FIG. 8 is a system configuration diagram showing another embodiment of the present invention.

Referring to FIG. 8, another embodiment of the present invention includes a recording medium 1B on which a circuit diagram editor is recorded. This recording medium 1B may be a magnetic disk, a semiconductor memory, or another recording medium.

The circuit diagram editor is read from the recording medium 1B into the data processing device 1A and controls the operation of the data processing device 1A. The data processing device 1A executes the above-described processes 11 to 17 in FIG. 2 under the control of the circuit diagram editor.

[0025]

As described above, according to the present invention, the mounting A
Reads SIC and PWB design data and automatically generates signal names for on-board ASIC and PWB pins according to conversion rules, reducing errors in assigning on-board ASIC and PWB pin signal names and reducing design time. There is an effect that can be.

[Brief description of the drawings]

FIG. 1 is a system configuration diagram showing a preferred embodiment of a signal name assigning method according to the present invention.

FIG. 2 is a processing flowchart illustrating a signal name assigning method according to a preferred embodiment of the present invention.

FIG. 3 is a system configuration diagram showing an embodiment of a signal name assigning method according to the present invention.

FIG. 4 is a diagram showing a specification example of a “signal name conversion rule file” used in the signal name assigning method of the present invention.

FIG. 5 is a diagram illustrating an example of a “signal name conversion rule file”.

FIG. 6 shows an example of the “mounted AS” used in the signal name assignment method of the present invention
FIG. 9 is a diagram illustrating an example of “IC design data”.

FIG. 7 is a diagram showing an embodiment in which the signal name assigning method of the present invention is applied to one symbol.

FIG. 8 is a system configuration diagram showing another embodiment of the signal name assigning method of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 component library 2 mounted ASIC design data 3 mounted PWB design data 4 signal name conversion rule file 5 PWB circuit diagram 6 PWB design data 7 circuit diagram editor 8 display unit 9 signal name conversion unit 10 storage unit 1A data processing device 1B recording Medium

Claims (5)

[Claims] 1. A method for assigning a signal name in a circuit diagram, wherein a signal name of each pin of the mounted article is automatically generated according to a symbol name of the mounted article and its mounting position. . 2. A method for assigning a signal name in a circuit diagram, comprising: design data including a basic signal name of each pin of a mounted product, a symbol name of the mounted product, and a signal of each pin of the mounted product according to its mounting position. A signal name change rule file holding a change rule for changing the name is prepared in advance, and when the symbol name of the mounted product and its mounting position are input, the design data and the signal name change rule file are read, and the A signal name assigning method, wherein the signal name of each pin of the mounted product is automatically generated by applying the change rule to the basic signal name of each pin of the mounted product. 3. The method according to claim 2, wherein the design data is ASIC design data. 4. The method according to claim 2, wherein the design data is PWB design data. 5. When a symbol name of a mounted product and its mounting position are inputted, design data including a basic signal name of each pin of the mounted product prepared in advance, and a symbol name of the mounted product and its mounting position are displayed. By reading a signal name change rule file holding a change rule for changing the signal name of each pin of the mounted product accordingly, and applying the change rule to the basic signal name of each pin of the mounted product A recording medium in which a circuit diagram editor for automatically generating signal names of each pin of the mounted product is recorded.