JPH0567107B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing apparatus having an input/output buffer and capable of specifying a recording position.

[Background of the Invention] When using a photoelectric conversion element such as a CCD as an image reading means in an image processing device that can enlarge or reduce an original image, the pixel data of the original image read by the photoelectric conversion element is Generally, an enlarged/reduced image signal is obtained by increasing or thinning out appropriate image data according to the enlargement/reduction magnification.

FIG. 52 is a block diagram of essential parts showing an example of a processing system for executing enlargement/reduction used in such an image processing apparatus.

In the figure, 40 is a memory for image data, and image data D read by an image reading means is supplied to an input terminal 41 after being subjected to enlargement/reduction processing. The output image data obtained at the output terminal 42 is supplied to a recording device etc. to be enlarged and
The reduced image is reproduced.

When enlarging/reducing, the amount of image data stored in the memory 40 is limited depending on the recording width of the recording device, but in this case, the generation timing of the address generator 47 for the memory 40 is controlled according to the enlargement/reduction. be done.

For this reason, first and second counters 43 and 44 that can be preset are provided, and a clock of a predetermined frequency (fifth
3C), the first and second output pulses C1, C2 are generated (Fig. 53D,
E).

The flip-flop 45 is activated by the first output pulse C1.
is set and reset by the second output pulse C2, thereby forming the window pulse WP shown in FIG. This window pulse WP
is supplied to the gate circuit 46 as a gate pulse, and a clock corresponding to the width W1 of the window pulse WP is supplied to the address generator 47. However, this clock is a clock synchronized with the enlarged/reduced image data.

As a result, address data for the memory 40 is generated for the period W1, so of the image data (B in the same figure) regulated by the horizontal valid area signal H-VALID in FIG. 53A, the image data for the period W1 is stored in the memory. 40 (G in the same figure).

Therefore, if the preset values P1 and P2 are changed in accordance with the magnification/reduction ratio, the width W1 of the window pulse WP will change in accordance with this change, thereby reducing the amount of image data written to the memory 40. is limited.

In the case of reduction, the window pulse WP and the horizontal valid area signal H-VALID are processed with the same width.

On the other hand, in the case of enlargement, the number of image data increases, so take this into account in advance and reduce the number of data by narrowing the width of the window pulse WP relative to the width of the horizontal effective area signal H-VALID. That's what I do.

[Problems to be Solved by the Invention] By the way, the conventional image processing apparatus having the above-mentioned enlargement/reduction function causes the following problems.

That is, in the configuration shown in FIG. 52, although the amount of image data to be written into the memory 40 is limited according to the magnification/reduction ratio, the write address is always set to address (0) first, regardless of the magnification.
address) will be specified, in particular,
Image reading or image recording is the original (recording paper)
When applied to an image processing apparatus that performs processing based on the center of the image, depending on the magnification, the image to be recorded may end up outside the transfer area of the recording paper.

For example, as shown in FIG. 54, when W is the maximum reading width (equal to the horizontal effective area width) of the image reading means, the image data of the original 52 is read based on the center line l of the original placing table 51, In the case where an image is recorded using the center line l as a reference, when the image is enlarged to the same size, it is recorded as shown in FIG. 55B, but when it is reduced, it is recorded as shown in FIG. 55A.

This is because the first write address in the memory 40, that is, the 0 address, corresponds to the write start position of the output device (recording device such as a laser printer). Therefore, when the size of the recording paper P to be recorded is small, the image may fall outside the transfer area of the recording paper, and in that case, the reduced image cannot be correctly recorded on the recording paper.

Even when the size of the recording paper P is large, there is a drawback that the reduced image is recorded on the edge of the recording paper P.

Furthermore, during the enlargement process, the margins of the original document are also enlarged, resulting in enlargement as shown in FIG. 55C. Therefore, there is a possibility that the required range of images cannot be recorded on the predetermined recording paper P.

Further, some of such image processing apparatuses are configured so that an operator can specify a recording position from the outside. This means that the 56th
This image processing apparatus is capable of enlarging an area n of a document 52 shown in FIG. A and recording the enlarged image N, for example, at a designated position on a recording paper 53 shown in FIG.

In such an image processing device, the write address to the memory 40 is limited by the specified magnification, the read address is controlled according to the position of the designated recording area, and the horizontal effective area is controlled according to the width of the designated reading area. It is necessary to control the width of the signal H-VALID.

Therefore, in the conventional image processing apparatus, as described above, the circuit configuration and other controls added to specify the recording apparatus are extremely complicated.

Therefore, the present invention solves the above-mentioned conventional problems, and proposes an image processing device capable of specifying a recording position, which has an input/output buffer that simplifies the circuit configuration and control for specifying the recording position. It is something.

[Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention performs image processing such as enlarging and reducing the image using image data read by photoelectrically converting image information. In an image processing device capable of specifying a recording position, the input buffer and output buffer for image data, and the write start address or read start address of the input buffer and output buffer are controlled according to the specified magnification and the position of the specified area. It is characterized by having a means.

[Effect] If the specified magnification is m, the image data of I0 is
Increases to m・I0.

In the case of I1>m・I0 (FIG. 43A, C), the enlarged image data (m・I0) read from the input buffer 400 is directly transferred to the output buffer 4.
50 and recorded this, the enlarged image data m·(x2−x1) in the original image area n will be recorded before reaching the recording start point x3 in the main scanning direction.

In addition, in the case of I1>m・I0 (Fig. 43B, D), even when the recording start point x3 is reached, the enlarged image data in the image area n is not recorded, and the data outside the area is recorded. You will end up being rejected.

To prevent this from happening, set the input buffer 4.
00 and the read start address or write start address of the output buffer 450 are controlled according to the specified magnification.

Therefore, the readout start address of the input buffer 400 is selected so that processing can be performed from the point (x1, y2) of the image area n.

Similarly, the write start address to the output buffer 450 is selected so that the read image area n is recorded at the designated recording position (x3, y3). That is, for input buffer 400, write start address = 0 read start address = 16 x x 1 (I0), for output buffer 450, write start address = 16 x x 3 (I1) read start address = 0. By setting write and read start addresses for the input buffer 450 and output buffer 450, it is possible to move to a specified position (coordinates) in the main scanning direction.

The movement of the image recording position in the sub-scanning direction can be realized by advancing the reading start of the image reading device or the writing start of the output device 65.

Also, instead of writing or reading image data from the first address of the line memory, if you automatically change the writing or reading start address according to the enlargement/reduction ratio, recording paper size, etc. When reducing an image, the image is not recorded from the edge of the recording paper. Particularly, in the type of printer that records images with the center as a reference, reduced images can be recorded correctly regardless of the size of the recording paper.

[Example] Hereinafter, an example of an image processing apparatus according to the present invention having an editing function capable of specifying a recording position will be described. This will be explained in detail with reference to the following figures.

However, the embodiment shown below is a case where the present invention is applied to a color image processing apparatus using an electrophotographic color copying machine as an output device.

Therefore, first, a schematic configuration of such a color image processing apparatus to which the present invention is applied will be explained with reference to FIG.

Image information such as a document is converted into an image signal by the image reading device 50, and then subjected to A/D conversion processing, shading correction processing, color separation processing, and other image processing to obtain information corresponding to each color signal. It is converted into image data of a predetermined number of bits, for example, image data of 16 gradations (0 to F).

Each image data is subjected to image processing such as enlargement/reduction in an enlargement/reduction circuit 2 based on a linear interpolation method. In this case, the interpolation data used as image data after enlargement/reduction processing is stored in an interpolation table (interpolation ROM), and the signal for selecting this interpolation data is the image data before enlargement/reduction processing. and interpolation selection data stored in the data ROM are used. Necessary interpolation selection data is selected based on a command from the system control circuit 80 in accordance with the specified magnification.

The image data after image processing is supplied to the output device 65, and the image is recorded at an externally set magnification. As the output device 65, an electrophotographic color copying machine can be used.

The image reading device 50 is equipped with a drive motor, an exposure lamp, etc. for driving an image reading means such as a CCD, and these are controlled at predetermined timing by command signals from the sequence control circuit 70. . The sequence control circuit 70 includes a position sensor (not particularly shown).
Data from is input.

In the operation/display section 75, various input data such as magnification designation, recording position designation, and recording color designation are input, and the contents thereof are displayed. As the display means, elements such as LEDs are used.

The various controls described above, the control of the entire image processing apparatus, the management of the state, etc. are controlled by the system control circuit 80. Therefore,
Microcomputer control is suitable for this system control.

The figure shows an example of microcomputer control, and necessary image processing data and control data are exchanged between the control circuit 80 and the various circuit systems described above via a system bus 81.

An image reading start signal, a start signal for shading correction, a recording color designation signal, and the like are supplied to the image reading device 50 via the system bus 81.

For the enlargement/reduction circuit 2, the operation/display section 7
After the magnification data specified in step 5 and threshold selection data for selecting a threshold for binarizing image data according to the type and density of the image to be recorded are taken into the control circuit 80, the system bus 81 is loaded. It is supplied via

The output device 65 is supplied with a start signal for image recording, a recording paper size selection signal, and the like.

Next, these components will be explained in detail.

For convenience of explanation, an example of the configuration of a simplified color copying machine applicable to the present invention will first be described with reference to FIG. 13.

The illustrated color copying machine attempts to record color images by separating color information into approximately three types of color information. In this example, black BK, red R, and blue B are illustrated as three types of color information to be separated.

In FIG. 13, 200 is an example of a main part of a color copying machine, and 201 is a drum-shaped image forming member (photosensitive drum), the surface of which is a photoconductive photosensitive material such as OPC (organic semiconductor). A body surface layer is formed so that an electrostatic image (electrostatic latent image) corresponding to an optical image can be formed.

The following members are sequentially arranged on the circumferential surface of the image forming body 201 in the direction of rotation thereof.

The surface of the image forming body 201 is uniformly charged by a charger 202, and the charged image forming body 201
Image exposure (the optical image is shown at 204) based on each color separation image is performed on the surface of the image.

After image exposure, the image is developed by a predetermined developing device.
The developing devices are arranged in a number corresponding to the color separated images.
In this example, a developing device 205 filled with a red toner developer, a developing device 206 filled with a blue toner developer, and a developing device 207 filled with a black toner developer are used to create an image. They are sequentially arranged to face the surface of the image forming body 201 in this order in the direction of rotation of the image forming body 201 .

The developing units 205 to 207 are sequentially selected in synchronization with the rotation of the image forming body 201. For example, by selecting the developing unit 207, toner adheres to an electrostatic image based on a black color separation image, thereby producing a black color. color separation images are developed.

A pre-transfer charger 209 and a pre-transfer exposure lamp 210 are provided on the developing device 207 side, and these make it easy to transfer the color image onto the recording medium P. However, these pre-transfer charger 209 and pre-transfer exposure lamp 210 are provided as necessary.

The color image or black and white image developed on the image forming body 201 is transferred to the recording body P by the transfer device 211.
transferred on top. The transferred recording medium P is subjected to a fixing process by a fixing device 212 at a subsequent stage, and then discharged.

Note that the static eliminator 213 includes one or a combination of a static elimination lamp and a corona discharger for static elimination.

The cleaning device 214 includes a cleaning blade and a fur brush, and is used to remove residual toner adhering to the drum surface after the color image of the image forming body 201 has been transferred.

It is well known that this removal operation is performed so that the surface of the image forming member 201 is separated by the time the developed surface is reached.

As the charger 202, a scorotron corona discharger or the like can be used. This is because stable charging can be applied to the image forming body 201 with less influence from previous charging.

As the image exposure 204, image exposure obtained by a laser beam scanner can be used. This is because a laser beam scanner can record clear color images.

For at least the second and subsequent development steps that are repeated to superimpose color toner images, care must be taken to ensure that the toner that has adhered to the image forming body 201 due to the previous development is not displaced during the subsequent development. It won't happen. In this sense, such development is preferably performed by non-contact jumping development.

FIG. 13 shows a type of developing device that performs development by such non-contact jumping.

As the developer, it is preferable to use a so-called two-component developer. This is because the two-component developer has clear colors and can easily control the charge of the toner.

FIG. 2 shows an example of the image reading device 50. As shown in FIG.

In the figure, color image information (optical image) of a document 52 is separated into two color separated images by a dichroic mirror 55. In this example, the image is separated into a color-separated image of red R and a color-separated image of cyan Cy.
Therefore, the cutoff of the dichroic mirror 55 is about 600 nm. As a result, the red component becomes transmitted light, and the cyan component becomes reflected light.

The color separation images of red R and cyan Cy are respectively supplied to image reading means 56 and 57 such as CCD.
Image signals of only the red component R and the cyan component Cy are output from each.

FIG. 3 shows the relationship between the image signals R, Cy and various timing signals, and shows the horizontal effective area signal H-
VALID (C in the same figure) corresponds to the maximum document reading width W (see Figure 52) of CCD56, 57, and F in the same figure
The image signals R and Cy shown in and G are synchronous clocks.
It is read out in synchronization with CLK1 (E in the same figure).

These image signals R and Cy are sent to the normalization amplifier 5.
The signal is supplied to A/D converters 60 and 61 via A/D converters 8 and 59, and is converted into a digital signal having a predetermined number of bits.

This digital image signal is subjected to shading correction. Reference numerals 63 and 64 indicate shading correction circuits having the same configuration. A specific example will be described later.

The digital color image signal subjected to the shading correction is supplied to the next stage color separation circuit 150, where it is separated into a plurality of color signals necessary for color image recording.

In the above example, the color recording device records a color image in three colors, red R, blue B, and black BK, so the color separation circuit 150 separates color signals R, B, and BK of these three colors. will be separated.
A specific example of color separation will be described later.

One of the color signals R, B, and BK is selected by the color selection circuit 160. This is because, as mentioned above, an image forming process is adopted in which a color image of one color is developed per one rotation of the image forming body 201. Developing device 205-20
7 is selected, and the color signal corresponding to this is selected in the color selection circuit 160.

The terminal 170 receives selection signals G1~ for color signals.
G3 is supplied. These selection signals G1 to G3 are
It is used to select the color signal to be output for three-color recording, that is, normal color recording mode (multi-color mode), and for single-color recording, that is, color-specified recording mode (mono-color mode). It is supplied from the system control circuit 80.

Note that the color separation process of separating color signals from a color original into three color signals is executed every rotation of the image forming body 201, but it may be executed only once during the preliminary rotation of the image forming body 201. .

Now, in a device that reads an image by irradiating a lamp onto a document and condensing the reflected light with a lens, a non-uniform optical image called shading is obtained due to optical problems with the lamp, lens, etc.

In Fig. 4, image data in the main scanning direction is
1, V2, . . . Vn, the level decreases at both ends in the main scanning direction. Therefore, in order to correct this, the shading correction circuits 63 and 64 perform the following processing.

In FIG. 4, VR is the maximum value of the image level, and V1 is the image level of the 1st bit when the white color of a reference white plate (not shown) of uniform density is read. In fact, assuming that the image level when the image is read is d1, the gradation level d1' of the corrected image is as follows.

d1'=d1×VR/V1 Correction is performed for each pixel image data so that this correction formula holds true.

FIG. 5 shows an example of the shading correction circuit 63.

First memory 66a composed of RAM etc.
is a memory for reading one line of normalization signals (shading correction data) obtained when a white plate is irradiated.

The second memory 66b stores the first memory when reading an image.
This is for correcting the image data based on the shading correction data stored in the memory 66a, and a ROM or the like is used.

In the shading correction, first, one line of image data obtained by scanning a white plate is stored in the first memory 66a. When reading an image of a document, the image data is supplied to address terminals A0 to A5 of the second memory 66b, and the shading correction data read from the first memory 66a is supplied to address terminals A6 to A11.
Therefore, the second memory 66b outputs image data that has been subjected to shading correction according to the above-mentioned arithmetic expression.

The above-mentioned color separation (color separation into three color signals from two colors) is performed based on the following idea.

Figure 6 schematically shows the spectral reflection characteristics of a color chart of color components, in which Figure A shows the spectral reflection characteristics of achromatic colors, Figure B shows the spectral reflection characteristics of blue, and Figure 6 shows the spectral reflection characteristics of blue. C indicates red spectral reflection characteristics.

The horizontal axis shows wavelength (nm), and the vertical axis shows relative sensitivity (%). Therefore, dichroic mirror 5
If the spectral characteristics of No. 5 are 600 nm, the red component R is transmitted and the cyan component Cy is reflected.

When the level of the red signal R normalized with white as the reference is VR, and the level of the cyan signal Cy is VC,
A coordinate system is created from these signals VR and VC, and red, blue, and black colors are separated based on the created color separation map. When determining the coordinate axes, the following points need to be considered.

In order to be able to express halftones, the concept of reflectance (reflection density) of the original 52, which corresponds to the luminance signal of the television signal, is adopted.

Color differences such as red and cyan (including hue and saturation)
Introduce the concept of

Therefore, the following may be used as the luminance signal information (for example, a 5-bit digital signal) and the color difference signal information (also a 5-bit digital signal).

Luminance signal information = VR + VC (1) However, 0≦VR≦1.0 (2) 0≦VC≦1.0 (3) 0≦VR+VC≦2.0 (4) The sum of VR and VC (VR + VC) is the black level (=0)
to white level (=2.0), and all colors exist in the range from 0 to 2.0.

Color difference signal information = VR/(VR+VC) or VC/(VR+VC) (5) In case of achromatic color, overall level (VR+VC)
The ratio of red level VR and cyan level VC included in is constant. Therefore, VR/(VR+VC)=VC/(VR+VC)=0.5 (6).

On the other hand, the proportion of chromatic colors is as follows for red colors: 0.5＜VR／(VR＋VC)≦1.0 (7) 0≦VC／(VR＋VC)＜0.5 (8) In cyan color, 0≦VR/(VR+VC)＜0.5 (9) 0.5＜VC／(VR＋VC)≦1.0 (10) It can be expressed as:

Therefore, by using a coordinate system with two axes: (VR + VC) and VR/(VR + VC) or (VR + VC) and VC/(VR + VC), chromatic colors (red and cyan) can be created just by level comparison processing. , achromatic colors can be clearly separated.

In Figure 7, the vertical axis shows the luminance signal component (VR+
VC), and the horizontal axis shows the color difference signal component VC/(VR+
The coordinate system when taking VC) is shown.

If VC/(VR+VC) is used as the color difference signal component, the area smaller than 0.5 will be red-ish R, and the area larger than 0.5 will be cyan-ish Cy. Color difference signal information =
Achromatic colors exist in the vicinity of 0.5 and in areas with little luminance signal information.

FIG. 8 shows a specific example of a color separation map in which colors are classified according to such a color separation method. A ROM table is used for the color separation map, and the example shown is
An example is shown in which the image is divided into 32x32 blocks. Therefore, as the number of address bits for this ROM table, 5 bits are used for the row address and 5 bits are used for the column address.

This ROM table stores quantized density corresponding values obtained from the reflection density of the original 52.

FIG. 9 is a system diagram of essential parts showing an example of a color separation circuit 150 for realizing such color separation.

In the figure, a red signal R and a cyan signal Cy that have been subjected to signal processing such as gradation conversion and γ correction are supplied to terminals 150a and 150b. These signals are used to obtain luminance signal data (VR+
It is used as an address signal for the memory 152 in which the calculation result of color difference signal data VC/(VR+VC) is stored, and as an address signal for the memory 153 in which the calculation result of the color difference signal data VC/(VR+VC) is stored.

Each output of these memories 152, 153 is used as an address signal for separate memories (ROM configuration) 154-156. The memories 154 to 156 use a data table in which data of the color separation map shown in FIG. 8 is stored for each color.

Memory 154 is for black signal BK, and memory 1
55 is for red signal R, and memory 156 is for green signal B.

As is clear from the color separation map shown in FIG. 8, three color signals of red, blue, and black are extracted from the color information signal of the color original by detecting the levels of the red signal R and the cyan signal Cy. R, B,
It can be separated into BK and output.

Each of the memories 154 to 156 outputs density data (4-bit configuration) regarding each color signal and color code data of 2-bit configuration at the same time.

The density data and color code data are combined in subsequent combiners 157 and 158, respectively. The combined density data and color code data are supplied to a ghost canceller (not shown) to perform ghost signal removal processing.

Each data after ghost removal is supplied to a color selection circuit 160 shown in FIG.

The color code data supplied to the terminal 161 is supplied to a decoder 164 to decode the color code, and the decoded output is supplied to OR circuits 166-169. Similarly, terminal 16
The data contents of the color selection signals G1 to G3 supplied to the circuit 3 are decoded by a decoder 165, and the decoded outputs are supplied to the plurality of OR circuits 166 to 169 described above to select colors ranging from red to black. Any color signal can be selected from among the signals (all colors) including all of the colors.

A selection signal for the color signal output from each OR circuit 166 to 169 is supplied to the density signal separation circuit 162 as a density selection signal. This density signal separation circuit 162 is supplied with the above-mentioned density data, and is selected in response to the above-mentioned select signal.

The selected density data is supplied to the enlargement/reduction circuit 2.

Color selection signals G1 to G3 correspond to each separated color signal, and in normal color recording mode,
Three-phase gate signals G1 to G3 synchronized with the rotation of the image forming body 201 are formed (FIG. 11 G to I).
At the same time, the developing units 205 to 207 are also
Developing biases shown through E are supplied to each of the developing devices 205 to 207 in synchronization with the rotation of the image forming body 201.

As a result, the exposure process for each color ~
(F in the same figure), exposure and development processing steps are sequentially executed.

On the other hand, in the color designated recording mode, a single designated image forming process is performed.

Therefore, as shown in FIG. 12, three selection signals G1 to G3 are obtained in phase regardless of the designated color signal (G to I in the same figure). The example shown in FIG. 12 is a case where red is specified.

At the same time, a developing bias is supplied only to the corresponding developing device 205 (D in the figure), and this becomes in operation. Therefore, since only the developing device 205 containing red toner (developer) is driven, an image is recorded in red regardless of the color information of the color document.

Even when specifying another color (black or blue), the image forming process is the same, so a detailed explanation thereof will be omitted.

FIG. 14 is a block diagram showing an example of the enlarging/reducing circuit 2. In FIG.

In this example, the image can be enlarged or reduced in 1.0% increments from 0.5 times to 2.0 times.

Here, in the present invention, in principle, the enlargement process is an interpolation process in which image data is increased, and the reduction process is thinned out in the image data. The enlargement/reduction in the main scanning direction shown in FIG.
The movement speed of the photoelectric conversion elements 57, 57 or image information is changed while keeping the exposure time of the photoelectric conversion elements 56, 57 provided at constant.

If the moving speed in the sub-scanning direction is slowed down, the original image will be enlarged, and if it is fast moved, the original image will be reduced. The details will be described later.

In FIG. 14, timing signal generation circuit 1
0 is used to obtain a timing signal that controls the processing timing of the entire enlargement/reduction circuit 2, and this includes a synchronization clock CLK1, a horizontal effective area signal H-
VALID, a vertical valid area signal V-VALID, and a horizontal synchronization signal H-SYNC.

The timing signal generation circuit 10 first outputs a synchronization clock CLK2 which is output only during the period of the horizontal valid area signal H-VALID. This is the same frequency as the synchronous clock CLK1.

Further, memory control signals INSEL and OUTSEL are outputted to the memories provided in the input buffer 400 and the output buffer 450, respectively.

Sent from the color selection circuit 160 for each color signal
Image data D having 16 gray levels is supplied to an input buffer 400.

Input buffer 400 is provided based on the following reasons.

Firstly, during enlargement processing, the number of image data used increases compared to before processing, so it is possible to effectively increase the processing speed after data increases without increasing the frequency of the basic clock. This is for the purpose of

Second, this is to ensure that an enlarged image during enlargement processing is recorded with the center as a reference.

Thirdly, it is possible to correctly record an enlarged/reduced image at a designated recording position.

Therefore, in order to satisfy the first condition during the enlargement process, the frequency of the read clock RDCLK supplied to the input buffer 400 is lowered than the normal frequency. Then, in order to satisfy the second and third conditions, the read start address is set according to the magnification and the designated recording position. Details will be explained in detail.

The output image data D corresponding to the designated magnification is supplied to two cascade-connected latch circuits 11 and 12, and the output image data D having a 4-bit configuration, that is, the output image data D having a halftone level, is Image data D1 and D0 of two adjacent pixels are latched at the timing of the latch clock DLCK.
The latch clock DLCK has the same frequency as the synchronous clock CLK1.

The image data D0 and D1 latched by the latch circuits 11 and 12 are used as address data for a memory 13 for interpolation data (using ROM, hereinafter referred to as interpolation ROM).

The interpolation ROM 13 is an interpolation data table in which image data having a new halftone level referenced from two adjacent image data (hereinafter, this image data will be referred to as interpolation data S) is stored.

As address data for the interpolation ROM 13, interpolation selection data SD is used in addition to the pair of latch data D0 and D1 described above.

300 is interpolation data selection means that stores interpolation selection data SD and the like. As will be described in detail later, the interpolation selection data SD is used as address data to determine which data is to be used as interpolation data from among the data table group selected by the pair of latch data D0 and D1. .

The interpolation selection data SD is enlarged and
Determined by the set magnification for reduction.

FIG. 15 shows an example of interpolation data S selected by latch data D0, D1 and interpolation selection data SD. In the example, D0, D1
The interpolated data is obtained by linearly interpolating the data.

In Fig. 15, S is interpolated data (4 bits) that is output at 16 gradation levels, and since the image data D0 and D1 used as latch data each have 16 gradation levels, the interpolated data S is , 16×16=256 data blocks are included.

The figure shows the theoretical values (decimal point 5
digit) and the value of the interpolation data S actually stored in the case of positive slope and negative slope, respectively.

Actually, interpolated data S is stored in the form shown in FIG. However, this data is
This is an example where 0=4 and D1=0 to F.

In FIG. 16, ADRS is the base address, and interpolation selection data SD (data from 0 to F arranged horizontally) when D1 takes the level from 0 to F when D0=4. , and the interpolated data S to be output. The actual address for the interpolation ROM 13 is obtained by adding the address data ADRS and the value of the interpolation selection data SD on the horizontal axis.

Now, the interpolated data S outputted from the interpolation ROM 13 is latched by the latch circuit 14, and then supplied to the binarization means 69, where a binarization process corresponding to the image data is performed.

The binarized binary image data of “1” and “0” is supplied to the output buffer 450.

The output buffer 450 is provided to process invalid data caused by a decrease in image data during image reduction, and to allow the image to be recorded correctly in a designated area. Furthermore, it is provided so that the reduced image can be recorded with the center of the recording paper P as a reference when reducing the image.

The final binary data obtained from the output buffer 450 is supplied to the output device 65, and an image is recorded based on this binary data.

An example of the binarization means 69 provided between the latch circuit 14 and the output buffer 450 will be explained with reference to FIG. 14 again.

In the figure, the main scanning counter 20 is for counting the write clock LCK2 of the output buffer 450, and the sub-scanning counter 21 is for counting the horizontal synchronizing signal H-SYNC. Threshold value data of the dither ROM 22 is addressed by the outputs of these counters 20 and 21.

The designated predetermined threshold value data is transmitted to the binarization circuit 23.
The interpolated data S is binarized with reference to this threshold data.

Therefore, a digital comparison circuit is used as the binarization circuit 23.

When the original to be read is a line drawing, a certain threshold data corresponding to the density of the original is used as the threshold value data. An example is shown in FIG. The threshold data in the figure is expressed in hexadecimal.

If the original 52 is a photographic image, it is preferable to perform binarization using the dither method, so in this example, dither matrix is used as the threshold data.

In this example, three types of dither matrices (for example, a 4×4 dither matrix) are prepared depending on the density of the original 52, and these are selected as appropriate.

When the dither matrix shown in FIG. 18A is selected when the density of the original 52 is low, the matrix shown in FIG. 18B is selected when the original density is normal, and the matrix shown in FIG. become.

The threshold data used for line drawings or the dither matrix used for photographic drawings is original 5.
Although the operator may manually select it according to the concentration of No. 2, it is more convenient to automate the selection. In the case of automation, the overall density of the document 52 is detected, and an optimal dither matrix or the like is selected based on the detected density based on a command from the control circuit 80.

Next, specific examples of each part of the above-mentioned enlargement/reduction circuit 2 will be explained below.

FIG. 19 shows an example of the input buffer 400.

The input buffer 400 includes a pair of line memories 4.
01 and 402 are provided, and one line of image data D or clear data is selectively supplied to each of them.

Reference numeral 413 is a switch (sixth switch) for this purpose, and this is the vertical effective area signal V-
It is controlled by VALID or a clear signal PE (see FIG. 21) associated with this vertical valid area signal. As a result, all image data in the line memories 401 and 402 is cleared using the period of the non-effective area.

Clear data is data "0" corresponding to white information.

The reason for providing the pair of line memories 401 and 402 is to alternately supply one line of image data so that writing and reading of image data can be processed in real time.

Line memories 401 and 402 have a capacity of 4096×4 bits. This capacity is based on a resolution of 16 dots/mm and a maximum document size of B4 (width: 256 mm).

When writing data to the line memory, the write clock CLK2 is used, and when reading data, the read clock RDCLK is used, so these clocks are connected to the respective address counters via the first and second switches 403 and 404 for clock selection. 405 and 406.

The read clock RDCLK is set to a frequency different from that in normal times when the enlargement magnification is specified. The frequency to be set differs depending on the specified magnification.

The first and second switches 403 and 404 are complementary controlled so that when one line memory is in the write mode, the other line memory is in the read mode. The control signal INSEL generated by the timing signal generation circuit 10 is used as a switch control signal for this purpose.

In this case, one switch 403 has terminal 4
The control signal INSEL obtained at 08 is inverted in phase by an inverter 409 and then supplied. Control signal INSEL is 2 horizontal synchronization 1
This is a rectangular wave signal with a period (see FIG. 34).

The output from the line memories 401 and 402 is the third
After one of them is selected by the switch 407, it is supplied to the latch circuit 11. The switching signal is the control signal INSEL mentioned above.
is used.

Address counters 405 and 406 are supplied with addressing data for setting their initial addresses. Therefore, as shown in the figure, the write start address data and the read start address data are transferred to the fourth and fifth switches 411 and 412.
through the respective address counters 405, 406
supplied to

In this case, the switch control signal INSEL
Control is performed such that write start address data and read start address data are alternately supplied line by line.

The write start address is always designated as 0 address, and the read start address is automatically changed according to the magnification.

The read start address is the data described later.
In some cases, address data stored in the ROM 311 is used, and in other cases, address data calculated by the system control circuit 80 is used.

The address data of the data ROM 311 is used in the normal recording mode. On the other hand, when the address data of the system control circuit 80 is used, it is in an editing mode such as recording position designation.

In normal recording mode, the amount of address data to be used is known, so it is possible to use a data table, but in editing mode, it is difficult to select the editing mode. This is because it is impossible to store enough address data in ROM to satisfy all edits.

In the case of the normal recording mode, the reading start address is address data such that reading and recording are based on a central reference.

The read start address is determined by a pair of latch circuits 41
After the latch timing is adjusted by the switches 4 and 415, it is output to the fourth and fifth switches 411 and 412.

Of the read start address, the lower 8 bits of data are supplied to the latch circuit 414 and latched based on the address set control signal WT(L) (see FIG. 26).

The upper 8 bits of the read start address are supplied to the other latch circuit 415 and latched by the address set control signal WT(U), and the lower 4 bits of the read start address are the fourth and fifth bits. switch 411, 41
2.

The address set control signal can also be used differently depending on the recording mode. In the normal recording mode, an address set control signal generated by a control circuit 313 to be described later is used, and in the editing mode, an address set control signal generated by the system control circuit 80 is used.

FIG. 20 is an example of the output buffer 450.

Its configuration is almost the same as the input buffer 400, but since the image data after binarization is stored,
The line memories 451 and 452 are 4096×1 bit.

A switch (sixth switch) 463 is connected to the data supply line of the pair of line memories 451 and 452.
is provided, clear data and enlargement/reduction circuit 2
Image data supplied from is selectively supplied.

The clear data is used to clear the data contents of the pair of line memories 451 and 452 before image data is supplied.

This is because if the line memories 451 and 452 are not cleared when the power is turned on or when the magnification is changed, data different from the original image data (invalid image data) will be stored in these line memories 451 and 452.
This is because there is a risk that it may remain in 2.

Clear data is “0” or “1”
data is used. In this example, since binary data is used as image data, clear data "0" corresponding to white information is used.

A switching circuit 464 is further provided on the input side of the first switch 453 for switching between the write clock LCK2 and the synchronous clock CLK2.

This is because, especially during reduction processing, the write clock LCK2 will be less than 4096 bits for one line, as described later, so when clearing the image data,
By selecting synchronous clock CLK2,
This is to clear all data in the line memories 451 and 452. synchronous clock
CLK2 is the same as the transfer signal supplied to the photoelectric conversion elements 56 and 57.

Both switches 463 and 464 are simultaneously controlled as shown by a clear signal PE.

Clearing timing for the line memories 451 and 452 is performed during a period outside the non-effective area for image reading. In this example, vertical ineffective areas are utilized. Therefore, as shown in FIGS. 21B and 21C, the signal shown in FIG. 21D, in which the vertical valid area signal V-VALID is latched by the horizontal synchronizing signal H-VALID, is used as the clear signal PE.

Only while the clear signal PE is "1", it is switched to the clear data side and the synchronous clock CLK2 side.

Vertical effective area signal V- instead of clear signal PE
VALID may also be used.

Also, in Fig. 20, 453, 454, 4
57 is the first to third switches, 455 and 456 are address counters, and 459 is an inverter.

The control signal for switch selection is a signal generated by the timing signal generation circuit 10.
OUTSEL (see Figure 34) is used.

The frequency of the clock LCK2 is changed only when the reduction magnification is specified. Clock PCLK is the synchronization clock for output device 65.

Address counters 455 and 456 are supplied with address designation data for setting their initial addresses. Therefore, as shown in the figure, write start address data and read start address data are supplied to counters 455 and 456 via fourth and fifth switches 461 and 462, respectively.

In this case, the switch control signal
The write start address data and the read start address data are controlled to be alternately supplied line by line by OUTSEL.

The read start address is always specified as 0 address, and the write start address is set so that the reduced image is always recorded with the center as the reference, and so that it can be recorded correctly at the specified recording position.
Automatically changes depending on the magnification.

Also in the output buffer 450, the data ROM 31 is
It is selected whether to use the write start address of 1 or the write start address on the system control circuit 80 side.

In FIG. 20, 466 and 467 are latch circuits for latching the upper and lower data of the write start address, and these include address set control signals RD(L) and 467 as shown in FIG.
RD(U) is supplied, and the timing of supply to switches 461 and 462 is controlled.

The address set control signal is also selectively used in the recording mode and the editing mode, as in the case of the write start address.

Note that when clearing image data, the write address is set to "0". As a result, the image data in the line memories 451 and 452 are always cleared regardless of the difference in processing magnification.

Here, input buffer 400 and output buffer 4
50 will be explained with reference to FIGS. 22 to 24.

Figure 22 shows the processing operation when the magnification is the same.
Input buffer 4 for synchronized clock CLK1
The frequency of the read clock RDCLK supplied to 00 is the same as the frequency of the synchronous clock CLK1 (FIG. 3B). As a result, the input buffer 40
Image data D shown in FIG.

As a result, interpolated data S as shown in figure D is obtained. This interpolated data S is finally supplied to the output buffer 450 and temporarily stored.

In this case, the frequency of the write clock LCK2 supplied to the output buffer 450 is the same as that of the synchronous clock.
It is the same frequency as CLK1.

On the other hand, FIG. 23 shows the processing operation when the magnification is set to 2 times.

When a magnification of 1 or more is set, the frequency of only the read clock RDCLK to the input buffer 400 is changed in accordance with the set magnification.

When the magnification is set to 2x, the frequency of the read clock RDCLK supplied to the input buffer 400 is 1/1/1 with respect to the synchronous clock CLK1 in Figure A.
2 (Figure B). As a result, the image data D shown in FIG. As a result, as shown in figure D, one cycle per cycle of the synchronous clock CLK1.
interpolated data S are obtained. This interpolation data S
is supplied to output buffer 450 and temporarily stored.

In this case, the frequency of the write clock CLK2 supplied to the output buffer 450 is equal to that of the synchronous clock.
It is the same frequency as CLK1 (A in the same figure).

In this way, even if a magnification of 1x or more is selected, the enlargement process is performed by lowering the frequency of the read clock RDCLK.
Clock RDCLK supplied to input buffer 400
Otherwise, processing operations are executed using the basic clock.

Therefore, as the enlargement/reduction circuit 2, it is not necessary to use a circuit element having a high operating speed.

Of course, since the clock frequency of even the input buffer 400 is lower than the clock frequency at the same time, it is not necessary to use high-speed operating circuit elements.

When reducing the image, for example, when reducing the image by 0.5 times, as shown in FIG.
The read clock RDCLK is a synchronous clock.
Output buffer 4 instead of being the same as CLK1
The frequency of the write clock CLK2 supplied to 50 is reduced by half. As a result, the writing timing of the interpolated data S becomes once every two cycles, so that excess image data is thinned out and stored in the output buffer 450.

Note that details of the enlargement/reduction processing operation will be described later.

Now, the interpolation data selection means 3 shown in FIG.
00 is composed of a data selection signal write circuit 310 and a data selection memory 320.

The data selection signal writing circuit 310 includes interpolation selection data SD determined by the magnification and a processing timing signal for controlling such that the interpolation selection data SD is output at a timing corresponding to the magnification.
A write start address and a read disclosure address used in the TD and normal recording mode are stored for each block.

Since the interpolation selection data SD has a large capacity,
The write circuit 310 uses a large capacity ROM. In this case, a dedicated ROM may be used, but a ROM for a control program provided in the system control circuit 80 may also be used.

The data selection memory 320 includes interpolation selection data SD stored in the interpolation selection data writing circuit 310;
Of the processing timing signal TD, it is used to write data SD and TD according to the magnification designation.
Therefore, the interpolation selection data written in this data selection memory 320 is used as the interpolation selection data SD during actual image processing.

For this reason, the data selection memory 320
For example, static RAM, which can be written and read at high speed, is used.

The magnification designation data and magnification set pulse DS are each supplied to the write circuit 310.

On the other hand, when writing the interpolation selection data SD and processing timing signal TD to the data selection memory 320,
The clock SETCLK on the write circuit 310 side is used. Therefore, as shown in FIG. 14, a clock selection circuit 35 is provided on the data selection memory 320 side.
0 is provided to select synchronous clock CLK2 and write clock SETCLK from write circuit 310.

The selected clock is counted by a counter 360, and its output is supplied as address data to 12-bit address terminals A0 to A11 in the data selection memory 320.

Here, the counter 360 is configured to generate a carry pulse when counting 4096 clocks (therefore, data for 4096 pixels).

The carry pulse is used as a transfer end signal (write end signal) CS (FIG. 26B).

The write start address, read start address, and address set control signal PC for setting these addresses calculated by the system control circuit 80 are transferred to the input buffer 400 and the output buffer 45 through the buffer 325.
0 respectively.

Buffer 318 is supplied with a phase-inverted mode control signal PC. This allows buffer output to be obtained only in edit mode.

FIG. 25 shows an example of the write circuit 310.

In the figure, 311 is a data ROM,
This stores interpolation selection data SD, processing timing signal TD (FIGS. 36 and 38), write start address, and read start address, respectively.

Here, the interpolation selection data SD etc. stored in the writing circuit 310 prior to image reading are
After the magnification is specified externally, the data set pulse (magnification set pulse) DS (Figure 26A)
Based on this, the data in the data ROM 311 is transferred to the data selection memory 320.

The data set pulse DS is supplied to the control circuit 313 shown in FIG.
Control signals for write enable shown in
ES is generated.

The control signal ES is supplied to the counter 314, and the counting state of the clock SETCLK from the oscillation circuit 315 supplied thereto is controlled (FIGS. 26D and E). Control signal ES is “0”
The period is the address A0 to A6 by the counter 314.
and interpolation selection data SD corresponding to addresses A7 to A13 according to the specified magnification and processing timing signal
TD is repeated in block units (dotted chain line area in Figures 36 and 38) and corresponds to one line.
4096 pieces of data are written to data selection memory 320.

Similarly, each data of the write start address and read start address in the normal recording mode is set to the corresponding latch circuits 414, 415, 46.
6,467 and are provided to an input buffer 400 and an output buffer 450, respectively.

Here, as shown in Figure 26 F and H, the magnification is
When the magnification is 160%, 160 clocks (data for 160 pixels) are repeated, and when the magnification is 80%, 100 clocks (data for 100 pixels) are repeated.

Furthermore, since the data ROM 311 has a slow access time, it is read out using a clock having a lower frequency than the normal reading speed. The write timing is synchronized with the data transfer clock SETCLK.

The buffer 316 is provided to prevent the signal from the data ROM 311 from having an adverse effect on the data selection memory 320 and the synchronization circuit 370 side, which will be described later, in the image reading state. It is active only during the period ``.

A buffer 317 is provided to control the output state of the write start address or read start address. Therefore, as mentioned above,
Address data is output only in normal recording mode. Therefore, the buffer 317 is controlled by the mode control signal PC generated by the system control circuit 80.

The control signal ES is also used as an enable signal for writing to the data selection memory 320 (see FIG. 14).

When writing of data (4096 pieces of data) to the data selection memory 320 is completed, the counter 360
A transfer end signal CS is output from the transfer end signal CS, thereby ending the data writing period (see FIG. 26).

Thereafter, the normal image processing mode is entered, and the interpolation selection data SD and processing timing signal TD are read out from the data selection memory 320 and supplied to the subsequent synchronization circuit 370 (see FIG. 14).

The writing start address and the reading start address are determined using a predetermined period before starting writing data to the data selection memory 320. Therefore, the output timing of the address set control signal is as shown in FIG.

The output state of the address set control signals WT(L) to RD(U) generated by the control circuit 313 is controlled by the buffer 318. That is, the mode control signal PC controls the address set control signal to be output to the input buffer 400 and output buffer 450 only in the normal recording mode.

The counter 314 is cleared by a clear signal CLR (F in the figure), but the timing of this clearing differs depending on the magnification.

It should be noted that when the magnification is reduced, the image becomes as shown in FIGS. 26G and 26H. G and H in the figure show the relationship between the address data of the counter 314 and the clear signal CLR supplied thereto when the magnification is 80%.

As described above, the processing timing signal TD is selected to be "1" when the interpolated data S exists, and "0" when the interpolated data S does not exist or when the data is thinned out.

FIG. 27 shows an example of the synchronization circuit 370 in FIG. 14.

As shown, the synchronization circuit 370 includes a plurality of latch circuits 371 to 375 and a plurality of AND gates 38.
The interpolation selection data SD is sequentially latched by latch circuits 371, 372 and 375.

On the other hand, bit 1 of the processing timing signal TD
The data is sequentially latched by latch circuits 371 to 374.

The latch circuits 371 to 374 have synchronous clocks.
CLK2 is supplied to the remaining latch circuits 375 and AND gates 381-384 as a synchronous clock CLK2 whose phase is inverted.

On the other hand, the latched processing timing signal TD is supplied to a plurality of AND gates 381-384. The output of the AND gate 381 is supplied as the read clock RDCLK of the input buffer 400, and the output of the AND gate 382 is supplied as the latch clock DLCK of the latch circuits 11 and 12.

Similarly, the output of AND gate 384 is provided as write clock LCK2 of output buffer 450, and the output of AND gate 383 is provided as latch clock LCK1 of latch circuit 14.

Here, when the processing timing signal TD is "1", the AND gates 381 to 384 are open and the signal is "0".
Closed when .

By configuring the synchronization circuit 370 in this manner, it is possible to generate read and write clocks having a frequency corresponding to a specified magnification. A specific example will be explained below.

FIG. 28 shows a timing chart when a magnification of 160% is selected.

First, as shown in FIG. 30, 4 bits of the data output from the data selection memory 320 are interpolation selection data SD, and the remaining 4 bits are interpolation selection data SD.
Of the bits, bit 0 is used as data for the read clock RDCLK for the input buffer 400 and the latch clock DLCK for the latch circuits 11 and 12.

Bit 1 is also used as the write clock LCK1 to the output buffer 450 and the latch clock LCK2 to the latch circuit 14. Bit 2 is used as a repeat signal to data ROM 311 and a clear signal CLR to counter 314. Bit 3 is an unused bit in this example.

Now, when the magnification is 160%, the interpolation selection data SD shown in FIG. 28B is output from the data selection memory 320, and the data shown in FIG. 28D and E are used as bits 0 and 1 of the processing timing signal TD. Output.

Both B and C in the same figure show interpolation selection data SD,
Figure B shows the timing before latching by the latch circuit 371, and Figure C shows the timing after latching.

Therefore, from the next stage latch circuit 372,
As shown in ~H, each signal is output with a delay of one cycle. Since the interpolated selection data SD is further latched by the latch circuit 375, it is delayed by one cycle, so that the result is as shown in FIG. The interpolation selection data SD shown in FIG. 1I is supplied to the interpolation ROM 13 as address data.

Since the AND gates 381 and 382 are supplied with the bit 0 processing timing signal TD shown in D and G in the same figure, a synchronous clock having the opposite phase to these signals is supplied.
If you AND CLK2, the read clock RDCLK and latch clock shown in J and K in the same figure will be
DLCK is obtained.

Furthermore, in the latch circuits 373 and 374, bit 1
Since the processing timing signal TD is latched (L and M in the same figure), the AND gate 383,
From 384, clocks as shown in N and O in the same figure are available.
LCK1 and LCK2 are output. These clocks LCK1 and LCK2 have opposite phases to each other, but their frequency is the same as that of the synchronous clock CLK1.

In this way, when the magnification factor is selected,
Only the read clock RDCLK supplied to input buffer 400 is changed in frequency.

FIG. 29 is a timing chart when reducing the size to 80%.

In this case, the data selection memory 320 outputs the interpolation selection data SD shown in FIG. 2B, and the data shown in FIG. 2D and E are output as bits 0 and 1 of the processing timing signal TD.

The read clock RDCLK supplied to the input buffer 400 and the latch clock RDCK to the latch circuits 11 and 12 are as shown in J and K in the figure.
That is, these frequencies do not change.

On the other hand, since the latch circuits 373 and 374 output the latch clocks shown in the figure L and M, the latch clock LCK1 shown in the figure N is obtained from the AND gate 383. From the other AND gate 384, a write clock LCK2 shown at O in the figure is obtained.

In this way, when reducing the image, the output buffer 450
Only the frequency of the write clock will be changed according to the set multiplier.

Now, as mentioned at the beginning, when an enlarged/reduced image is to be recorded with reference to the center line l of the recording paper P, first when enlarging the image, the input buffer 4 is
The read start address of 00 may be controlled according to the enlargement magnification. On the other hand, when reducing an image, the writing start address to the output buffer 450 may be controlled according to the reduction magnification. The reason for this will be explained next.

As mentioned above, the maximum image reading size of CCD56 and 57 is B4 size, and its resolution is
If it is assumed to be 16 dots/mm, the memory capacity for one line is 4096 bits. Therefore, the line memories 401, 402 and 451, 452 only need to have a capacity of 4096 bits.

At the same magnification, line data with a capacity of 4096 bits is supplied as is to the output buffer 450, and then
It will be supplied to the output device 65.

On the other hand, when enlarging an image, the input buffer is 40
The amount of output image data from 0 will increase according to the magnification, and the increased image data will be supplied as is to the output buffer 450, so if left as is, the image data will overflow and necessary image data will be leaked. Not only can the image not be stored in the output buffer 450 without the center of the image, but the image cannot be recorded with the center as a reference.

When the original image data read out from the input buffer 400 is as shown in FIG. 31A, if it is enlarged twice, the amount of image data becomes twice that amount. On the other hand, the 2048th bit of the image data corresponds to 1/2 of the capacity (4096 bits) of an effective horizontal line (effective length) in B4 size, and corresponds exactly to the center l of the recorded image.

Therefore, if you read out the 1024th bit to 3072nd bit of the image data supplied to the input buffer 400 and perform enlargement processing on this total of 2048 bits of image data, the amount of data will be reduced to 2 as a result of the enlargement processing. Even if it were doubled, it would still be within the range that can be handled by the output buffer 450 (B in the same figure).

Moreover, as shown in FIG. 31A, since the data that has been image-processed around the center l of the image (the 2048th bit of the original image data) is supplied to the output buffer 450, the required enlargement is No part of the image will be recorded as missing.

For this reason, when enlarging, input buffer 4
By controlling the readout start address of 00 according to the set magnification, it is possible to record the image on the recording paper P centering on the center of the image, as shown in FIG. 32B.

Therefore, the reading start address during enlargement is set as follows.

Read start address = (4096 x enlargement magnification - 4096)/2 Here, if you want to enlarge to 200%, the enlargement magnification will be 200/100 = 2.0.

During the reduction process, as shown in FIG. 31C, data is written to and read from the input buffer 400 in the same way as in the case of the same magnification, and data is written from address 0 and read from address 0.

Then, when the image is reduced by 0.5 times, the image data for one line is reduced to 1/2 by the interpolation process.
This image data is reduced to an output buffer 45.
Written to 0.

Here, if the image data D read from the input buffer 400 is written as is to the output buffer 450, the image data will be written from the 0 address of the output buffer 450, and the image data from this 0 address will be used to transfer the recording paper to the output buffer 450. Since the image will be recorded sequentially from one side of the
It will only be recorded as shown.

To avoid this, change the write start address to
It is sufficient to set it at the 1024th address (D in the same figure).

If you set the read start address to 0 address, empty data (corresponding to white) will be recorded up to the 1024th bit, so
The recorded image is a reduced image centered on the center l of the recording paper P, as shown in FIG. 32A.

Therefore, the write start address of the output buffer 450 is set as follows: Write start address = (4096-4096 x reduction magnification)/2.

Therefore, if the read start address of the input buffer 400 and the write start address of the output buffer 450 are appropriately selected according to the enlargement/reduction magnification, even if a line memory with a capacity of one line is used, the center Standard recording processing can be achieved. FIG. 33 shows an example of setting address data.

FIG. 34 shows an example of the processing operation described above.

As shown in D to G in the figure, the input buffer 400
Read start address and output buffer 45
Any write start address to 0 is set during horizontal ineffectiveness.

The write and read timings for the input buffer 400 are shown in FIGS. Similarly, write and read timings for the output buffer 450 are shown in F and G of the same figure.

As described above, the control signals IHNSEL and OUTSEL are rectangular wave signals having two horizontal periods as one period.

Now, FIG. 35 shows the relationship between each sampling position used when enlarging an image and the interpolation selection data SD. The example data is magnification M of 160% (1.6x)
In this case, the magnification can be set at intervals of 1%.

When the enlargement rate is 160%, the sampling interval is 100/160 (=0.62500), so the sampling position (theoretical value) relative to the original data position and the interpolation selection data referenced at that time.
The relationship with SD is as shown in the figure.

In the interpolated selection data SD at the original data position "0", the former data (O) is the interpolated selection data SD when the sampling position is (0.00000)
The latter data (A) is interpolated selection data SD when the sampling position is (0.62500).

Note that the original data positions are 2, 4, 7, 9.
In such places, the value of the latter interpolation selection data SD does not exist. This indicates that during that cycle period, there is no increase in data due to expansion and only one piece of data exists.

These data are actually stored in the data ROM 311 in a state as shown in FIG.
In Figure 36, base address ADRS (vertical axis)
The data referenced by and step number (horizontal axis) is interpolation selection data SD on the left side, and data on the right side is input buffer 400 and output buffer 4.
50 clock control signals and counter 3
14 clear signal CLR (processing timing signal
TD).

The bit configuration of the data ROM 311 is as shown in Figure 34, so the read clock RDCLK and latch clock
When outputting DLCK, bit 0 = “1” and the writing clock LCK2 and latch clock
When outputting CLK1, bit 1 should be “1”, and bit 2 should be “0” at the data position of the repetition period.

In other words, in the interpolation selection data SD, bit 0 corresponding to the previous cycle is set to "1", and the subsequent cycle is set to "0".
And it is sufficient.

Further, bit 1 is always set to "1". Therefore, ××××0111=×7 ××××0110=×6 ××××0011=×3 becomes.

FIG. 37 shows a part of a data table of interpolation selection data SD used at the time of image reduction. The illustrated data is when the reduction rate M is 80%. In the figure, the * mark indicates thinned-out data (invalid data).
Actually, it is stored in the memory in the state shown in FIG. 38. Bit 1 becomes "0" only in the data corresponding to the * mark. In the figure, it is shown as "05".

Next, regarding the enlargement/reduction processing operation described above,
First, the enlargement processing operation will be explained in detail with reference to FIG. 39 and subsequent figures. For convenience of explanation, the magnification rate M is 160%.
shall be.

FIG. 39 is an analog diagram of the relationship between the original data and the interpolated data.
D indicates original data, and S indicates converted data after interpolation (interpolated data).

The relationship between the image information level and the interpolated data at this time is as shown in FIG. Further, the relationship between the sampling pitch and the interpolation selection data SD during interpolation at this time is as shown in FIG.

A timing chart of signals in each part during this interpolation process is shown in FIG.

The original image data obtained from CCDs 56 and 57 are D0 (0), D1 (F), D2 (F), D3 (0), D4
(0) (The inside of the bracket indicates the gradation level of each image data).

Read clock to input buffer 400
When RDCLK is supplied, image data D is output after access time t1 (Fig. 40A, B),
This is latched by the latch clock DLCK (C in the same figure). Latch circuit 1 in synchronization with the latch clock
When D1 (F) is output from 1, D0 (0) is output from the latch circuit 12 (D and E in the same figure).

Note that the latch pulse DLCK is a synchronous clock.
It lags behind CLK1 by one cycle.

On the other hand, the third
The data table shown in FIG. 8 is referred to. 0; A; 4; E;... (40th
Figure F) is output.

As a result, the image data is output from the interpolation ROM 13.
The interpolation data table is referred to using D0, D1 and the interpolation selection data SD, and the necessary interpolation data S (G in the figure) is output. Therefore, the interpolated data S is 0 (S ₀ ), 9 (S ₁ ), F (S ₂ ), F (S ₃ ), 8 (S ₄ ),
0
(S ₅ ),...

The read interpolation data S is sequentially sent to the latch circuit 14 (H and I in the figure). The binarized interpolated data S is written to the output buffer 450 by the write clock LCK2 (J,
K).

In addition, in FIG. 40, t2 is the interpolation ROM 13
, and t3 is the access time of the binarization means 69.

Next, the reduction process will be explained.

FIG. 41 is an analog diagram of the image signal when the reduction ratio is selected as 80% (0.8 times), and the image data D0, D1, D2, D3,...
are represented by ○ marks, and interpolated data S0, S1,... are represented by × marks. FIG. 42 shows a timing chart of the signals at that time, and the relationship between the original image data D and the interpolated data S used at that time is the third
The relationship between the interpolation selection data SD in FIG. 8 is as shown in FIG. 37.

It is assumed that the gradation level of the image data is the same as in the case of the enlargement process described above.

Then, from the latch circuits 11 and 12, two adjacent
two image data (e.g. image data D1, D0)
is supplied to the interpolation ROM 13 as an address signal, and an externally set scaling factor (80%) is supplied to the data selection signal writing circuit 310, as in the case of the enlargement process described above.

In the case of reduction processing, the read clock
Both RDCLK and latch pulse DLCK are synchronous clocks.
Since it has the same frequency as CLK1 and data as shown in FIG. 37 is selected as the interpolation selection data SD, the input buffer 400
The relationship between the signals from to the interpolation ROM 13 is as shown in FIGS. 42A to 42F.

On the other hand, latch pulse LCK1 is G in the same figure.
Therefore, the latch output becomes as shown in figure H.
Here, since the write clock LCK2 also has the same frequency as the latch pulse LCK1, data as shown in FIG. 1 is written into the output buffer 450.

In the above embodiment, if the magnification of enlargement or reduction is changed, the interpolation selection data SD output from the selection memory 320 for interpolation data changes, and the interpolation selection data SD is changed.
It will be clear that 13 is addressed accordingly and the corresponding interpolated data S is output.

Next, read the image data only in the specified area,
Next, an example of setting a write or read start address necessary for recording an enlarged/reduced image at a designated recording position will be explained.

43A to 43D are explanatory diagrams of recording position designation, and for convenience of explanation, the diagrams are explanatory diagrams when enlarging an image, but it goes without saying that this can also be applied to the case of image reduction.

First, the designated image areas are designated as n1 to n4, and the enlarged/reduced recorded image areas are designated as N1 to N4.

Then, the number of data and the number of lines from the reference point to the specified area in the main scanning direction (horizontal direction) and the sub-scanning direction (vertical direction) are set as I0, I1, L0, and L1.

A and C in the same figure show an example of I0>I1, and B and D of the same figure show an example of I0<I1.

As mentioned above, when the recording density is 16 dots/mm, I0 and I1 are as follows: I0=16×x1 I1=16×x3.

Here, if the specified magnification is m, the image data of I0 increases to m·I0. Figure 44 shows I1＞
m·I0, FIG. 45 shows the case of I1<m·I0.

In the case of I1>m・I0, the image data read out from the input buffer 400 and expanded (m・I0)
If you write this as it is to the output buffer 450 and record it, the recording start point in the main scanning direction will be
Before reaching x3, enlarged image data m·(x2−x1) in the original image area n is recorded.

Further, in the case of I1<m·I0, even when the recording start point x3 is reached, the enlarged image data in the image area n is not recorded, and the data outside the area is recorded in a deviated manner.

In order to prevent this from happening, in the present invention, the input buffer 400 and the output buffer 45
The read start address or write start address of 0 is controlled according to the specified magnification.

Therefore, the reading start address of the input buffer 400 is selected so that processing can be performed from the point (x1, y2) of the image area n, and the read image area n is placed at the specified recording position (x3, y2). y3)
The write start address to the output buffer 450 is selected as recorded in .

The relationship of addresses for input buffer 400 and output buffer 450 is shown in FIGS. 46 and 47.

For input buffer 400, write start address = 0 read start address = 16 x x 1 (I0) For output buffer 450, write start address = 16 x x 3 (I1) read start address = 0 In this way, By setting write and read start addresses for the input buffer 450 and output buffer 450, it is possible to move to a specified position (coordinates) in the main scanning direction.

The movement of the image recording position in the sub-scanning direction can be realized by advancing the reading start of the image reading device 50 or the writing start of the output device 65.

To show only the results, when L1>L0, the output device 65 is started earlier than usual by T0=(L1−m·L0)·main scanning time. The main scanning time refers to the time required in the main scanning direction to scan one line.

When L1<L0, the image reading device 50 is started earlier than usual by T0=(L0−m·L1)・main scanning time.

In addition to selecting the operation timing in this way,
By selecting the write and read addresses described above, it becomes possible to correctly record the enlarged/reduced image in the read area at a preset recording position.

When editing, such as specifying a recording position, the write start address or read start address calculated by the system control circuit 80 is used, and the write start address or read start address for central reference recording is the data.
Since it is stored in the ROM 311, there is no need to use a CPU or the like to calculate the necessary address data.

In the above description, an example is shown in which an image is enlarged, but it goes without saying that the present invention can also be applied to cases where only the same-size processing position is moved and recorded, or where the image is recorded after being subjected to reduction processing.

Incidentally, in the above description, the invention is applied to an image processing apparatus that reads an image based on the center of the document and records the image based on the center of the recording paper, but the present invention can also be applied to other image processing apparatuses. can do.

First, when both image reading and image recording are processed based on one side of the original (recording paper), the image reading start position of the CCDs 56 and 57 and the recording start position (light scanning start position) position,
In a laser printer, since the recording beam start position of the laser beam is the same, the present invention can be applied without any problem.

Second, in an image processing apparatus of the type in which image reading is performed based on the center line of the document and image recording is processed based on one side of the recording paper, the readout start address of the input buffer 400 is as follows. become.

In this case, the write start address of the output buffer 450 is always 0. On the other hand, the read start address cannot be determined only by the magnification signal. It varies depending on the size of the manuscript.

Therefore, in this type of image processing apparatus, the readout start address is determined from the specified magnification indicating the document size.

As shown in FIG. 48, the original 52 to be read
The following shows when the size of is A4 size.

As mentioned above, when the width is 16dots/mm, the number of bits for the width of A4 size is 210mm x 16ots/mm = 3360 bits, so if the maximum scanned document size is B4 size, the width Y in Figure 48 is The value obtained by multiplying by the magnification becomes the read start address for the line memory.

Therefore, the read start address at the same magnification is: (4096-3360)/2=368 bits becomes.

FIG. 50 shows the values of the read start address of the input buffer 400 and the write start address of the output buffer 450 at arbitrary magnifications. However, the original size is A4.

The reason why the write start address is constant regardless of the magnification is because the image is recorded with one side as the reference.

Third, as shown in FIG. 49, in an image processing apparatus of the type in which image reading is performed with one side as a reference and image recording is processed with reference to the center line l of the recording paper, the input buffer 400 is The read start address and the write start address of the output buffer 450 are determined as follows.

That is, in the case of 4096>3360×magnification, the write start address of the output buffer 450 is set, and in the opposite case, the read start address of the input buffer 400 is set.

Therefore, when 4096 > 3360 x magnification, the write start address is: Write start address = (4096 - 3360 x magnification) /
2 At this time, the read start address of the input buffer 400 is the 0 address.

On the other hand, when 4096<3360×magnification, the readout start address is: Readout start address = (3360−4096/magnification)/
It is 2. At this time, the write start address of the output buffer 450 becomes 0.

As a result, the input buffer 4 at any magnification
Read start address of 00 and output buffer 45
The write start address of 0 has a value as shown in FIG.

In this way, the reading start address or the writing start address can be changed depending on the standards for reading or writing the document.

[Effects of the Invention] As explained above, in this invention, the write start address or read start address of the input buffer and output buffer is controlled according to the settings such as the specified magnification and the specified recording area. Images that are enlarged or reduced to any position can be recorded in real time.

Therefore, it has the feature that an image of an area desired by the operator can be recorded at a desired position on the recording paper, and an image of a desired size can be recorded.

In addition, in the editing mode, the write start address or the read start address calculated in the system control circuit 80 is used, and in the normal recording mode, the address data stored in the data ROM 311 is used. The arithmetic processing time in the normal recording mode can be significantly shortened, and the copy processing time can also be shortened.

Of course, in this invention, since the writing or reading start address to the line memory is controlled according to the magnification, the same effect as when enlarging/reducing is performed based on the center of the reading side can be obtained. , the recording will be performed with the center of the recording paper as a reference.

As a result, the reduced image may be recorded unevenly, or
There is no risk of an image being recorded outside the transfer area of the recording paper.

Furthermore, even when an image is enlarged, there is no risk that the margin will be enlarged, so the required image can be recorded correctly.

Furthermore, since the present invention obtains interpolated data while referring to a data table, it has remarkable effects such as better image quality and faster processing than conventional methods.

[Brief explanation of drawings]

FIG. 1 is a system diagram showing an overview of an image processing device that can be enlarged and reduced according to the present invention, FIG. 2 is a system diagram showing an example of an image reading device, FIG. 3 is a waveform diagram for explaining its operation, and FIG. The figure is an explanatory diagram of shading correction, FIG. 5 is a system diagram showing an example of a shading correction circuit, FIGS. 6 and 7 are diagrams for explaining color separation, and FIG. 8 is a diagram showing an example of a color separation map. , FIG. 9 is a system diagram showing an example of a color separation circuit, FIG. 10 is a system diagram showing an example of a color selection circuit, and FIG. 11 is a system diagram showing an example of a color selection circuit.
12 and 12 are waveform diagrams for explaining the image forming process, FIG. 13 is a configuration diagram showing an example of a simple electrophotographic color copying machine, and FIG. 14 is a system showing an example of an enlargement/reduction circuit. Figures 15 and 16 are diagrams showing the relationship between image data, interpolation selection data SD, and interpolation data S, Figure 17 is a diagram showing an example of threshold data used for line drawing, and Figure 18 is a photograph. FIG. 19 is a system diagram showing an example of an input buffer, FIG. 20 is a system diagram showing an example of an output buffer, and FIGS. 21 to 24 are diagrams showing an example of the output buffer. 25 is a system diagram showing an example of a data selection signal writing circuit; FIG. 26 is a waveform diagram showing an example of the operation; FIG. 27 is a system diagram showing an example of a synchronous circuit; FIG. 29 and 29 are waveform diagrams for explaining the operation, and FIG. 30 is the data.
ROM configuration diagram, Figure 31 is a diagram for explaining recording of the center reference during enlargement/reduction, Figure 32 is a diagram showing an example of recording of the center reference, and Figure 33 is a diagram for reading when recording the center reference. A diagram showing an example of start address data, FIG. 34 is a waveform diagram for explaining the processing operation at that time, and FIGS. 35 and 36.
37 and 38 are diagrams showing specific numerical examples of the sampling position and interpolation selection data when reducing the image, FIG. 39 is a diagram of an image signal to explain image enlargement, FIG. 40 is a waveform diagram to explain the operation at that time, FIG. 41 is a diagram of an image signal to explain image reduction, and FIG. 42 is a diagram of the image signal. FIG. 43 is an explanatory diagram of recording position designation, FIGS. 44 and 45 are diagrams showing the relationship between recording position and enlargement processing, and FIGS. 46 and 47 are diagrams for explaining the operation at that time. A diagram showing the relationship between the write start address and the read start address, Figures 48 and 49 are diagrams showing other examples of image reading and image recording, and Figures 50 and 51 are the read start used at that time. A diagram showing the relationship between addresses and preset data, FIG. 52 is a system diagram showing an example of the main parts of a conventional image processing device that can be enlarged and reduced, FIG. 53 is a waveform diagram to explain its operation, and FIG. 54 55 is an explanatory diagram of an image reading system, FIG. 55 is an explanatory diagram of a recorded image, and FIG. 56 is an explanatory diagram of image recording by specifying a recording position. 2... enlarging/reducing circuit, 50... image reading device, 65... output device, 80... system control circuit, 300... interpolation data selection means,
310...Data selection signal writing circuit, 320...
...Data selection memory, 400...Input buffer,
450...Output buffer, D...Image data, S
...Interpolated data, SD...Interpolated selection data, TD...
...Processing timing signal.

Claims (1)

[Scope of Claims] 1. In an image processing device capable of specifying a recording position and capable of performing image processing such as enlarging or reducing an image using image data read by photoelectrically converting image information, an input to the image data is provided. An image in which a recording position can be specified, comprising a buffer, an output buffer, and means for controlling a write start address or a read start address of the input buffer and output buffer according to a specified magnification and the position of the specified area. Processing equipment. 2. An image processing apparatus capable of specifying a recording position according to claim 1, wherein the readout start address of the input buffer is controlled in accordance with a specified magnification. 3. An image processing apparatus capable of specifying a recording position according to claim 1, wherein the write start address of the output buffer is controlled according to a specified magnification.