JPS62264761A - Color picture processor capable of magnification and reduction - Google Patents

Abstract

PURPOSE:To prevent the deterioration of quality of a recording picture and the reduction in the color separation characteristic by applying color separation to a picture signal, applying magnification/reduction and applying multi-value processing. CONSTITUTION:Picture information such as an original 52 is converted into a picture data of prescribed bit number corresponding to each color signal by using a picture reader 50 so as to apply picture processing such as color separation processing and A/D conversion processing. Each picture data are fed to a picture processing circuit 2 after a magnification for a magnification designated by an operation/display section 75 and a threshold value selection data selecting a threshold value to binary-code the picture data in response to the kind or density of the recorded picture are fetched by a control circuit 80. A buffer circuit 90 executes the processing based on the picture recording processing by the central reference and the recording designation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention relates to a color image processing device that can be enlarged and reduced and can be applied to a simple electrophotographic color copying machine or the like.

[Front leg of the invention] In an image processing device capable of enlarging or reducing an original image, the output device used therein, such as a display device or a recording device, is generally represented only by black and white. There are many.

The dither method is known as a method for expressing halftones in a pseudo manner using such an output device. A halftone image is expressed by changing the number of dots recorded within the image.

Therefore, the dither method is as shown in FIG.

A portion corresponding to one pixel of a document is recorded in one dot and one dot using a predetermined threshold value matrix.

As a result, output data that has been converted into a second image is obtained.

This output data pseudo-represents a halftone image using binary values of white and black.

Incidentally, a color image processing apparatus having such an output device has been developed which can enlarge or reduce an original image at an externally set magnification and record the image. This is an image signal that has been enlarged or reduced by increasing or thinning out appropriate image data according to the enlargement φ reduction magnification for the pixel data of the original image read by an image reading means such as a CCD. This is a device designed to help you achieve this goal.

However, such enlargement/reduction processing is intended for binary image signals. Also, as another method, C
The image signal obtained by enlarging/reducing the signal from the OD is separated into a plurality of color signals necessary for color recording.

[Problems that IN+ tries to solve] By the way, J:
In the conventional color image processing apparatus described above, image processing such as enlargement/reduction is performed from binarized image data, resulting in a significant deterioration in image quality.

This is because enlarging/reducing processing is an image processing that increases or thins out image data.
If it is digitized data, it is only necessary to increase or thin out data that is “1” or “ON”.
For example, when an image with diagonal lines is enlarged, the jaggedness of the diagonal lines in the image becomes []t.

Additionally, if image processing such as enlargement or reduction is performed before separating into multiple color signals, color separation performance may deteriorate depending on the specified magnification, or in the worst case, the characteristics of one color component may have to be changed for each magnification. This caused an unavoidable situation.

Separation of the original color image into multiple color signals is performed by referring to a color separation map and selecting a predetermined color.
This is because color separation data at the same magnification is stored, so if the magnification of the enlarged fist differs, the color data corresponding to the original color image cannot be referenced.

Therefore, if a single color separation map is used, the color separation characteristics will naturally deteriorate. In order to avoid this, if color separation maps were used for each magnification, the control system would become complicated.

Therefore, in this invention, the deterioration of the quality of the recorded image and the color separation a
This paper proposes a color image processing device that can be enlarged and reduced without causing problems such as low F characteristics.

[Problems to be Solved by the Invention] In order to solve the above-mentioned problems, the present invention provides an image reading device that separates image information into a plurality of color separation images and converts these plurality of color separation images into image signals. , a color separation means that performs color separation based on image signals from an image reading device, and a plurality of color signals obtained from the color separation means for magnification and color separation.
It is characterized by comprising an image processing circuit that performs reduction, and a multi-fume conversion circuit that performs multi-value processing on the enlarged/reduced color signal based on a threshold value set for each color signal. .

[Operation] When the image is converted into 2-1 after the enlargement/reduction process, the halftone image itself is enlarged/reduced by 9/9 and then binarized, so that no deterioration in image quality occurs.

Furthermore, since the enlargement/reduction processing is performed after separating the signals into a plurality of color signals, a medium color separation map can be used regardless of the enlargement/reduction magnification.

As a result, the color separation characteristics do not differ depending on the enlargement/reduction magnification, and color separation corresponding to the original color image is performed.

Furthermore, if the darkness value table for multi-value conversion for each separated color is selected in accordance with the density of the original color image, color recording faithful to the original color image can be achieved.

[Embodiment] Next, a color image processing device that can be enlarged and reduced according to the present invention will be described.

However, in the embodiment shown below, a simple electronic color copying machine is used as an output device, in which images are read and recorded based on the center, and the recording position of the image can be set externally. This is a case where the present invention is applied to a color image processing device.

Therefore, first, the prerequisites for such a color image processing apparatus to which the present invention is applied will be explained.

The explanation will start from image reading and recording using the center reference.

As shown in FIG. 37, when W is the maximum reading gap width of the image reading means, the image data of the original 52 is read based on the center line of the original JtLt table 51, and the image data of the original 52 is read based on this center border. When the image is recorded at 1:1 magnification,
Although it is recorded as shown in FIG. 38B, when m is small, it is recorded as shown in FIG. 38A.

Therefore, when the size of the recording paper 53 to be recorded is small, it is possible that it will be outside the transfer area of the recording paper.
In that case, the reduced image cannot be correctly recorded on the recording paper.

Even when the size of the recording paper 53 is large, there is a drawback that the reduced image is recorded on the edge of the recording paper 53.

Furthermore, during the enlargement process, the margins of the original document are also enlarged, resulting in an enlargement as shown in FIG. 38C. Therefore, there is a possibility that the required range of images cannot be recorded on the predetermined recording paper 53.

Therefore, in such a center-based system, it is necessary to appropriately adjust the image data processing timing (in terms of A-type, the timing of reading and writing image data to an output buffer circuit, which will be described later). In the embodiment, an arrangement is made such that an image is recorded with the center of the recording paper as a reference at any magnification.

Next, the color image processing apparatus configured so that the recording position can be specified from the outside is used for the original 52 shown in FIG. 39A.
For example, by enlarging the area n of the recording paper 53 shown in FIG.
The enlarged image N can be recorded at the specified position l of the color image processing apparatus 1. FIG. 1 shows a schematic configuration of a color image processing apparatus according to the present invention.

Image information such as the original 52 is subjected to color separation processing, A/D conversion processing, and other image processing by the image reading device 50, so that image data of a predetermined number of bits corresponding to each color signal, for example, 16th floor It is converted into m(0-F) image data.

Each image data is subjected to image processing such as enlargement/reduction in the image processing circuit 2, and then sent to the output buffer circuit 90.
Image recording processing based on the central reference and processing based on recording designation, which will be described later, are executed.

These processes are accomplished by controlling the address or read address for the line memory provided in the output buffer circuit 90.

The image data corresponding to each color read out from the output buffer circuit 90 is supplied to the output device 65, and the image is recorded at an externally set magnification or at an externally set position. .

The image reading device 50 is equipped with a drive motor, an exposure lamp, etc. for driving the image reading means, and these are controlled at predetermined timing by control signals obtained from a sequence control circuit (sequence driver) 70. Ru. The sequence control circuit 70 also receives data from a position sensor (not particularly shown).

In the operation/display section 75, various input data such as magnification designation, recording position l designation, recording color designation, etc. are input, and the contents thereof are displayed.

Elements such as LEDs are used for the display stage.

The system control circuit 80 performs the above-mentioned various controls, controls the entire image processing device, and manages the state.
controlled by Therefore, it is appropriate for this system control circuit 80 to be controlled by a microcomputer using a CPU.

The figure shows an example of microcomputer control, and necessary image processing data and control data are exchanged between this control circuit 80 and the various circuit systems described above via a system bus 81.

The details will be explained below.

A single image reading start signal, a start signal for shading correction, a recording color designation signal, etc. are supplied to the image reading circuit 50 via the system bus 81.

For the image processing circuit 2, a threshold value for dividing the image data into two images is selected according to magnification data for specifying the magnification specified on the operation fist display section 75, and the type and density of the image to be recorded. Threshold selection data to be used, as well as recording position designation data when a recording position is designated, are taken into the control circuit 80 and then supplied via the system bus 81.

The output buffer circuit 90 is supplied with a write or read start address for the line memory provided therein. The fill or read start address data set in the line memory differs depending on the designated magnification, recording position designation data, etc.

The output device 65 is supplied with a start signal for image recording, a recording paper size selection signal, and the like. As the output device 65, an electrophotographic color copying machine or the like is used.

Next, these components will be explained in detail.

For convenience of explanation, an example of the configuration of a simplified color copying machine applicable to the present invention will first be described with reference to FIG. 6 and subsequent figures.

A simple color copying machine attempts to record a color image by separating color information into about three types of color information.9 In this example, the three types of color information to be separated are black, BK,
Red R and blue B are illustrated.

In FIG. 6, 200 is an example of a main part of a color copying machine, and 201 is a drum-shaped image forming body, on the surface of which a photoconductive photoreceptor surface layer such as selenium Se is formed, and an optical image is formed. An electrostatic image (electrostatic latent image) corresponding to the image can be formed.

The following members are sequentially arranged on the circumferential surface of the image forming body 201 in the direction of rotation thereof.

The surface of the image forming body 201 is charged to -1 by a charger 202, and then the surface is uniformly exposed to weak light by an exposure lamp 203.

The surface of the charged and exposed image forming body 201 is subjected to image exposure based on each color separation image (the optical image thereof is indicated by 204).

After image exposure, the image is developed by a predetermined developing device.

The developing devices are arranged in a number corresponding to the color separated images.

In this example, the developing device 20 is filled with black toner developer.
5, a developing device 206 filled with a red toner developer, and a developing device 207 filled with a blue toner developer.
They are sequentially arranged facing the surface of the image forming body 201 in this order in the rotation direction of the image forming body 201.

The developing devices 205 to 207 are sequentially selected in synchronization with the rotation of the image forming body 201. For example, by selecting the developing device rE205, toner adheres to the electrostatic image based on the black color separation image, and thus the black color separation is performed. The image is developed.

A pre-transfer charger 209 and a pre-transfer exposure lamp 210 are provided on the developing device 207 side, and these make it easy to transfer the color image onto the recording medium P. However, these pre-transfer charger 209 and pre-transfer exposure lamp 210 are provided as necessary.

The color image developed on the image forming body 201 is transferred to the transfer device 2.
11, the image is transferred onto the recording medium P. The transferred recording medium P is subjected to a fixing process by a fixing device 212 at a subsequent stage, and then the recording medium P is discharged.

Note that the static eliminator 213 is composed of a static eliminator lamp, a static eliminator corona discharger, or a combination of both.

The cleaning device 214 is composed of a cleaning blade and a fur brush, and is used to remove residual toner remaining on the drum surface after the color image of the image forming member 201 has been transferred.

It is well known that this removal operation is performed so that the surface of the image forming member 201 is separated by the time the developed surface is reached.

As the charger 202, a scorotron corona radiator or the like can be used. This is because stable charging can be applied to the image forming body 201 with less influence from previous charging.

As the image exposure 204, light obtained by a laser beam scanner can be used. In the case of a laser beam scanner, clear color images can be recorded.

For at least the second and subsequent development steps that are repeated to superimpose color toner images, it is necessary to ensure that the toner T that has adhered to the image forming body 201 from the previous development is not disturbed by the subsequent development. In this sense, it is preferable that such development be performed by a non-contact jumping development method. FIG. 6 shows a type of developing device that performs development by such non-contact jumping development.

As the developer, it is preferable to use a so-called two-component developer in which a non-magnetic toner and a magnetic carrier are mixed.
This is because when the developer is made of two components, a toner with a clear color and easy charge control can be used.

FIG. 2 shows an example of the image reading device 50 and the image processing circuit 2.

In the figure, color image information (optical image) of a document 52 is captured in a graphical mirror 55.

It is separated into two color separation images. In this example, the image is separated into a color-separated image of red R and a color-separated image of cyan C7. Therefore, the cutoff of the guichroic mirror 12 is 600 nm.
A moderate amount is used. As a result, the red component becomes transmitted light, and the cyan component becomes reflected light.

The color separation images of red R and cyan cy are respectively supplied to image reading means 56 and 57 such as COD, and image signals of only the red component R and cyan component Cy are output from each image reading means 56 and 57, respectively.

FIG. 3 shows the relationship between the image signals R, CF and various timing signals, including the horizontal effective area signal (H-VALIII).
(Figure C) t*ccp 56 , 57(7) M large gM
The image signal R shown in F and G in the same figure corresponds to the reading width W.
, CF are read out in synchronization with the synchronous clock CLK (E in the figure).

These image signals R and Cy are normalized by amplifiers 58 and 59.
The signal is supplied to A/D converters 60 and 61 via the A/D converters 60 and 61, thereby being converted into a digital signal having a predetermined number of bits. The digital color image signal is supplied to the next stage color separation circuit 150, where it is separated into a plurality of color signals necessary for color image recording.

In the above example, it is a simple recording device that records a color image in three colors: red, R, blue, and black.
In the color separation circuit 150, these three color signals R, B, BK
It will be separated into Here, 3 of R, B, BK
Although the colors have been described, a specific example of six-color separation, in which the reading device may be used to separate into four complementary colors of magenta, magenta, and cyan, or four colors including black, will be described later.

One of the color signals R, B, and BK is selected by the color selection circuit 160. As mentioned above, this is per revolution of the image forming body 201! This is because an image forming process is adopted in which a color image of 11 colors is developed, and the developing devices 205 to 207 are selected in synchronization with the rotation of the image forming body 201, and the selected developing device The color signal corresponding to the color signal is selected by the color selection circuit 160.

Selection signals Gl to G3 for color signals are supplied to the terminal 170. These selection signals Gl to G3 are.

As will be described later, this is used to select the color signal to be output for three-color recording, that is, normal recording mode, and for single-color recording, that is, color-specified recording mode, and the system control circuit 80 Supplied from.

Note that color separation processing for separating color signals from a color original into three color signals is executed every rotation of the image forming body 201.

-1- The color molecule i (color separation gi from two colors to three color signals) described above is performed based on the following idea.

FIG. 7 schematically shows the spectral reflection characteristics of a color chart of color components, in which A shows the spectral reflection characteristics of achromatic colors, B shows the spectral reflection characteristics of blue, and If4
C shows red spectral reflection characteristics.

The horizontal axis shows the wavelength (nm), and the vertical axis shows the relative sensitivity (%).
00nm, the red component R is transmitted and the cyan component Cy
is reflected.

The level of the red signal H normalized with white as the standard is VR,
When the level of the cyan signal Cy is set to VC, by creating a coordinate system from these signals VR and VC, red, blue and black colors can be separated based on a created color separation map.

When determining the coordinate axes, it is necessary to consider the first-order points p.

In order to be able to express halftones, the concept of the reflectance (reflection density) of the original 11 that is compatible with the brightness signal of the television signal is adopted.

■Introduce the concept of color difference (including hue and saturation) such as red and cyan.

Therefore, luminance signal information (for example, a 5-bit digital signal) and color difference signal information (similarly, a 5-bit digital signal)
)), for example, the following may be used.

Luminance signal information = VR + VC (1) however.

0≦VR≦1, 0 (2) o≦vc
≦1. o (3) O≦VR+VC≦2
, 0 (4) VR, VC (1) Sum (VR + VC
) if black L then go Jl/(=O) to white level (=2
, 0), and all colors exist in the range from 0 to 2.0.

Color difference signal information = VR/ (VR+VC)t or VC/
(VR+VC) (5) In the case of an achromatic color, the 11th combination of the red level VR and the cyan level VC included in the overall level (VR+VC) is constant. Therefore.

VR/ (VR+VC) = VC/ (VR+VC)=
Q, 5 (6) becomes.

On the other hand, in the case of chromatic colors, for red colors, 0, 5
<Vl'l / (VR+V(: )≦1.0 (7
)0≦VC/ (VR+VC) <0, 5 (8)
In cyan color.

0≦VR/ (VR+VC) <0 , 5 (9) 0
, 5<VC/ (VR+VC)≦1.0 (10).

Therefore, the coordinate axes are (VR+VG) and VR/(V
R+VC) or (VR+VC),! :We/
By using a coordinate system having two axes (VR+VC), chromatic colors (red and cyan) and achromatic colors can be clearly separated just by level comparison processing.

In FIG. 8, the vertical axis shows the luminance signal component (VR+VC), and the horizontal axis shows the color difference signal component VC/(
VR+Vllll: shows the coordinate system when ) is taken.

If vc/(vR+vc) is used as the color difference signal component, an area smaller than 0.5 will be redish R, and an area larger than 10°5 will be cyanish (, F).

Achromatic colors exist in the vicinity of color difference signal information=0.5 and in areas with little luminance signal information.

FIG. 9 shows a specific example of a color separation map in which colors are classified according to such a color separation method.
A table is used and the example shown is divided into 32x32 blocks, so the number of address bits for this ROM table is 5 row addresses.
5 bits and column address are used. This ROM
The table stores quantized C degree corresponding values obtained from the reflection density of the original.

FIG. 4 is a system diagram showing an example of a color separation circuit 150 and a color selection circuit 160 for realizing such color separation.

A red signal R and a cyan signal cy before color separation into three colors are supplied to the terminals 150a and 150b, and the arithmetic processing circuit 15
1, processing such as gradation conversion and γ correction is executed.

The data after the arithmetic processing is used as an address signal for the memory 152 where the arithmetic result of (VR+VC) for obtaining the N-degree signal data is stored, and the arithmetic result of the color difference signal data VC: / (VR+VC) is stored. The address signal is used as an address signal for the memory 153.

Each output of these memories 152 and 153 is a memory 1 which will be described later.
It is used as an address signal of 54 to 156. The memories 154 to 156 use a data table in which data of the color separation map shown in FIG. 13 is stored for each color.

The memory 154 is for the black signal BK, the memory 155 is for the red signal R, and the memory 156 is for the n signal B.

As is clear from the color separation map shown in Fig. 9, the levels of the red signal R and cyan signal cy are detected and the three colors of red, blue and black are extracted from the two color information signals by @calculation processing. It can be separated into signals R1B and BK.

The predetermined color signals read from each of the memories 154 to 156 are supplied to a color selection circuit 160.

The color selection circuit 160 has buffer circuits 161 to 163, respectively, and color signals obtained from each buffer circuit are sent to AND gates 165 to 163.
167, and only necessary color signals are selectively output. The output is supplied to the image processing circuit 2 via the OR gate 168. These and gates, or gates 1
4-bit data is actually input to 65-168.

The gate signal 0 mentioned above is applied to the ant gates 165 and 166.
1 to G3 are supplied.

The gate signals G1-G3 correspond to the separated color signals, and three-phase gate signals G1-G3 synchronized with the rotation of the image forming body 201 are formed (FIG. 5 C-H), and at the same time, the developing The developing bias shown in FIG.
It will be supplied from 05 to 207.

As a result, the exposure process I~■ for each color (F in the same figure)
Thereafter, exposure and development processing steps are sequentially performed.

FIG. 10 is a two-dimensional diagram showing an example of the image processing circuit 2. As shown in FIG.

In this example, 1.5% between 0.5x and 2.0x
This is a case in which the image can be enlarged or reduced in increments (as an approximation of 1/84).

Here, also in this invention, in principle, the enlargement process increases the image data, and the reduction process is an interpolation process that thins out the image data. The enlargement and reduction in the main scanning direction shown in FIG. I am trying to do this by changing the movement speed of.

Slowing down the movement speed in the sub-scanning direction enlarges the original image,
If you speed it up, it will shrink.

In FIG. 10, the timing signal generation circuit IO is for obtaining timing signals etc. for controlling the processing timing of the entire image processing circuit 2, and includes CC05.
Similarly to 6,57, the synchronous clock (CLK),
Water effective area signal (H-VALI[l), vertical effective area signal (V-VALIII) and horizontal synchronization signal (H-5YN
C:) is supplied.

In addition to the above-mentioned timing signal, the timing signal generation circuit 1o outputs a clock CKL2 having twice the frequency of the synchronous clock CLK in order to process in real time a multiplication factor up to 2x.

Image data having 16 gradation levels sent out for each color signal from the color selection circuit 160 is supplied to two cascade-connected latch circuits 11 and 12 via the switching circuit 25, and is converted into 4-bit image data, Therefore, among the image data output at the halftone level, the image data DI and DO of two adjacent pixels are latched at the timing of the synchronization clock.

The switching circuit 25 is used, when setting an image area to be read, as shown in FIG. 39, to discard image information outside the set area. Therefore, the switching circuit 25 is controlled so that "o?" data (data when the image is white) is latched outside the designated area.

The control signal for the switching circuit 25 is generated by two timing signal generation circuits 10, and this timing signal generation circuit 10 also! Of course, the control is performed based on the reading area designation data supplied through the 10 port 26.

Image data DO latched by latch circuits 11 and 12,
Di is used as address data for the memory 13 for interpolation data.

The interpolation memory 13 is a data table in which image data having a new halftone level referenced from two adjacent image data (hereinafter, this image data will be referred to as interpolation data) is stored.

ROM etc. are used.

As address data for the interpolation memory 13, a data selection signal SD is used in addition to J:, the aforementioned pair of latch data DO and DI.

The data selection signal SD is a pair of latch data Do, DI.
It is used as address data for determining which data from the data table group selected by is to be used as interpolation data.

The data selection signal SD is determined by the set magnification for enlargement/reduction, as will be described later.

FIG. 11 shows latch data DO, Di and data selection value!
>SD shows an example of interpolated data S selected by SD. In the embodiment, interpolated data is obtained by linearly interpolating DO and DI data.

In the ml1 diagram, S is interpolated data (4 bits) output with 16 gradation levels, and since the image data DQ and DI used as latch data each have 16 gradation levels, the interpolated data S is , 16X16
= 256 types of data blocks are included.

The figure shows the theoretical value (5 decimal places) obtained by linear interpolation at each step when DO=O, DI=F, and the value of the interpolation data S actually stored in the IF forward slope negative slope. Each case will be shown.

In reality, the interpolated data S is in the form shown in Figure 1li12.
is memorized. However, this data is DO=O,D
This is an example of I-0 to I-F.

In FIG. 12, ADR3 is the base address, and when DO=4, the data selection signal SD (O
to F) and the interpolated data S to be output.

The actual address for the interpolation memory 13 is obtained by adding the address data ADRS and the value of the data selection signal SD on the horizontal axis.

The interpolated data S output from the interpolation memory 13 is latched by the launch circuit 14.

On the other hand, 16 is an interpolation data selection memory in which a data selection signal SD is stored. A data table is also used here, and data (data selection signal SD) used as an address for selecting interpolation data is stored.

Figure 13 shows the data selection signal SD used when enlarging the image.
0 Exemplary data showing a portion of the magnification M is 124/84
In this case, the magnification can be set at intervals of 1/84. In the figure, this mark indicates invalid data.

In this way, if the magnification can be set at intervals of 1764, the repetition period will be 6 as shown in Figure 13.
It becomes 4. Also, when the expansion rate is 124/θ4, the sampling interval is θ4/124 (= 0.51613
), so the sampling position for the repetition period is 2
1 (theoretical A1) and the data selection signal SD referred to at that time is as shown in the figure.

In the data selection signal SD at the repetition period rOJ,
The song title data (0) has a sampling position of (o, oo
ooo), and the latter data (8) has a sampling position of (0,51813).
This is the data selection signal SD at the time. These pairs of data selection signals SD differ depending on the value of the repetition period.

Note that when the repetition period is 15.32 and 48, the value of the latter data selection signal SD does not exist, which indicates that only one piece of data exists in that period.

These data are actually stored in the interpolation data selection memory 16 in a state as shown in FIG. In FIG. 14, base address ADR3 (vertical axis) and step! Of the data selection signal SD referenced by (horizontal axis), the data on the right side is old clock control data (processing timing signal TD
).

When the processing timing signal TD is "1", it becomes a write enabled state (input enable), and when it is "O", L13
Access is prohibited. Therefore, the data “OO” in the same figure
indicates invalid data.

:515 shows a part of the data table of the interpolation data selection signal SD used at the time of image reduction.

The illustrated data is the case where the reduction ratio M is 33/84. In the figure, the main mark indicates thinned-out data. This data selection signal is also stored in the memory in the state shown in FIG.

Now, as shown in FIG. 1O, the magnification signal set by the operation/display unit 75 via the I10 port 27 is stored in the address terminals A7 to A13 of the upper 7 bits of the interpolation data selection memory 16 as the 7dress data. Supplied as. The counter output of the counter circuit 15 is supplied as address data to the address end /-AO-AS of the lower 7 bits. Therefore, the counter circuit 15 has a synchronous clock C7.
LK2 is supplied.

An interpolation data selection signal is sent from the interpolation data selection memory 16.
In addition to SD, a processing timing signal TD is output.

As described above, the processing timing signal TD is selected to be "1" when interpolation data exists, and "0" when it does not exist or when data is to be thinned out.

The data selection signal SD and the processing timing signal TD are latched by the latch circuit 17. The latch timing is regulated by the synchronization clock CLK2.

The processing timing signal TD controls the timing of the interpolated data S to be latched in the latch circuit 14. Therefore, the processing timing signal TD is once supplied to the latch circuit 18 to control the access time of the interpolation memory 13. will only be delayed.

The processing timing signal TD delayed by a predetermined time (one period of the synchronous clock CLK2) is supplied to the gate circuit 19 as its gate signal.

The gate circuit 19 is supplied with the synchronous clock CLK2, and is opened when the processing timing signal TD is "1".
It is controlled so that it is closed when it is "0", and a clock is output only when it is "1".

The write clock output from the gate circuit 19 is used as a latch pulse for the latch circuit 14 to latch only valid data among the interpolated data S output from the interpolation memory 13. The write clock is also used as a clock for occupying the output buffer circuit 90 at the subsequent stage.

What has been described above is the main configuration of the image processing circuit 2. After the output data obtained from the image processing circuit 2 is once binarized, it is processed by the output buffer circuit 90 (details will be described later).
The output signal is supplied to the output device 2165 via.

An example of the circuit configuration for binarization processing will be explained with reference to FIG. 10 again.

In the figure, the dark value table 69 is connected to the main scanning counter 20 that counts the old clock.

A sub-scanning counter 21 that counts the tree f synchronization signal, and a matrix (ROM 4
! composition) 22.

The intelligence data is selected based on a control signal from the system control circuit 8o. Namely.

If the document to be read is a line drawing, certain internal data corresponding to its density is used.

The spy data in Figure 0, an example of which is shown in Figure 17, is displayed in hexadecimal.

If the original 52 is a photographic painting, 2
Since digitization is preferred, a dither matrix is used in this example as l×4(N data).

In this example, three types of matrices are used as dither matrices depending on the density of the original 52, and these are selected as appropriate. As a dither matrix, 4
A matrix composed of ×4 can be used,
When the dither matrix shown in FIG. 18A is selected when the density of the original 52 is light, the matrix shown in FIG. 18B is selected when the density is equal to ff, and the matrix shown in FIG.

Although the operator may manually select the spy data used for line drawings or the dither matrix used for photographic drawings depending on the density of the document 52, an automated method is more convenient. In the case of automation, the entire density of the document 52 is detected.

Based on the concentration, the optimum dither matrix, matrix, etc. are selected based on instructions from the system control circuit 80.

Note that the dithered image using the dither matrix uses the ffi dithering method so that one threshold value is entered in the maximum area aperture of the dither matrix (4×4 area aperture in Fig. 18) rather than random dither or conditional dither. A dithered image is preferred, and a distributed dithered image in which the threshold values are evenly distributed even in the minimum area aperture is preferred, and a Bayer dithered image in which the threshold values are completely distributed is particularly preferred.

In the 2-1 conversion circuit 23, the image data output from the latch circuit 14 is compared with the dither threshold value set in the dither matrix 22, and is converted into 2-1 data for each pixel.

Next, the image processing operation of the image processing apparatus 2 mentioned above will be described in detail, starting with the enlargement processing operation, with reference to FIG. 19 and subsequent figures. For convenience of explanation, the magnification rate M is 124/84 (
21.94) times.

FIG. 19 is an analog diagram of the relationship between original data and interpolated data, where D indicates the original data and S indicates the output data after interpolation.

The relationship between the image information level and the interpolated data at this time is as shown in FIG. Further, the relationship between the sampling pitch and the data selection signal SD during interpolation at this time is as shown in FIG.

The timing chart of the signals in each part during this interpolation process is shown in FIG. 20. Therefore, now the CCD6
The original image data obtained from 0 is DO(0),
D I(F), D2(F), D3(0), D4(0)(
The numbers in parentheses indicate the gradation level of each image data).
DI(F) is output from the latch circuit 11 in synchronization with the synchronous clock.
), but the latch circuit 12 outputs Do(0).

On the other hand, the data table shown in FIG. 15 is referred to based on the externally set magnification signal and the output of the counter circuit 15, and the data selection signal SD is 0, 8.0, 8.1.
,9.1,9. ... (Fig. 21E) is output, and the processing timing signal TD is 1, 1, 1 . ...(FIG. F) is output.

From the interpolation memory 13, the interpolation data table is referred to using the one-image data DO, DI and the data selection signal SD, and necessary interpolation data S (G in the figure) is output.

That is, since the data selection signal SD is 0 and 8 between the image data D 0 (0) and DI (F), O and 8 are output as the interpolation data SO and Sl.

Between image data DI(F) and 02(F), since the data selection total t'fSD is O and 8, F and F are output as interpolated data S2 and S3.

Between the image data D2(F) and D3(Q), since the data selection signal SD is 1 and 9, the interpolated data S
E and 7 are output as 4 and S5.

Since the selection means SD is 1 and 9 between the image data D3((1) and 04(Q)), 0 and O are output as the interpolation data S6 and S7.

Subsequent image data D5. Regarding DB, . . . , the interpolation data S is read in the same manner as described above.

Therefore, if the interpolated data is represented by an X mark, it can be seen that image data having a predetermined level between the original image data is interpolated and output as shown in FIG.

In this way, interpolated data 5O-37 is sequentially read out using the interpolation method with respect to actual image data DO-04,
These interpolated data S are sequentially sent to the latch circuit 14 (I in the same figure). On the other hand, the processing timing signal TD output from the latch circuit 17 is delayed by the latch circuit 18 by the time t (see Fig. 22). As described above, this delay time t is the time required for data access in the interpolated data memory 13, and is the time required for the latch circuit 14 to read the interpolated data S.

Since the on/off of the gate circuit 19 is controlled by the processing timing signal TD from the latch circuit 18, the latch circuit 14 performs a latch operation only when the gate circuit 19 is on, and does not perform a latch operation at other times. Not possible.

Next, the reduction process will be explained.

FIG. 21 is an analog diagram of an image signal in the case of reduction processing, and is image data DO.

DI, D2, D3,... are marked O,
Interpolated data 30, Sl, . . . are represented by X marks. FIG. 22 shows a timing chart of the signals at that time, and the original image data D used at that time.
The relationship between and interpolated data S is as shown in FIG. 12, and the relationship between data selection signal SD is as shown in FIG. 15. Note that the reduction ratio M illustrated here is 33/64 (-0, 52), and the gradation level of one image data is the same as in the case of the enlargement process described above.

Two adjacent image data (
For example, image data 1)1. DCI) is the address -;
- is supplied to the interpolation memory 13, and the reduction magnification (33/84) set externally is supplied to the interpolation data selection memory 1
The fact that the synchronous clock CLK2 is further counted by the counter circuit 15 is the same as in the case of the enlargement process described in 1-1.

As is clear from FIGS. 15 and 16, the data selection signal SD from the selection memory 16 is 0. Thursday; F9
Book; book, tree, E, O, ...... is output, and the processing timing signal TD is 1.0, 1, 0, 0.0,
1. ... is output. However, since the tree is invalid data, O data is stored in the interpolation data selection memory 16.

Therefore, interpolated data S as shown in FIG. 21 is read out from the interpolated data memory 13.

That is, since the data selection signal SD is equal to O between one image data D0(0) and DI(F), only O is output as interpolation data 5 (=SO).

Between the image data DI(F) and 02(F), since the data selection signal SD is equal to F, the interpolated data S1
0 image data 2(F) and 03 where F is output as
(G), since the data selection signals SD are both trees, no interpolated data S is output.0 image data D between 3(0) and D4(0), the selection data SD is Since E is a tree, only O is output as interpolation data S2.

Subsequent image data D4. D5. . . . -, the interpolation data S is read in the same manner as described above.

In this way, the actual image data Do, DI.

By obtaining data for . . . by the interpolation method, interpolated data SO, Sl, . Ru.

On the other hand, the processing timing signal TD is 0,1,0°0.0
．． 1... (Figure F), gate circuit 1
Since the old clock output from 9 is as shown in FIG. 22H, certain data are thinned out and the interpolated data S
O, Sl, . . . are output (FIG. 1).

As mentioned above, when reducing the size, new image data is inserted between the original pixels of the original image information and that image data is output, and some of the image data of the original pixels is thinned out or left as is. These output image data are generally referred to as interpolated data.

1- In the embodiment described above, if the magnification of enlargement or reduction is changed, the data selection signal SD output from the selection memory 16 for interpolation data changes, and the memory 13 for interpolation data is addressed accordingly. It will be clear that interpolated data S is output.

Now, the image data that has been subjected to the enlargement/reduction processing and the z-value processing is supplied to the output buffer circuit 90, but in this output buffer circuit 90, based on external specified data such as the enlargement/reduction magnification, The starting address for data loading or reading from the line memory provided in the output buffer circuit 90 is controlled.

First, the reason for controlling the write or read start address according to the specified magnification is explained in Figures 23 and 24.
This will be explained with reference to J.

For example, if the maximum image reading size of the CCD 60 is 84 format and the resolution is 18 dots/layer,
Image data for one line? Considering that the zero magnification is up to 2 times, which is 4096 bits, a line memory with a capacity of 8192 bits as shown in FIG. 23 is prepared as a line memory for storing one image data.

Then, the recorded result is the center (2048 bits 11)
Image data is written so that it becomes gano1 (pei),
It may be read out.

Therefore, when reducing an image by, for example, 1/2, the line memory write start address is 40.
Since the address corresponding to 1/4 of 96 bits (1024th address) will be set, in that case the reduced image data will be written to the line memory in the state shown in Figure 23A. .

On the other hand, the read start address is set to the O address. Therefore, a reduced image is recorded as shown in FIG. 24A.

This is because one image data is 0'' from the O address to the 1023rd address, so that period is considered white and recorded on the recording paper, and recording based on the reduced image data starts from the 1024th address. Because it will be.

For example, when the reduction ratio is 32/84, reduced image data is written from 1024 addresses. Similarly 33/64
When the reduction rate is 992 addresses, 34
When the reduction ratio is /64, data will be written starting from 960 addresses.

In this way, if the image data is old so that the result is in the center and the O address is set to jl'MP- for reading, the image will be recorded with the center edge of the recording paper 53 as a reference.

For this reason, the preoccupation start address when shrinking is
The settings are as follows.

, η-inclusive start address=(409B-4098X reduction magnification)/2 When enlarging an image, one image data increases, so the readout start address is controlled in the opposite way to when reducing.

If the maximum magnification is 2x, the image data at that time will be twice the image data at the same magnification.

In that case, the area of the recorded image will be quadrupled, so even if you try to double the size of a B4'F4 original, if the maximum size of the recording paper is up to 84, the enlarged image will be It is not possible to record everything on paper.

Taking this into consideration, it is possible to obtain a more natural enlarged image by limiting the processing results to the central portion of the document to be recorded, depending on the maximum size of the recording paper.

Therefore, when enlarging an image, as shown in FIG. 23B, 172 data (corresponding to the position of the center edge of the enlarged image) of the enlarged image data amount is 7! Accordingly, a total of 4096 bits, 2048 bits before and after, are read out.

Therefore, when the enlargement ratio is 12B/84, among the enlarged image data, the first data to the 2047 bit 11 data are ignored, and reading to the line memory starts from the 2048 bit 11 data, and from this a total of 4096 Bit image data will be read out.

On the other hand, the write start address is set to "O"'' address.

Similarly, when the enlargement ratio is 127/84, reading starts from 2016 bits 11, and when the enlargement ratio is 124/84, reading starts from the 1984th bit, and from this, a total of 4096 bits of image data is read out. It will be.

It goes without saying that even if other magnification ratios are set, the image data from the readout start address will be selected according to that magnification ratio.For this reason, the readout start address during enlargement should be set as follows. It is something that will be done.

Reading start address = (4098X enlargement magnification - 4098)/2 Putting it all together, the writing and reading start addresses at the time of enlargement/reduction are set as shown in FIG.

The following is an example of setting the fill-in or read-out start address when an image is processed with the center as a reference.

Next, an example of controlling a write or read start address necessary for reading image data only in a designated area and recording an enlarged/reduced image at a designated recording position will be described.

FIG. 26 is an explanatory diagram of recording position designation, and for convenience of explanation, the diagram is an explanatory diagram when enlarging an image, but it goes without saying that it can also be applied to the case of image reduction.

First, the image area to be read is nl - n4.

The recorded image areas resulting from the enlargement/reduction are Ml to N4, and the coordinates located on the diagonal line E of the image areas n1-n4 are as follows:
(xi, yl), (x2, y2).Similarly, among the coordinates located on the diagonal 1- of the recorded image area N1-N4, the minimum coordinate is (x3.y3).
The reference point (′
11 The above-mentioned coordinates in the main scanning direction (mizumo scanning direction) and the sub-scanning direction (horizontal scanning direction) from the edge of the draft 52 (referring to the point (x, y) = (0, 0)) As shown in the diagram, the number of data and lines up to IO.

When the 0 image area nl-n4 is specified as II, LO, and Ll, the input image data is changed to 0 by the switch changeover circuit 25 shown in Fig. 1θ.
(white information) is controlled by the timing generation circuit IO.

Figures A and C are examples of If > IO, and Figure B
and D is II (an example of IO).

It) The case of IO will be explained.

When the recording density is 16 dots/layer as described above, IO,It is.

(2) 0=16*xl 11=16*x3 Here, if the specified magnification is m, the image data of process 0 increases to m@IO.

On the other hand, since 11 is as described above, the relationship between them can be illustrated as shown in FIG. 27.

Also, when trying to record the image area nl, the IO
As mentioned above, the data is 0 data (white information),
Furthermore, the data Il in the recording area Nl is O data in which nothing is recorded.

Now, since the example shown in FIG. 27 is II) mΦIO, if the enlarged image data is directly loaded into the line memory and read out, then the horizontal recording start point x
3, the enlarged image data m·(x2-xi) in the original image area nl is recorded and is recorded off the designated recording start point.

In order to prevent this from happening, it is necessary to control the start point of inputting the enlarged image data into the line memory. That is, in such a case, as shown in FIG.
Since the difference between me IO and me IO becomes the deviation of the recording start point, the enlarged image data should be stored in the line memory from riAO to the extent that this difference is taken into account.

In this way, the address A1 where the designated image data is written becomes as shown in FIG. 30.

The number of data up to address A1 corresponds to It, which immediately corresponds to water coordinate x3 in the recording coordinate system.

Therefore, when II>IO and II)me IO, the enlarged image data is 1! from the address of AO=II-m・IO ]1. ; included;
Its reading is from the O address. In addition, as will be described later, the reline memory is cleared with O data (white information) using the period when no enlargement/reduction processing is being performed, so from the 0 address to the AO address, '0 ``Data is occupied when II <lo-t', m-lo>It.

As is clear from FIGS. 29 and 30, the enlarged image data is occupied from the O address, whereas the image data is read from the read address corresponding to AO=m111O-11. .

By doing this, even in the case of m@IO)II, the image will be correctly recorded from the set horizontal coordinate point x3.

In this way, by setting the write or read start address for the line memory, it becomes possible to horizontally move the image recording position.

The movement of the image recording position in the vertical direction is realized by controlling the operation timing, such as by advancing the reading start of the image reading device 2250 or the reading start of the output device 65.

To show only the results, when Ll > LO, To = (Ll - m - LO) - The output device 65 is started by the main scanning time from the normal time. I:,
The scanning time refers to the time required to scan one line in the 1-mi scanning direction.

When Ll<LO.

TO=(mFist LO-Ll)" The image reading device m50 is started earlier than normal by the main scanning time.

In addition to selecting the operation timing in this way.

By selecting the above-mentioned 517 inclusion and read address, it is possible to correctly record the enlarged/reduced image Nl-N4 at the preset recording position 21 (x3°y3).

FIG. 26 shows an example of enlarging an image.
] The above-mentioned operation can be performed by moving only the recording position in isometric processing (m = 1.0), or by recording by moving only the recording position (m = 1.0), or by reducing processing (m (1, 0)
) It goes without saying that this method can also be applied to the case where an image is recorded at L.

Now, FIGS. 31 and 31 are circuit diagrams showing an example for realizing the above-described image recording operation based on the central reference or the image recording operation based on recording position designation.

FIG. 31 shows an example of the output buffer 7 circuit 9o.

The output buffer circuit 90 includes a pair of line memories 100.
101 are provided, each of which is supplied with image data for one line. The reason for providing the pair of line memories Zoo and 101 is to alternately supply 1947 worth of image data so that one frame of image data can be loaded and read out in real time. Line memory 100, 10
1 has a capacity of 8192 bits as described above.

Writing and reading to and from the line memories 100 and 101 when recording an image with the center as a reference is controlled as follows.

First, when loading data into the line memory, an interrupt clock generated in the image processing circuit 2 is used.
Since the read clocks for the output device 65 are used during reading, these clocks are used as the first clock for clock selection.
and a second switch 102.103 to each address counter 104.105.

The first and second switches 102, 103 are complementary controlled so that when one line memory is in the aging mode, the other line memory is in the read mode. The switch control for this is the control circuit 10.
The water cycle control signal output from 7 (32nd
Figure C) is used.

The address counters 104 and 105 are further supplied with four address data for determining the S-load start address and read address for the line memories too and 101 via third and fourth switches 108 and 109, respectively.

The third and fourth switches 108 and 109 are also controlled in a complementary manner so that when one address counter is in the write mode, the other address counter is in the read mode. ，
109 is also supplied with a water cycle control signal as shown in FIG. 32C.

The write start address or read start address is preset in the address counter 104 or 105 in synchronization with the horizontal synchronizing signal (FIG. 32A). CPU80
The write or read address of F, generated by
08°109.

Line memory 100. After one of the outputs from the lot is selected by the fifth switch 110, it is supplied to the above-mentioned output "J 2165" and the 1-image memory 64.
Since the switch 110 is used to select image data in the read mode, a signal having an opposite phase to the control signal shown in FIG. 32C is used.

Now, the sixth switch 140 is turned off on the data supply line of the pair of line memories Zoo, 101, and 1 original image data and 0 data (corresponding to white information) are selected. This is line memory 100. This data is for clearing the lot, and is selected when the document is not being read.

In the case of recording position specification mode, in addition to inputting the coordinate data of coordinates (xi, yl) and (X2, y2) indicating the read image area, the coordinate (x
3. y3) and designated times *m are input from the operation/display section 75.

Inputting these data can be done by manually inputting the keys directly by the operator as described above, or by placing the original 52 on the pointing device L such as a tablet, directly specifying the position, and reading the coordinates using the CPU 80. It may be possible to do so.

Even if the keys are manually operated, each coordinate may be specified by inserting the document 52 into a transparent holder on which f4 lines are formed vertically and horizontally at a predetermined pitch.

By using such a transparent holder, the coordinates can be read quickly.

Addresses are calculated from each of the above-mentioned input data (a ROM table in which the addresses are stored may be used), and the loading and reading addresses for the line memory Zoo, 101 are selected in a predetermined manner. At the same time, speed control data is calculated and is used for image reading 'A150.
By supplying the image data to a drive motor attached to the drive motor, the reading speed is regulated according to the designated magnification, and an image reading start signal is supplied.

A recording start signal corresponding to the designated magnification and recording position is also supplied to the output device 65.

Incidentally, in the above description, the invention is applied to an image processing apparatus that reads an image with reference to the center of a1t4 and records the image using the center of recording paper as a reference, but the present invention can also be applied to other image processing apparatuses. can do.

First, when both image reading and image recording are processed based on one side of the original (recording paper),
Since the image reading start position of C0D56.57 and the recording start position (in the case of a laser printer, the recording beam start position δ of the laser beam) are the same, this civilization can be applied without any problem.

Second, in an image processing apparatus of the type in which one image is read based on the center line of the document and image recording is processed based on one side of the recording paper, writing to the output buffer circuit 90 and the start address are It will look like this:

In this case, the write start address to the line memories 100 and 101 is always the O address.

On the other hand, the readout start address cannot be determined only by the magnification signal and differs depending on the size of the document.

Therefore, in this type of image processing apparatus, the readout start address is determined from a signal indicating the document size and the magnification.

As shown in FIG. 33, the case where the size of the original 52 to be read is 44 size is shown below.

As mentioned above, when it is 18dots/ms.

What is the number of bits for the width of 44 format?

210m*X 18dotg/ms+=336
Since it is 0 bit, if the maximum read original size is 84 size, the value obtained by multiplying the width Y in FIG. 33 by the magnification becomes the read start address for the line memory.

Therefore, the read start address at the same magnification is:

(4098-3380) / 2 = 388 bits.

Figure 34 shows the values of the old and starting addresses at a magnification of 1:i, provided that the original size is 4th size.

Thirdly, in an image processing apparatus of the type in which image reading is performed on one side as shown in FIG. Writing to the circuit 90 and the starting address are determined as follows.

In this case, the maximum number of bits for 4th format (3360 bits) and the maximum number of bits for 84 format (4096
The preemption start address is determined from the bit). That is, 1-inch start address = (409111-3380X magnification)/2. At this time, the read start address is 0 address.

When the write start address becomes negative (during expansion), its (li becomes the value of the read start address. Therefore,
The write start address at this time is the O address.

FIG. 36 shows the values of write and read start addresses at arbitrary magnifications.

In this way, the filling or reading start address can be changed depending on the document reading or filling reference position. Further, the line memory 100 and the starting address for loading into the lot may be changed depending on the paper size of the recording paper.

Note that in the embodiment described above, the present invention was applied to a simple color copying machine, but when applied to a color copying machine that can record color images in many colors, the colors that can be specified may also be different. Needless to say, the number will increase accordingly.

In addition, in J: description, the expansion ψ reduction ratio is changed from 128/84 to 3
Under the condition that it is possible to select in 1/64 increments up to 3/84, the frequency of the synchronization clock CLK2 obtained by the timing generation circuit 10 is twice that of the reference synchronization clock, but this frequency is the maximum This is determined by the magnification rate.

For example, when the maximum enlargement rate is selected to be three times, the frequency of the synchronization clock CLK2 is set to three times the frequency of the reference synchronization clock. Therefore, the frequency of the synchronization clock CLK2 is changed depending on the maximum enlargement ratio used.

The memories 13 and 16 may use RAM instead of ROM, and the memory 13 may use an arithmetic circuit instead.

[9. Brightness Effect] As explained above, in this invention, image processing such as enlargement/reduction is performed before multilevel conversion, so that the quality of the recorded image does not deteriorate significantly depending on the magnification. do not have.

Further, since color separation is performed on the enlarged/reduced moe, color separation processing can be performed correctly regardless of the small magnification of the enlarged number line. Therefore.

There is no need to change color separation characteristics depending on the magnification.
Further, even if color separation is performed using a single color separation map regardless of the magnification, the color separation characteristics will not deteriorate.

Further, since the darkness value data for multi-value conversion is selected according to the density of the original 52, it is possible to record an image with the optimum density.

When controlling the output buffer circuit 90 and the like according to the enlargement/reduction magnification, it is possible to record an enlarged and reduced image at any designated position. Therefore, the image of the area desired by the operator can be placed at the desired position on the recording paper.
It has the feature of being able to record images of desired size and color.

Of course, in this invention, since the writing or reading start address to the line memory is controlled according to the magnification, the same effect as when enlarging/reducing is performed with the center on the reading side as the reference point can be obtained. Once obtained, the center of the recording paper will be used as the basis for recording.

As a result, there is no risk that the reduced image will be recorded unevenly or that the image will be recorded outside the transfer area of the recording paper, and even when the image is enlarged, there is no risk that it will be enlarged to the margins, so the required image It has characteristics such as being able to record correctly.

Furthermore, since the present invention obtains interpolated data while referring to a data table, it has remarkable effects such as better image quality and faster processing than conventional methods.

[Brief explanation of drawings]

FIG. 1 is a system diagram showing an overview of an image processing device that can be enlarged and reduced according to the present invention, FIG. 2 is a system diagram showing an example of an image reading device, and FIG. 3 is a waveform diagram for explaining its operation.
FIG. 4 is a system diagram showing an example of a color separation circuit and a color selection circuit; FIG. 5 is an explanatory diagram showing an example of an image forming process;
FIG. 6 is a configuration diagram showing an example of a simplified electrophotographic color copying machine, FIGS. 7 and 8 are diagrams for explaining color separation,
FIG. 9 is a diagram showing an example of a color separation map, FIG. 10 is a system diagram showing an example of an image processing circuit, FIGS. 11 and 12 are diagrams showing an example of interpolation data used when enlarging an image, Figures 13 and 14 are diagrams showing the relationship between the repetition period used when enlarging an image and the data selection signal at that time.
Figures 5 and 16 are diagrams showing the relationship between the repetition period and data selection signal used when reducing an image, Figure 17 is a diagram showing an example of threshold data used for line drawings, and Figure 18 is a diagram showing the relationship between the repetition period and data selection signal used for image reduction. A diagram showing an example of the threshold value data matrix used, FIG. 19 is a signal waveform diagram for explaining the image enlargement processing operation, FIG. 20 is a timing chart at that time, and FIG.
The figure is a signal waveform diagram for explaining the image reduction processing operation.
Figure 2 is a timing chart at that time, Figure 23 is a diagram explaining the line memory, Figure 24 is an illustration of recorded images, and Figures 25, 34, and 36 are -7 loading and reading start, respectively. Figure 26 is a diagram showing an example of an address, Figure 26 is an explanatory diagram of the recording position and designation, Figures 27 to 30 are diagrams used to explain its operation, Figure 31 is a system diagram showing an example of an output buffer circuit, The figure is a waveform diagram to explain its operation, Figures 33 and 35 are diagrams showing other examples of image reading and image recording, and Figure 37 is the main part of a conventional image processing device with 0 enlargement/reduction. FIG. 38 is a waveform diagram to explain the operation, FIG. 39 is an explanatory diagram of recording position designation, and FIG. 40 is an explanatory diagram of an example of recording using a dither image. 2... Image processing circuit 10... Timing signal generation circuit 13... Interpolation data memory 16... Interpolation data selection memory 22... Dither matrix 23... Binarization circuit 50... Image reading Device 60... Image reading f-stage (CCD) 65... Output device 70... Sequence control circuit 75... Operation/display unit 90... Output buffer circuit D... Image data S... Interpolated data SD...Data selection signal CLK2...Periodic clock TD...Processing timing signal PE...Control signal Patent applicant Konishi Roku Photo Industry Co., Ltd. Figure 1'i Data selection signal 1 voice i) □ Figure 12 → Number of steps +8 +7 +8 +9 +A +B +
G +D +E +F Tada Shichimori 13 Contents Arc MfRM No. 5υ th AORS +O+1 +2 +3 +4 +5 +8 Data selection memory 11 +7 +8 +9 +A +B
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[j! , Tsui] and 1 Figure 24 Buttons and leaves During tea ceremony Ii-chichi Figure 25 11 Figure 27 Figure 29 Figure 30 t-11-m-10+ m-IQ −-H Fig. 34 Figure 36 Figure 57 ゛(47 in 11-n) Figure 39 Eight B Figure 40 Menu

Claims (4)

[Claims] (1) An image reading device that separates image information into a plurality of color separation images and converts these plurality of color separation images into image signals, and a color separation means that performs color separation based on the image signal from the image reading device. , the multiple color signals obtained from the color separation means described above are used to enlarge and
An image processing circuit capable of scaling up and down, characterized by comprising an image processing circuit that performs scaling down, and a multi-value conversion circuit that performs multi-level conversion processing on color signals that have been expanded/reduced based on threshold values set for each color signal. Color image processing device. (2) The color image processing apparatus according to claim 1, wherein the threshold value set for each color signal can be set externally. (3) The color image processing apparatus according to claim 1, wherein the threshold value set for each color signal is automatically set according to the density of image information. (4) The color image processing apparatus according to any one of claims 1 to 3, wherein a dithered image is used as the multivalued image.