JPH0750915B2 - Image processing device that can be enlarged / reduced - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scalable image processing apparatus having an input / output buffer adapted to scale an original image using data interpolation.

[Background of the Invention] In an image recording apparatus capable of enlarging / reducing an original image, when a photoelectric conversion element such as a CCD is used as an image reading unit, the pixel data of the original image read by the photoelectric conversion element is used. In general, an image signal that has been enlarged / reduced is obtained by increasing or reducing appropriate image data according to the enlargement / reduction ratio.

FIG. 46 is a block diagram of essential parts showing an example of a processing system for executing enlargement / reduction used in such an image processing apparatus.

In the figure, numeral 40 is a memory for image data, and the image data D read by the image reading means is supplied to the input terminal 41 after being enlarged / reduced. The output image data obtained at the output terminal 42 is supplied to a recording device or the like to reproduce an enlarged / reduced image.

When enlarging or reducing, the amount of image data to the memory 40 is limited by the recording width of the recording device. In that case, the generation timing of the address generator 47 for the memory 40 is controlled according to the enlargement or reduction. To be done.

Therefore, the presettable first and second counters 4
3, 44 are provided, and when the clock CK (Fig. 47C) of a predetermined frequency is counted up to the preset values P1, P2, respectively, the first and second output pulses C1, C2 are generated (Fig. 47). D,
E).

By setting the flip-flop 45 with the first output pulse C1 and resetting it with the second output pulse C2,
The window pulse WP shown in FIG. This window pulse WP is supplied to the gate circuit 46 as a gate pulse, and the clock CK is supplied to the address generator 47 by the width W1 of the window pulse WP. However, this clock
CK is a clock synchronized with the enlarged / reduced image data.

As a result, since the address data for the memory 40 is generated only during the period W1, the horizontal effective area signal H-VALI of FIG. 47A is generated.
Of the image data regulated by D (B in the figure), the period W
The image data corresponding to 1 is written in the memory 40 (G in the figure).

Therefore, if the preset values P1 and P2 are changed according to the enlargement / reduction ratio, the width W1 of the window pulse WP changes according to this change, which limits the amount of image data written in the memory 40. It

In the case of reduction, the window pulse WP and the horizontal effective area signal H-VALID have the same width and are processed.

On the other hand, in the case of enlargement, the number of image data increases, so that the horizontal effective area signal H-VALI
The width of the window pulse WP is made narrower than the width of D to reduce the number of data.

[Problems to be Solved by the Invention] In the conventional image processing apparatus having the enlargement / reduction processing function described above, the following problems occur.

That is, in the configuration shown in FIG. 46, although the amount of image data to be written in the memory 40 is limited according to the magnification of enlargement / reduction, the write address is always the first address (0 Since the address is designated, when the image reading or image recording is applied to an image processing apparatus in which the center of a document (recording paper) is used as a reference, the image may be recorded depending on the magnification. The desired image may be located outside the transfer area of the recording paper.

For example, as shown in FIG. 48, when W is the maximum reading width of the image reading means (equal to the horizontal effective area width),
When the image data of the original 52 is read with the center line 1 of the original placing table 51 as a reference and an image is recorded with this center line 1 as a reference, at the same magnification, it is recorded as shown in FIG. 49B. However, at the time of reduction, it is recorded as shown in FIG.

This is because the first write address in the memory 40, that is, the 0 address corresponds to the write start position of the output device (recording device such as a laser printer). Therefore, when the size of the recording paper P to be recorded is small, it may be outside the transfer area of the recording paper, and in that case, the reduced image cannot be correctly recorded on the recording paper.

Even when the size of the recording paper P is large, there is a drawback in that the reduced image is packed and recorded at the edge of the recording paper P.

Further, during the enlargement processing, the margin portion of the original document is also enlarged, and as a result, it is enlarged as shown in FIG. 49C. Therefore, there is a possibility that an image in the required range cannot be recorded on the predetermined recording paper P.

Therefore, the present invention solves the above-mentioned conventional problems, and an image to be recorded is recorded with reference to the center of the recording paper when the image is enlarged or reduced, particularly when the image is reduced. The present invention proposes an image processing device capable of enlarging / reducing.

[Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention is capable of enlarging / reducing an image by using image data read by photoelectrically converting image information. In the image processing apparatus, an input buffer and an output buffer for the image data are provided, the write start address to the output buffer is changed in accordance with the reduction processing during the reduction processing, and the input buffer to the input buffer is changed during the enlargement processing. The writing start timing is changed according to the enlargement processing.

[Operation] The write start address to the output buffer is changed according to the magnification (especially when reducing the image) and the recording paper size.

In this way, the write start address changes according to the magnification, so that it is equivalent to outputting "0" data (data corresponding to white) from the 0 address to this write start address.

Here, the write start address is set so that the reduced image is recorded with the center of the recording paper as a reference.

[Embodiment] An example of an image processing apparatus capable of enlarging / reducing according to the present invention will be described with reference to FIG. A detailed description will be given with reference.

However, the following embodiments are applied to a color image processing apparatus using an electrophotographic color copying machine as an output device.

Therefore, first, a schematic configuration of such a color image processing apparatus to which the present invention is applied will be described with reference to FIG.

Image information such as a document is converted into an image signal by the image reading device 50, and then subjected to A / D conversion processing, shading correction processing, color separation processing, and other image processing, so that a predetermined bit corresponding to each color signal is obtained. Number of image data,
For example, it is converted into image data of 16 gradations (0 to F).

In the enlarging / reducing circuit 2, each image data is subjected to image processing such as enlarging / reducing based on the linear interpolation method. In this case, the interpolation data used as the image data after the enlargement / reduction processing is stored in the interpolation table (interpolation ROM), and as the signal for selecting this interpolation data,
The image data before the enlargement / reduction processing and the interpolation selection data stored in the data ROM are used. The required interpolation selection data is selected based on a command from the system control circuit 80 according to the designation of the magnification.

The image data after the image processing is supplied to the output device 65, and the image is recorded at the magnification set externally. As the output device 65, an electrophotographic color copying machine can be used.

The image reading device 50 is provided with a drive motor for driving image reading means such as a CCD and an exposure lamp, which are controlled at a predetermined timing by a command signal from the sequence control circuit 70. Data from a position sensor (particularly not shown) is input to the sequence control circuit 70.

On the operation / display unit 75, various input data such as magnification designation, recording position designation, recording color designation, etc. are input,
Its contents are displayed. An element such as an LED is used as the display means.

The system control circuit 80 controls the above-mentioned various controls, the control of the entire image processing apparatus, the management of the state, and the like. Therefore, microcomputer control is suitable for this system control.

The figure shows an example of microcomputer control. Necessary image processing data and control data are exchanged by the system bus 81 between the control circuit 80 and the various circuit systems described above.

An image reading start signal, a start signal for shading correction, a recording color designation signal, and the like are supplied to the image reading device 50 via the system bus 81.

For the enlarging / reducing circuit 2, threshold value selection data for selecting a threshold value for binarizing the image data according to the magnification data designated by the operation / display unit 75 and the type and density of the image to be recorded. Are supplied to the control circuit 80 and then supplied via the system bus 81.

To the output device 65, a start signal for recording an image, a recording paper size selection signal, and the like are supplied.

Next, these components will be described in detail.

For convenience of description, first, an example of the configuration of a simple color copying machine applicable to the present invention will be described with reference to FIG.

The color copying machine shown in the figure is intended to record a color image by separating color information into about three types of color information. In this example, three types of color information to be separated are black BK and red R.
And blue B are illustrated.

In FIG. 13, reference numeral 200 is an example of a main part of a color copying machine, 201 is a drum-shaped image forming body, on the surface of which a photoconductive photoreceptor surface layer such as selenium Se is formed, and an optical image is formed. The electrostatic image (electrostatic latent image) corresponding to is formed.

On the peripheral surface of the image forming body 201, members described below are sequentially arranged in the rotation direction thereof.

The surface of the image forming body 201 is uniformly charged by the charger 202, and then the surface thereof is uniformly exposed by the exposure lamp 203 with weak light. Image exposure based on each color separation image (the optical image is
Is shown).

After the image exposure, it is developed by a predetermined developing device. The developing devices are arranged by the number corresponding to the color separation image. In this example, the developing device 205 filled with the developer of red toner, the developing device 206 filled with the developer of blue toner, and the developing device 207 filled with the developer of black toner are They are arranged in this order in the order of rotation in the direction of rotation of the forming body 201 so as to face the surface of the image forming body 201.

The developing devices 205 to 207 are sequentially selected in synchronization with the rotation of the image forming body 201. For example, when the developing device 207 is selected, toner is attached to the electrostatic image based on the black color separation image, and thus the black color is obtained. The decomposed image is developed.

A pre-transfer charger 209 and a pre-transfer exposure lamp 21 are provided on the developing device 207 side.
0 is provided, and a color image is recorded on the recording medium P by these.
It is easy to transfer to. However, the pre-transfer charger 209 and the pre-transfer exposure lamp 210 are provided as necessary.

The color image or the monochrome image developed on the image forming body 201 is transferred onto the recording body P by the transfer unit 211. The transferred recording material P is subjected to a fixing process by the fixing device 212 in the subsequent stage, and then discharged.

It should be noted that the static eliminator 213 is composed of one or both of a static elimination lamp and a static elimination corona discharger.

The cleaning device 214 is composed of a cleaning blade or a fur brush, and is configured to remove the residual toner adhering to the drum surface after the color image of the image forming body 201 is transferred.

It is well known that this removing operation is performed so as to separate from the surface of the image forming body 201 by the time the surface on which the development is performed reaches.

As the charger 202, a scorotron corona discharger or the like can be used. This is because the influence of the previous charging is small and stable charging can be applied to the image forming body 201.

Image exposure obtained by a laser beam scanner can be used as the image exposure 204. This is because a laser beam scanner can record a clear color image.

For at least the second and subsequent developments that are repeated to superimpose the color toner images on each other, the image forming member formed by the previous development is used.
It is necessary to prevent the toner adhering to 201 from being displaced in the subsequent development. In that sense, such development is preferably performed by non-contact jumping development.

FIG. 13 shows a developing device of the type that develops by such non-contact jumping.

A so-called two-component developer is preferably used as the developer. This is because the two-component developer has a clear color and the toner charge control is easy.

FIG. 2 shows an example of the image reading device 50.

In the figure, the color image information (optical image) of the original 52 is separated into two color separated images by the dichroic mirror 55. In this example, the color separation image of red R and the color separation image of cyan Cy are separated. Therefore, the dichroic mirror
The cutoff of 55 is about 600 nm. As a result, the red component becomes transmitted light and the cyan component becomes reflected light.

The color-separated images of red R and cyan Cy are supplied to image reading means 56 and 57 such as CCD, and the image signals of only the red component R and cyan component Cy are output from the respective image reading means 56 and 57.

FIG. 3 shows the relationship between the image signals R and Cy and various timing signals. The horizontal effective area signal H-VALID (C in the same figure) is CCD5.
Corresponding to the maximum document reading width W of 6,57 (see Fig. 48),
The image signals R and Cy shown in F and G of FIG.
(E in the same figure) is read in synchronization with.

These image signals R and Cy are input to A through the amplifiers 58 and 59 for normalization.
By being supplied to the / D converters 60 and 61, they are converted into digital signals having a predetermined number of bits.

This digital image signal is shading corrected. 63,6
Reference numeral 4 denotes a shading correction circuit having the same configuration. A specific example will be described later.

The shading-corrected digital color image signal is supplied to the color separation circuit 150 at the next stage and separated into a plurality of color signals necessary for color image recording.

In the above example, the color recording device records the color image with three colors of red R, blue B, and black BK, so the color separation circuit 150 separates the color signals R, B, and BK of these three colors. Will be done. A specific example of color separation will be described later.

One of the color signals R, B, and BK is selected by the color selection circuit 160. This is because, as described above, the image forming processing process in which a color image of one color is developed per one rotation of the image forming body 201 is adopted, and in synchronization with the rotation of the image forming body 201. The developing devices 205 to 207 are selected, and the color signals corresponding to these are selected by the color selection circuit 16
It will be selected at 0.

Selection signals G1 to G3 for color signals are supplied to the terminal 170. The selection signals G1 to G3 are color signals to be output depending on three-color recording, that is, a normal color recording mode (multi-color mode) and single-color recording, that is, a color designation recording mode (mono-color mode). It is used to select a signal from the system control circuit 80.

The color separation processing for separating a color original into three color signals is executed every one rotation of the image forming body 201.
It may be executed only once during the preliminary rotation of 01.

Now, in an apparatus that irradiates an original with a lamp to collect reflected light with a lens and reads an image, a non-uniform light image called shading is obtained due to optical problems of the lamp, the lens, and the like.

In FIG. 4, the image data in the main scanning direction is V1, V2 ...
・ If Vn, the level is lowered at both ends in the main scanning direction. Therefore, in order to correct this, the shading correction circuits 63 and 64 perform the following processing.

In FIG. 4, VR is the maximum value of the image level, and V1 is the image level of the first bit when the white color of the reference white plate (not shown) of uniform density is read. Actually, assuming that the image level when the image is read is d1, the gradation level d1 ′ of the corrected image is as follows.

d1 ′ = d1 × VR / V1 The correction is performed for each image data of each pixel so that this correction formula is satisfied.

FIG. 5 shows an example of the shading correction circuit 63.

The first memory 66a configured by a RAM or the like is a memory for reading a normalization signal (shading correction data) for one line obtained when a white plate is illuminated.

The second memory 66b stores the first memory 66a during image reading.
The ROM is used to correct the image data based on the shading correction data stored in.

In the shading correction, first, the image data for one line obtained by scanning the white plate is stored in the first memory 66a. When reading the image of the original, the image data is the second
Of the memory 66b is supplied to the address terminals A0 to A5, and the shading correction data read from the first memory 66a is supplied to the address terminals A6 to A11. Therefore, the second memory 66b outputs the image data that has been subjected to the shading correction according to the above-described arithmetic expression.

The above-described color separation (color separation from two colors into three color signals) is performed based on the following idea.

FIG. 6 schematically shows the spectral reflection characteristics of a color chart of color components. FIG. 6A shows achromatic spectral reflection characteristics, FIG. 6B shows blue spectral reflection characteristics, and FIG. C indicates the spectral reflectance characteristics of red, respectively.

The horizontal axis represents wavelength (nm) and the vertical axis represents relative sensitivity (%). Therefore, the spectral characteristic of the dichroic mirror 55 is 600n.
If m, the red component R is transmitted and the cyan component Cy is reflected.

The level of the red signal R normalized with reference to white is VR,
When the level of the cyan signal Cy is VC, these signals V
A coordinate system is created from R and VC, and red, blue, and black color separation is performed based on the created color separation map. The following points must be taken into consideration when determining the coordinate axes.

I. In order to be able to express halftones, the concept of the reflectance (reflection density) of the original 52 corresponding to the luminance signal of the television signal is incorporated.

II. Introduce the concept of color difference (including hue and saturation) such as red and cyan.

Therefore, for example, the following may be used as the luminance signal information (for example, 5-bit digital signal) and the color difference signal information (also for 5-bit digital signal).

Luminance signal information = VR + VC (1) However, 0 ≦ VR ≦ 1.0 (2) 0 ≦ VC ≦ 1.0 (3) 0 ≦ VR + VC ≦ 2.0 (4) The sum of VR and VC (VR + VC) is from the black level (= 0). Corresponding to the white level (= 2.0), all colors are in the range 0 to 2.0.

Color difference signal information = VR / (VR + VC) or VC / (VR + VC) (5) In the case of achromatic color, the ratio of the red level VR and the cyan level VC included in the overall level (VR + VC) is constant.
Therefore, VR / (VR + VC) = VC / (VR + VC) = 0.5 (6)

On the other hand, the ratio of chromatic colors is 0.5 <VR / (VR + VC) ≦ 1.0 for red colors (7) 0 ≦ VC / (VR + VC) <0.5 (8) For cyan colors, 0 ≦ VR / ( VR + VC) <0.5 (9) 0.5 <VC / (VR + VC) ≦ 1.0 (10)

Therefore, as the coordinate axes, (VR + VC) and VR / (VR + V)
C) or by using a coordinate system having (VR + VC) and VC / (VR + VC) as two axes, chromatic colors (red and cyan) and achromatic colors can be clearly separated only by level comparison processing.

In FIG. 7, the vertical axis represents the luminance signal component (VR + VC),
The horizontal axis shows the coordinate system when the color difference signal component VC / (VR + VC) is taken.

If VC / (VR + VC) is used as the color difference signal component,
The area smaller than 0.5 is red system R, and the area larger than 0.5 is cyan system Cy. An achromatic color exists in the vicinity of the color difference signal information = 0.5 and in the area with little luminance signal information.

FIG. 8 shows a specific example of a color separation map obtained by performing color classification according to such a color separation method. A ROM table is used for the color separation map, and the illustrated example shows an example in which the table is divided into 32 × 32 blocks. Therefore, as the number of address bits for this ROM table, the row address is 5 bits,
The column address uses 5 bits.

In this ROM table, the quantized density corresponding value obtained from the reflection density of the original 52 is stored.

FIG. 9 shows a color separation circuit for realizing such color separation.
3 is a systematic diagram of a main part showing an example of 150. FIG.

In the figure, terminals 150a and 150b are supplied with a red signal R and a cyan signal Cy before being color-separated into three colors.
At 151, processing such as gradation conversion and γ correction is executed.

The data after the arithmetic processing is used as an address signal for the memory 152 that stores the calculation result of (VR + VC) for obtaining the luminance signal data, and the calculation result of the color difference signal data VC / (VR + VC) is stored. Memory 153
Is used as an address signal for.

Each output of these memories 152 and 153 is a separate memory (ROM configuration)
It is used as an address signal of 154-156. Memory 154
156 uses a data table in which the data of the color separation map shown in FIG. 8 is stored for each color.

The memory 154 is for the black signal BK, the memory 155 is for the red signal R, and the memory 156 is for the blue signal B.

As is apparent from the color separation map shown in FIG. 8, by detecting the levels of the red signal R and the cyan signal Cy, three color signals R, red, blue, and black are detected from the color information signals of the color document. B and BK can be output separately.

From each of the memories 154 to 156, density data (4 bit structure) concerning each color signal and 2 bit structure color code data are simultaneously outputted.

The density data and color code data are combined in the latter stage of the synthesizer 15 respectively.
Synthesized at 7,158. The combined density and color code data is a ghost canceller (not shown)
And the ghost signal removal processing is performed.

Each data after the ghost removal is the color selection circuit 16 shown in FIG.
Supplied to 0.

The color code data supplied to the terminal 161 is the decoder 164
And the color code is decoded, and the decoded output is supplied to the OR circuits 166 to 169. Similarly, the color selection signals G1 to G3 supplied to the terminal 163 are transmitted to the decoder 1
The data contents are decoded at 65, and the decoded output is supplied to the plurality of OR circuits 166 to 169 described above, and any of the signals (all colors) including red to black and all of these colors is supplied. The color signal of can be selected.

Select signals for the color signals output from the OR circuits 166 to 169 are supplied to the density signal separation circuit 162 as density selection signals. The above-mentioned density data is supplied to the density signal separation circuit 162, and this density data is selected according to the above-mentioned select signal.

The selected density data is supplied to the enlarging / reducing circuit 2.

The color selection signals G1 to G3 correspond to the separated color signals, and in the normal color recording mode, three-phase gate signals G1 to G3 synchronized with the rotation of the image forming body 201 are formed (the eleventh part).
Figures GI). At the same time, the developing units 205 to 207 are also shown in FIG.
The developing bias indicated by E is supplied to each of the developing devices 205 to 207 in synchronization with the rotation of the image forming body 201.

As a result, the exposure and development processing steps are sequentially performed in the exposure processes I to III (FIG. F) for each color.

On the other hand, in the color designation recording mode, the designated single image forming process is performed.

Therefore, as shown in FIG. 12, three selection signals G1 to G3 are obtained in phase regardless of the designated color signal (G to G in FIG.
I). The example shown in FIG. 12 is when red is designated.

At the same time, the developing bias is supplied only to the corresponding developing unit 205 (D in the same figure), and this becomes the operating state. Therefore, since only the developing device 205 containing red toner (developer) is driven as the developing device, an image is recorded in red regardless of the color information of color development.

When the other color (black or blue) is designated, the image forming process is the same, and the detailed description thereof will be omitted.

FIG. 14 is a block diagram showing an example of the enlargement / reduction circuit 2.

In this example, it is possible to enlarge / reduce between 0.5 times and 2.0 times in 1.0% steps.

Here, also in principle in the present invention, the enlargement processing is an interpolation processing for increasing the image data and the reduction processing is an interpolation processing for thinning out the image data. Then, enlargement in the main scanning direction shown in FIG.
The reduction is performed by electrical signal processing, and the enlargement / reduction processing in the sub-scanning direction (rotational direction of the image forming body) is performed with the photoelectric conversion element provided in the image reading device with a constant exposure time. Alternatively, the moving speed of the image information is changed.

When the moving speed in the sub-scanning direction is slowed down, the original image is enlarged,
If it is faster, it will be reduced.

In FIG. 14, a timing signal generating circuit 10 is for obtaining a timing signal for controlling the processing timing of the entire enlarging / reducing circuit 2. For this purpose, as in the case of the CCDs 56, 57, the synchronization clock CLK1, Horizontal effective area signal H
-VALID, vertical effective range signal V-VALID and horizontal sync signal H
-SYNC is supplied.

Then, the timing signal generating circuit 10 first outputs the synchronous clock CLK2 which is output only during the period of the horizontal effective area signal H-VALID. This has the same frequency as the synchronization clock CLK1.

Further, a memory control signal INSE for the memories provided in the input buffer 400 and the output buffer 450, respectively.
L and OUTSEL are output.

The image data D having 16 gradation levels sent from the color selection circuit 160 for each color signal is supplied to the input buffer 400.

The input buffer 400 is provided for the following reason.

That is, first, since the number of image data used during the enlargement processing is larger than that before the processing, it is possible to effectively increase the processing speed after the data increase without increasing the frequency of the basic clock. This is because

Secondly, the enlarged image at the time of the enlargement processing is recorded with the center as a reference.

Therefore, since the first condition is satisfied during the enlargement processing, the frequency of the read clock RDCLK supplied to the input buffer 400 is made lower than the normal frequency. Then, since the second condition is satisfied, the read start address is set according to the magnification. The details will be described later.

Image data D output according to the specified enlargement / reduction magnification
Is supplied to two cascade-connected latch circuits 11 and 12, and image data D1 and D0 of two adjacent pixels among the image data D having a 4-bit structure, that is, the image data D output with a halftone level are latched. It is latched at the timing of clock DLCK. Latch clock DLCK is a synchronous clock
It has the same frequency as CLK1.

The image data D0 and D1 latched by the latch circuits 11 and 12 are used as address data for a memory 13 for interpolation data (using ROM, hereinafter referred to as interpolation ROM) 13.

The interpolation ROM 13 is an interpolation data table in which image data having a new halftone level referred to by two adjacent image data (hereinafter, this image data is referred to as interpolation data S) is stored.

As address data of the interpolation ROM 13, interpolation selection data SD is used in addition to the above-mentioned pair of latch data D0 and D1.

Reference numeral 300 is an interpolation data selection means that stores interpolation selection data SD and the like. As will be described later in detail, interpolation selection data
SD is used as address data for deciding which data in the data table group selected by the pair of latch data D0 and D1 is used as interpolation data.

The interpolation selection data SD is determined by a set magnification for enlarging / reducing as will be described later.

FIG. 15 shows an example of the interpolation data S selected by the latch data D0, D1 and the interpolation selection data SD.
In the embodiment, the interpolation data is obtained by linearly interpolating the data of D0 and D1.

In FIG. 15, S is interpolation data (4 bits) output at 16 gradation levels, and the image data D0 and D1 used as latch data each have 16 gradation levels. Contains 16 × 16 = 256 data blocks.

In the figure, when D0 = 0 and D1 = F, the theoretical value (five decimal places) by linear interpolation in each step and the value of the interpolation data S actually stored are shown for positive slope and negative slope, respectively. The case will be shown.

Actually, the interpolation data S is stored in the form as shown in FIG. However, this data is D0 = 4, D1 = 0 to F
This is an example of the case.

In FIG. 16, ADRS is a base address,
When D0 = 4, the relationship between the interpolation selection data SD (data 0 to F arranged in the horizontal direction) and the interpolation data S to be output when D1 takes a level from 0 to F is shown.
The sum of the address data ADRS and the value of the horizontal axis interpolation selection data SD is the actual address for the interpolation ROM 13.

Now, the interpolation data S output from the interpolation ROM 13 is latched by the latch circuit 14 and then supplied to the binarizing means 69, and binarization processing corresponding to the image data is performed.

The binarized “1” and “0” binary image data is supplied to the output buffer 450. The output buffer 450 is provided to process invalid data caused by reduction of image data when the image is reduced. Further, it is for enabling the reduced image to be recorded with the center of the recording paper P as a reference when the image is reduced.

The final binary data obtained from the output buffer 450 is supplied to the output device 65, and an image is recorded based on this binary data.

2 provided between the latch circuit 14 and the output buffer 450
An example of the value conversion means 69 will be described with reference to FIG. 14 again.

In the figure, the main scanning counter 20 is for counting the write clock LCK2 of the output buffer 450,
The sub-scanning counter 21 is for counting the horizontal synchronizing signal H-SYNC. The outputs of these counters 20, 21 address the threshold data in dither ROM 22. The specified predetermined threshold value data is supplied to the binarization circuit 23, whereby the interpolation data S is binarized with reference to the threshold value data.

Therefore, the binarization circuit 23 uses a digital comparison circuit.

As the threshold data, when the document to be read is a line drawing, data of a constant threshold corresponding to the density is used. Figure 17 shows an example. The threshold data in the figure is a hexadecimal display.

When the original 52 is a photographic image, it is preferable to use binarization by the dither method, and thus the dither matrix is used as the threshold data in this example.

As the dither matrix, depending on the density of the original 52,
In this example, three types of matrices (for example, 4 × 4 dither matrix) are prepared, and these are appropriately selected.

When the density of the original document 52 is low, the dither matrix shown in FIG. 18A is selected, when it is normal density, the dither matrix shown in FIG. 18B is selected, and when it is dark, the dither matrix shown in FIG.

The operator may manually select the threshold data used for a line drawing or the dither matrix used for a photographic image according to the density of the original 52, but it is convenient to automate it. In the case of automation, the density of the entire original 52 is detected, and an optimum dither matrix or the like is selected from the density based on a command from the control circuit 80.

Subsequently, specific examples of the respective units in the above-mentioned enlargement / reduction circuit 2 will be described below.

FIG. 19 shows an example of the input buffer 400.

The input buffer 400 is provided with a pair of line memories 401 and 402, each of which is supplied with image data D for one line. The pair of line memories 401 and 402 are provided in order to alternately supply image data for one line so that writing and reading of image data can be processed in real time.

As the line memories 401 and 402, those having a capacity of 4096 × 4 bits are used. This capacity is when the resolution is set to 16 dots / mm, and the maximum document size is B4 version (horizontal length is 25
6 mm).

Write clock when writing data to line memory
CLK2 is used and read clock RDCL
Since K is used, these clocks are supplied to the respective address counters 405 and 406 via the first and second switches 403 and 404 for clock selection.

The read clock RDCLK is set to a frequency different from the normal time when the enlargement ratio is specified. The frequency to be set depends on the designated magnification.

The first and second switches 403 and 404 are complementarily controlled so that when one line memory is in the write mode, the other line memory is in the read mode. The control signal INSEL generated by the timing signal generation circuit 10 is used as a switch control signal for that purpose.

In this case, one of them is phase-inverted and supplied by the inverter 409. The control signal INSEL is a rectangular wave signal having two horizontal periods as one period (see FIG. 33).

Here, even when the image is enlarged, the enlarged image is the recording paper P.
In order to perform recording with reference to the center of, the writing start timing is controlled according to the enlargement ratio during the enlargement processing. Therefore, the clock CLK2 is supplied to the first and second switches 403 and 404 via the clock output control circuit 410 including a gate circuit.

The preset data Po for controlling the write start timing is supplied to the control circuit 410.

The control circuit 410 counts the clock CLK2 and outputs the clock CLK2 when the value of the clock CLK2 matches the preset data Po. This limits the amount of data written to the input buffer 400, but a detailed description will be given later.

The outputs from the line memories 401 and 402 are supplied to the latch circuit 11 after any one of them is selected by the third switch 407. The control signal INSEL described above is used as the switching signal.

FIG. 20 shows an example of the output buffer 450. The configuration is almost the same as the input buffer 400, but since the image data after binarization is stored, the line memories 451 and 452 have 4096
× 1 bit is used.

Further, 453, 454 and 457 are first to third switches, 455 and 456 are address counters, and 459 is an inverter.

A signal OUTSEL (see FIG. 33) generated by the timing signal generation circuit 10 is used as a control signal for selecting a switch.

The frequency of the clock LCK2 is changed only when the reduction ratio is specified. The clock PCLK is a synchronous clock for the output device 65.

Address counters 455 and 456 are supplied with addressing data for setting their initial addresses. Therefore, as shown in the figure, the write start address data and the read start address data are stored in the fourth and fifth switches.
It is supplied to the respective counters 455 and 456 via 461 and 462.

In this case, the switch control signal OUTSEL is controlled so that the write start address data and the read start address data are alternately supplied for each line. The read start address is always designated as 0 address, and the write start address is automatically changed according to the magnification so that the reduced image is always recorded with the center as a reference. Details will be described later.

The write start address data and the read start address data are both supplied from the system control circuit 80.

Here, the processing operation of the input buffer 400 and the output buffer 450 will be described with reference to FIGS. 21 to 23.

FIG. 21 shows the processing operation at the time of equal magnification, and the frequency of the read clock RDCLK supplied to the input buffer 400 with respect to the synchronous clock CLK1 of FIG. A is the same as the frequency of the synchronous clock CLK1 (B of FIG. ). This makes the input buffer
The image data D shown in FIG. 6C is read from 400, and this is supplied as the address data of the interpolation ROM 13. As a result, the interpolation data S as shown in FIG. This interpolation data S is finally supplied to the output buffer 450 and temporarily stored.

In this case, the frequency of the write clock LCK2 supplied to the output buffer 450 is the same as the frequency of the synchronous clock CLK1.

On the other hand, FIG. 22 shows the processing operation when the magnification is set to 2.

When a magnification of 1x or more is set, input buffer 400
The frequency of only the read clock RDCLK is changed according to the set magnification.

When the magnification is set to 2 times, the synchronization clock of FIG.
The frequency of the read clock RDCLK supplied to the input buffer 400 with respect to CLK1 is reduced to 1/2 (B in the figure). As a result, the image data D shown in FIG. 6C is read from the input buffer 400 and supplied as the address data of the interpolation ROM 13. As a result, one interpolation data S is generated for one cycle of the synchronous clock CLK1 as shown in FIG.
Is obtained. This interpolation data S is supplied to the output buffer 450 and temporarily stored.

In this case, the frequency of the write clock CLK2 supplied to the output buffer 450 is the same as the frequency of the synchronous clock CLK1 (E in the figure).

As described above, even when a magnification of 1 or more is selected, the enlargement process is performed by lowering the frequency of the read clock RDCLK. Therefore, except for the clock RDCLK supplied to the input buffer 400, the basic clock remains unchanged. The processing operation is executed at.

Therefore, as the enlarging / reducing circuit 2, a circuit element having a high operating speed may not be used.

Of course, even in the input buffer 400, since the clock frequency thereof is lower than the clock frequency at the time of equal magnification, it is not necessary to use all the circuit elements of high speed operation.

At the time of reduction, for example, when reducing the image by 0.5 times,
As shown in the figure, the read clock RDCLK to the input buffer 400 is the same as the synchronous clock CLK1, but the frequency of the write clock LCK2 supplied to the output buffer 450 is dropped to 1/2. As a result, the writing timing of the interpolation data S becomes once every two cycles, so that extra image data is thinned out and stored in the output buffer 450.

Details of the enlargement / reduction processing operation will be described later.

Now, the interpolation data selection means 300 shown in FIG. 14 is composed of a data selection signal writing circuit 310 and a data selection memory 320. The data selection signal writing circuit 310 stores, for each block, an interpolation selection data SD determined by a scaling factor and a processing timing signal TD for performing control such that the interpolation selection data SD is output at a timing according to the scaling factor. Has been done.

Since the interpolation selection data SD has a large capacity, a large capacity ROM is used as the writing circuit 310. In this case, a dedicated ROM can be used, but a ROM for a control program included in the system control circuit 80 may be used.

The data selection memory 320 is the interpolation selection data writing circuit 310.
Interpolation selection data SD, processing timing signal TD stored in
Of these, it is used to write data SD and TD according to the magnification designation. Therefore, the interpolation selection data SD written in the data selection memory 320 is used as the interpolation selection data SD during the actual image processing.

From this, as the data selection memory 320,
Static that can write and read at high speed
RAM etc. are used.

The magnification designation data and the magnification set pulse DS are supplied to the writing circuit 310, respectively.

On the other hand, when writing the interpolation selection data SD and the processing timing signal TD to the data selection memory 320, the clock SETCLK on the writing circuit 310 side is used. Therefore, as shown in FIG. 14, the clock selection circuit 3 is provided on the data selection memory 320 side.
50 is provided to select the synchronous clock CLK2 and the write clock SETCLK from the write circuit 310.

The selected clock is counted by the counter 360, and its output is supplied as address data to the 12-bit address terminals A0 to A11 in the data selection memory 320.

Here, in counter 360, 4096 clocks (and therefore 409
A carry pulse is generated when counting 6 pixels of data).

The carry pulse is used as a transfer end signal (write end signal) CS (FIG. 25B).

FIG. 24 shows an example of the writing circuit 310.

In the figure, 311 is a data ROM, which is
The interpolation selection data SD and the processing timing signal TD as shown in FIG. 37 are stored.

Here, prior to image reading, the interpolation selection data SD, etc. stored in the writing circuit 310 is data based on the data set pulse (magnification set pulse) DS (Fig. 25A) after the magnification is specified from the outside. The data of the ROM 311 is transferred to the data selection memory 320.

The data set pulse DS is the control circuit shown in Fig. 24.
It is supplied to 313 and the control signal ES for write enable shown in FIG. 25C is generated.

The control signal ES is supplied to the counter 314, and the count state of the clock SETCLK from the oscillation circuit 315 supplied to the counter 314 is controlled (FIGS. 25D and E). While the control signal ES is "0", the address A0 to A7 by the counter 314 is displayed.
And the interpolation selection data SD corresponding to the addresses A8 to A15 according to the designated magnification and the processing timing signal TD are repeated in block units (dotted line area in FIGS. 35 and 37), and 4096 data corresponding to one line are obtained. Data selection memory 320
Written in.

Here, when the magnification is 160% as shown in FIGS. 25F and H, 160 clocks (data for 160 pixels), the magnification is 80%
If, then 100 clocks (data for 100 pixels) are repeated.

Further, since the data ROM 311 has a slow access time, the data ROM 311 is read with a clock having a frequency lower than the normal reading speed. The write timing is the data transfer clock SETC
It is synchronized with LK.

In the image reading state, the buffer circuit 316 is
The signal from the data ROM 311 is provided so as not to adversely affect the data selection memory 320 and the synchronization circuit 370, which will be described later, and is active only while the control signal ES is "0".

The control signal ES is also used as an enable signal for writing to the data selection memory 320 (first
(See Figure 14).

When the writing of the data (4096 pieces of data) to the data selection memory 320 is completed, the transfer end signal C from the counter 360
S is output, which ends the data writing period (see FIG. 25).

After that, the normal image processing mode is set and the data selection memory
The interpolation selection data SD and the processing timing signal TD are read from 320 and supplied to the synchronization circuit 370 in the subsequent stage.

The counter 314 is cleared by the clear signal CLR (F in the figure), but the clear timing differs depending on the magnification.

Note that when the reduction ratio is set, it becomes as shown in FIGS. In the same figure, G and H show the relationship between the address data of the counter 314 and the clear signal CLR supplied thereto when the magnification is 80%.

The processing timing signal TD is selected as "1" when the interpolation data S exists as described above and "0" when the interpolation data S does not exist and when the data is thinned out.

FIG. 26 shows an example of the synchronizing circuit 370 in FIG.

The synchronizing circuit 370 includes a plurality of latch circuits 371 to
375 and a plurality of AND gates 381 to 384, the interpolation selection data SD is sequentially latched by the latch circuits 371, 372 and 375.

On the other hand, the data of bit 1 of the processing timing signal TD is sequentially latched by the latch circuits 371 to 374. In contrast,
The data of bit 0 is latched by the latch circuits 371 and 372.

The synchronous clock CLK2 is supplied to the latch circuits 371 to 374 as a latch clock, and the phase-inverted synchronous clock ∇ is supplied to the remaining latch circuits 375 and AND gates 381 to 384.

On the other hand, the latched processing timing signal TD is supplied to the plurality of AND gates 381 to 384. The output of the AND gate 381 is the read clock RDCL of the input buffer 400.
While being supplied as K, the output of the AND gate 382 is supplied as the latch clock DLCK of the latch circuits 11 and 12.

Similarly, the output of the AND gate 384 is supplied as the write clock LCK2 of the output buffer 450, and the output of the AND gate 383 is supplied as the latch clock LCK1 of the latch circuit 14.

Here, the AND gates 381 to 384 are opened when the processing timing signal TD is "1", and closed when the processing timing signal TD is "0".

When the synchronizing circuit 370 is configured in this way, it is possible to generate a read / write clock having a frequency according to the designated magnification. A specific example will be described below.

FIG. 27 shows a timing chart when a magnification of 160% is selected.

First, the data output from the data selection memory 320 is the second data.
As shown in FIG. 9, 4 bits of all data are interpolation selection data SD, and of the remaining 4 bits, bit 0 is for read clock RDCLK for input buffer 400 and latch clock DLCK for latch circuits 11 and 12. Used as data.

Bit 1 is used as a write clock LCK2 for the output buffer 450 and a latch clock LCK1 for the latch circuit 14. Bit 2 is used as a repeat signal to the data ROM 311 and a clear signal CLR to the counter 314. Bit 3 is an unused bit in this example.

Now, when the magnification is 160%, the data selection memory 3
The interpolation selection data SD shown in FIG. 27B is output from 20 and the data shown in D and E of the same figure is output as bit 0 and bit 1 of the processing timing signal TD.

Both B and C in the figure show the interpolation selection data SD, but FIG. B shows the timing before being latched by the latch circuit 371, and C in the figure is the timing after being latched.

Therefore, the latch circuits 372 in the next stage output the signals delayed by one cycle as shown in FIGS. Since the interpolation selection data SD is further latched by the latch circuit 375 by the synchronous clock ▲ ▼ of the opposite phase, the interpolation selection data SD is further delayed by 1/2 cycle. The interpolation selection data SD shown in FIG.
It is supplied to M13 as address data.

Since the AND gates 381 and 382 are supplied with the processing timing signal TD of bit 0 shown in D and G in the same figure, if these are ANDed with the synchronous clock ▲ ▼ of the opposite phase, the reading shown in J and K in the same figure. The clock RDCLK and the latch clock DLCK are obtained.

Further, since the processing timing signal TD of bit 1 is latched by the latch circuits 373 and 374 (L and M in the same figure),
The AND gates 383 and 384 output clocks LCK1 and LCK2 as shown in N and O of FIG. These clocks LCK1, LCK2
Are clocks in opposite phases to each other, but their frequencies are the same as the synchronous clock CLK1.

In this way, when the enlargement ratio is selected, only the read clock RDCLK supplied to the input buffer 400 has its frequency changed.

FIG. 28 is a timing chart when reducing to 80%.

In this case, the interpolation selection data SD shown in FIG. 9B is output from the data selection memory 320, and the data shown in D and E of FIG. 7 is output as bit 0 and bit 1 of the processing timing signal TD.

The read clock RDCLK supplied to the input buffer 400 and the latch clock RDCK to the latch circuits 11 and 12 are as shown in J and K in FIG. That is, these frequencies are unchanged.

On the other hand, since the latch circuits 373 and 374 output the latch clocks shown in L and M in the figure, the AND gate 383 obtains the latch clock LCK1 shown in N in the figure. Then, from the other AND gate 384, the write clock LCK2 shown in FIG.

As described above, when the image is reduced, only the frequency of the write clock LCK2 for the output buffer 450 is changed according to the set magnification.

As described above, in order to record the enlarged / reduced image on the basis of the center line 1 of the recording paper P, it is necessary to control the write start timing of the input buffer 400 or the write start address of the output buffer 450. Good.
The reason will be described below.

As mentioned above, the maximum image reading size of CCD56,57 is
If the resolution is 16 dots / mm in B4 format, the memory capacity for one line is 4096 bits. Therefore, the line memories 401, 402, 451 and 452 may have a capacity of 4096 bits.

At the same size, the line data having a capacity of 4096 bits is directly supplied to the output buffer 450 side and then to the output device 65.

On the other hand, when the image is enlarged, the image data amount of the input buffer 400 increases according to the magnification, and the increased image data is supplied to the output buffer 450. Therefore, the image data overflows as it is. The required image data cannot be stored in the output buffer 450 without omission, and the image cannot be recorded with the center as a reference.

When the original image is magnified twice, the amount of image data becomes twice as much as the original image data due to the interpolation process. Therefore, the amount of data written in the input buffer 400 is limited to 1/2 in advance.

On the other hand, the 2048th bit of the image data corresponds to 1/2 of the capacity (4096 bits) of the effective horizontal line (effective length) in B4 format, which corresponds to the center 1 of the recorded image.

Therefore, a total of 2048 bits from the 1024th bit to the 3072th bit of the input image data are shown in FIG.
As shown in FIG. 7, if the data is sequentially written from the 0th address of the input buffer 400, all the image data can be written in the output buffer 450 even if the data amount is doubled by interpolation processing. (Figure B).

In this case, since the image data after the interpolation processing is the data expanded as shown in FIG. 30B with the center 1 of the image as the center, a part of the required image may be recorded as lacking. There is no such thing.

From such a fact, at the time of enlargement, if the write start address of the input buffer 400 is controlled according to the set magnification, the 31st
As shown in FIG. B, it is possible to record on the recording paper P centering on the center of the image.

Therefore, the preset data Po at the time of expansion is set as follows.

Preset data Po = (4096 × enlargement factor−4096) / 2 FIG. 31C shows an example of recording at the same magnification.

At the time of reduction processing, as shown in FIG. 30C, the input buffer 400
The data writing and reading to and from are the same as in the case of the normal size, and the writing is performed from the 0 address and the reading is performed from the 0 address.

When the image is reduced by 0.5 times, the image data for one line is reduced to 1/2 by the interpolation processing, and this image data is written in the output buffer 450.

Here, if the read image data is written in the output buffer 450 as it is, the image data is written from the 0 address of the output buffer 450 and is recorded with the image data from the 0 address as shown in FIG. Since the recording is sequentially performed from one side of the paper P, the image is recorded only as shown in FIG. 48A.

To avoid this, the write start address should be set to the 1024th address (D in the figure).

Then, if the read start address is set to 0, it means that blank data (corresponding to white) is recorded up to the 1024th bit, so that the recorded image is recorded on the recording paper P as shown in FIG. 31A. A reduced image is recorded around the center 1 of the. The read start address is set by the preset data Po.

Therefore, the write start address of the output buffer 450 is set as follows: write start address = (4096−4096 × reduction ratio) / 2.

Therefore, by appropriately selecting the write start timing (preset data Po) of the input buffer 400 and the write start address of the output buffer 450 according to the enlargement / reduction scale, a line memory having a capacity of one line can be obtained. Even if it is used, the central reference recording process can be realized. FIG. 32 shows an example of setting write start address data and preset data Po.

FIG. 33 shows an example of the processing operation described above.

As shown in FIGS. 7A to 7G, the preset data Po and the write start address are set in synchronization with the horizontal synchronizing signal H-SYNC.

Write and read timings for the input buffer 400 are shown in FIGS. Similarly, write and read timings for the output buffer 450 are shown in FIGS.

The control signals INSEL and OUTSEL are 2 as described above.
It is a rectangular wave signal whose horizontal period is one period.

Now, FIG. 34 shows the relationship between each sampling position used for image enlargement and the interpolation selection data SD. The illustrated data is for a case where the enlargement ratio M is 160%, and the magnification can be set at intervals of 1%.

If the magnification is 160%, the sampling interval is 100/1
Since 60 (= 0.62500), the relationship between the sampling position (theoretical value) with respect to the original data position and the interpolation selection data SD referred to at that time is as shown in the figure.

In the interpolation selection data SD at the original data position “0”, the former data (0) has the sampling position (0.
00000), and the latter data (A) is the interpolation selection data SD when the sampling position is (0.62500).

Note that the values of the latter interpolation selection data SD do not exist where the original data positions are 2, 4, 7, 9, and so on. This means that there is no data increase due to the expansion and only one data exists in the cycle period.

These data are actually stored in the data ROM 311 as shown in FIG. In FIG. 35, the data referred to by the base address ADRS (vertical axis) and the number of steps (horizontal axis) is the interpolation selection data SD on the left side, and the data on the right side is the clock control of the input buffer 400 and the output buffer 450. Clear C to signal and counter 314
LR (processing timing signal TD) is shown.

Since the bit configuration of the data ROM 311 is as shown in FIG. 33, when the read clock RDCLK and the latch clock DLCK are output, bit 0 = “1”, and the write clock LCK2 and the latch clock LCK1 are output. In this case, bit 1 = "1", and bit 2 = "0" at the data position of the repetition cycle.

That is, in the interpolation selection data SD, bit 0 corresponding to the previous cycle may be set to "1" and the subsequent cycle may be set to "0".

Bit 1 is always "1". Therefore, ×××× 0111 = × 7 ×××× 0110 = × 6 ×××× 0011 = × 3.

FIG. 36 shows a part of the data table of the interpolation selection data SD used when reducing the image. For example, the data shows a reduction rate M of 80.
This is the case with%. In the figure, * indicates thinning data (invalid data). Actually, it is stored in the memory in the state as shown in FIG. Only in the data corresponding to the * mark, bit 1 = "0". In the figure, it is shown as "05".

Next, the above-described enlargement / reduction processing operation will be described in detail with reference to FIG. For convenience of explanation, the enlargement ratio M is 160%.

FIG. 38 shows the relationship between the original data and the interpolated data in an analog manner. D shows the original data and S shows the converted data after the interpolating (interpolation data).

The relationship between the image information level and the interpolated data at this time is as shown in FIG. Further, the relationship between the sampling pitch and the interpolation selection data SD at the time of interpolation at this time is as shown in FIG.

FIG. 39 shows a timing chart of signals in each unit during this interpolation processing.

Original image data obtained from CCD56,57
(0), D1 (F), D2 (F), D3 (0), D4 (0) (the parenthesis indicates the gradation level of each image data).

When the read clock RDCLK is supplied to the input buffer 400, the image data D is output after the access time t1 (first
39 (A, B), which is latched by the latch clock DLCK (C in the same figure). When D1 (F) is output from the latch circuit 11 in synchronization with the latch clock, the latch circuit 12 outputs
D0 (0) is output (D and E in the figure).

The latch pulse DLCK is delayed from RDCLK by one cycle of the synchronization clock CLK1.

On the other hand, the data table shown in FIG. 37 is referred to by the magnification signal set externally. As interpolation selection data SD
0; A; 4; E; ... (Fig. 39F) is output.

As a result, from the interpolation ROM 13, the interpolation data table is referred to by the image data D0, D1 and the interpolation selection data SD, and the required interpolation data S (G in the figure) is output. Therefore, the interpolation data S is 0 (S ₀ ), 9 (S ₁ ), F (S ₂ ), F (S ₃ ), 8 (S ₄ ), 0 (S ₅ ),
... will be.

The read interpolated data S are sequentially sent to the latch circuit 14 (H and I in the same figure). The binarized interpolation data S is written in the output buffer 450 by the write clock LCK2 (J and K in the same figure).

In FIG. 39, t2 is the access time of the interpolation ROM 13, and t3 is the access time of the binarizing means 69.

Next, the reduction processing will be described.

FIG. 40 shows the image signal in an analog manner when the reduction ratio is selected to be 80%. The image data D0, D
1, D2, D3, ... Are indicated by a circle, and interpolation data S0, S1 ,. FIG. 41 shows a timing chart of signals at that time. The relationship between the original image data D and the interpolation data S used at that time is shown in FIG. 37, and the relationship of the interpolation selection data SD is shown in FIG. On the street.

The gradation level of the image data is the same as in the case of the enlargement processing described above.

Then, two adjacent image data (for example, image data D1 and D0) are supplied from the latch circuits 11 and 12 to the interpolation ROM 13 as an address signal, and the reduction magnification (8
The fact that 0%) is supplied to the data selection signal writing circuit 310 is also the same as in the case of the enlargement processing described above.

In the case of reduction processing, both the read clock RDCLK and the latch pulse DLCK have the same frequency as the synchronous clock CLK1,
Since the data shown in FIG. 36 is selected as the interpolation selection data SD, the relationships of signals from the input buffer 400 to the interpolation ROM 13 are as shown in FIGS.

On the other hand, since the latch pulse LCK1 is G in the figure,
The latch output is as shown in FIG. Here, since the write clock LCK2 also has the same frequency as the latch pulse LCK1, the data as shown in FIG.

In the above-described embodiment, if the enlargement / reduction ratio is changed, the interpolation selection data SD output from the interpolation data selection memory 320 changes, and the interpolation ROM 13 is addressed accordingly and the corresponding interpolation data S is output. It will be obvious that this will be done.

By the way, although the above is applied to the image processing apparatus in which the image is read based on the center of the original and the image is recorded based on the center of the recording paper, the present invention is also applied to other image processing apparatuses. can do.

First, when both the image reading and the image recording are processed with reference to one side of the original (recording paper),
Since the image reading start position of the CCDs 56 and 57 is the same as the recording start position (optical scanning start position, in the laser printer, the recording beam start position of the laser beam), the present invention can be applied without problems.

Secondly, in the image processing apparatus of the type in which image reading is performed with reference to the center line of the original and image recording is performed with reference to one side of the recording paper, the read start address of the input buffer 400 is as follows. become.

In this case, the preset data Po of the output buffer 450 is always 0. On the other hand, the read start address cannot be determined only by the magnification signal. It depends on the size of the original.

Therefore, in this type of image processing apparatus, the read start address is determined from the designated magnification indicating the document size.

As shown in Fig. 42, the size of the original 52 to be read is A4.
The following is the case when the format is true.

As mentioned above, when the size is 16 dots / mm, the width of the A4 size bit is 210 mm x 16 ots / mm = 3360 bits, so the maximum read document size is B4 size.
The value obtained by multiplying the width Y in Fig. 42 by the magnification is the input buffer.
This is the read start address for 400.

Therefore, the read start address is (4096-3360) / 2 = 368 bits.

FIG. 44 shows each value of the write start address and the preset data Po at an arbitrary magnification.

However, the original size is A4. Thus, the write start address and the preset data Po are constant regardless of the magnification because the image is recorded with one side as the reference.

Thirdly, as shown in FIG. 43, in the image processing apparatus of the type in which the image reading is performed with one side as the reference and the image recording is performed with the center line 1 of the recording sheet as the reference, The preset data Po and the write start address of the output buffer 450 are determined as follows.

That is, when 4096> 3360 × magnification, the write start address is set, and vice versa, the preset data Po is set.

Therefore, when 4096> 3360 x magnification, the write start address is: write start address = (4096-3360 x magnification) / 2 At this time, the preset data Po of the input buffer 400 is 0.
Is set to.

On the other hand, when 4096 <3360 × magnification, the preset data Po is preset data Po = (3360−4096 / magnification) / 2. At this time, the write start address of the output buffer 450 becomes 0.

As a result, the read start address and preset data Po at any magnification have values as shown in FIG.

As described above, the write start address or the preset data Po can be changed according to the reading or writing standard of the document.

[Effects of the Invention] As described above, according to the present invention, the write start address to the output buffer is changed according to the reduction ratio during the reduction processing, and the write start timing to the input buffer is increased during the enlargement processing. Since the change is made according to the magnification, the same effect as when the enlargement / reduction is performed with the center of the reading side as the reference is obtained, and the recording is performed with the center of the recording paper as the reference. Will be.

As a result, even in the case of the reduction processing, there is no possibility that the reduced image is recorded unevenly or the image is recorded outside the transfer area of the recording paper. Similarly, since the enlarged image is not biasedly recorded or is enlarged and recorded up to an unnecessary margin portion, it is possible to correctly record the required image.

Furthermore, in the present invention, since the interpolation data is obtained while referring to the data table, the image quality is better than that of the conventional method, and high-speed processing is possible.
It has a remarkable effect.

[Brief description of drawings]

FIG. 1 is a system diagram showing an outline of an image processing apparatus capable of enlarging / reducing according to the present invention, FIG. 2 is a system diagram showing an example of an image reading apparatus, and FIG. 3 is a waveform diagram used for explaining the operation thereof.
FIG. 4 is an explanatory diagram of the shading correction, FIG. 5 is a system diagram showing an example of the shading correction circuit, FIGS. 6 and 7 are diagrams for explaining color separation, and FIG. 8 is an example of a color separation map. FIG. 9 is a system diagram showing an example of a color separation circuit, FIG.
Fig. 10 is a system diagram showing an example of a color selection circuit, Figs. 11 and 12
13 is a waveform diagram used to explain the image forming process shown in FIG.
FIG. 14 is a block diagram showing an example of a simplified electrophotographic color copying machine. FIG. 14 is a system diagram showing an example of an enlargement / reduction circuit.
Figures and 16 show the relationship between image data, interpolation selection data SD and interpolation data S, Figure 17 shows an example of threshold data used for line drawings, and Figure 18 is used for photographs. Showing an example of a threshold value data matrix, FIG. 19 is a system diagram showing an example of an input buffer, FIG. 20 is a system diagram showing an example of an output buffer, and FIGS. 21 to 23 are waveforms used for explaining the operation. FIG. 24 is a system diagram showing an example of a data selection signal writing circuit, FIG. 25 is a waveform diagram used to explain its operation, FIG. 26 is a system diagram showing an example of a synchronizing circuit, FIGS. 27 and 28. Fig. 29 is a waveform diagram for explaining the operation respectively, Fig. 29 is a configuration diagram of the data ROM, Fig. 30 is a diagram for explaining recording of the central reference at the time of enlargement / reduction, and Fig. 31 shows an example of recording of the central reference. Fig. 32 shows an example of the data of the write start address when recording with center reference. FIG. 33, FIG. 33 is a waveform diagram for explaining the processing operation at that time, FIGS. 34 and 35 are diagrams showing specific numerical examples of sampling positions and interpolation selection data at the time of image enlargement, and 36. FIGS. 37 and 37 are diagrams showing specific numerical examples of sampling positions and interpolation selection data at the time of image reduction, FIG. 38 is a diagram of an image signal used for explanation of image enlargement, and FIG. 39 is an explanation of operation at that time. FIG. 40 is a waveform diagram used for explanation of image reduction, FIG. 40 is a diagram of image signal used for explanation of image reduction, FIG. 41 is a waveform diagram used for explanation of operation at that time, and FIGS. 42 and 43 are other than image reading and image recording. FIG. 44 and FIG. 45 are diagrams showing the relationship between the write start address and preset data used at that time, and FIG. 46 is an example of a main part of a conventional image processing apparatus capable of scaling. Fig. 47 is a waveform diagram for explaining the operation, Fig. 47 FIG. 8 is an explanatory diagram of the image reading system, and FIG. 49 is a diagram showing an image recording state. 2 …… Enlargement / reduction circuit 50 …… Image reading device 65 …… Output device 69 …… Binarizing means 70 …… Sequence control circuit 75 …… Operation / display unit 80 …… System control circuit (CPU) 300 …… Interpolation data selection means 310 …… Data selection signal writing circuit 320 …… Data selection memory 400 …… Input buffer 450 …… Output buffer 401,402,451,452 …… Line memory D …… Image data S …… Interpolation data SD …… Interpolation selection data TD ...... Processing timing signal

Claims (4)

[Claims] 1. An image processing apparatus capable of enlarging / reducing an image using image data obtained by photoelectrically converting image information and reading the image information, wherein an input buffer and an output buffer for the image data are provided, and the image data is reduced. At the time of processing, the write start address to the output buffer is changed according to the reduction processing, and at the time of enlargement processing, the write start timing to the input buffer is changed according to the enlargement processing. Image processing device that can be enlarged / reduced. 2. A write start address to the output buffer is changed according to a reduction ratio, and a write start timing to the input buffer is changed according to an enlargement ratio. Range 1st
An image processing apparatus capable of enlarging / reducing according to the item. 3. The expansion according to claim 1, wherein the write start address to the output buffer or the write start timing to the input buffer is changed according to the recording paper size. Image processing device that can be reduced. 4. The write start address to the output buffer or the write start timing to the input buffer is changed according to the reading or writing reference position of the original document.
An image processing apparatus capable of enlarging / reducing according to the item.