JPS5970358A - Picture contracting and expanding device - Google Patents

Abstract

PURPOSE:To execute simply in high speed the contracting and expanding processing of a picture, by switching optionally a preset value of a counter with a digit signal for interleaving or overlapping a picture. CONSTITUTION:In magnifying a picture, a magnifying command CC1 of an NAND gate 13 is set to ''1'', and in shrinking the picture, a shrinking command CC2 of an NAND gate 23 is set to ''1''. Further, a preset value PD is outputted from a preset data memory 50 in response to the magnification rate and contraction rate of the picture, the preset value is subtracted with a main clock signal MCK in a sampling counter 30, and when the count is finished, a digit signal BW is outputted. In magnifying the picture, the input picture data is counted overlappingly with a BW output, a magnified picture data D2 is outputted. In shrinking the picture, the input D2 of the output buffer 20 is interleaved and outputted in response to the BW output.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an image reduction/enlargement device for reducing and enlarging binary dot matrix images. The image on the am-device relates to a small magnification device.

[Prior art]

In digital image processing, it is necessary to perform appropriate reduction/enlargement on a dot matrix image of λ values (y:Ct&). For example, in a facsimile machine, when outputting a reproduced image, an image editing device performs reduction/enlargement by density conversion of scanning lines to obtain a reproduced image of a predetermined size.

There have been many proposals regarding circuits that perform this kind of material reduction/enlargement.For example, the conventional method is to input image data into an image memory and then perform an operation to thin out the image data. Processing is done by software line 9
There is a way.

However, since this method requires a lot of time to display, it is difficult to process in real time, and interactive editing work is not possible.

In addition, as another method, for example, JP-A-33-1010
73 and Japanese Unexamined Patent Publication No. 1973; -1λ≠/r by using an adder as described in 1976, by repeatedly adding the magnification in the case of reduction, and repeatedly adding the number of magnifications in the case of enlargement. A technique is known in which the carry signal is used as a sampling signal for pixel thinning or duplication.

However, in this method, the density is reduced by % from 72 dots/NM to t dots/11Ill, and conversely, the density is reduced by % to r dots/1Ill.
1m@) et al.:1. In particular, in the case of reduction/enlargement with a magnification expressed by a simple V number ratio, such as doubling/enlargement to a dot/crane, and also featuring an adder with a large number of digits,
In the case of enlargement, it is necessary to update the reciprocal of the multiple as a parameter, which is inconvenient for performing image processing.

〔the purpose〕

Therefore, the present invention eliminates the drawbacks of the prior art as described above, and
It is an object of the present invention to provide an image reduction/enlargement device capable of easily and quickly executing reduction/enlargement processing.

〔composition〕

Hereinafter, one embodiment of the present invention will be explained with reference to the drawings.
The figure is a block diagram showing an image reduction/enlargement apparatus according to the present invention.
The input buffer IO, which is a temporary storage device for storing image information D3, is connected to the output buffer J, which is a similar temporary storage device and which is configured with a register, for example, and which outputs the image information D3. The information is sent to the input buffer 3, and 2 is transferred. Input buffer IO and output buffer J receive address information A/ and A2Y by address counters // and :l/, respectively.
Addressing is performed by given f. The input buffer IO and address counter // of these fL are output buffer J and address counter 21 by the input clock signal OK/.
is driven by the output clock signal OK2.

By the way, the main clock signal MOK is input to the AND gates 12 and n and the sampling counter 30.
The sampling counter 30 receives as input the preset value PD output from the preset data memory SO connected thereto according to the reduction rate or enlargement rate, and receives the main clock signal M.
Upon OK, this preset value FD is decremented, and when counting is completed, a digit signal BW for performing digit shift or digit down is output. This digit signal is input to the NAND gate (/J), the coupling counter 30, and the memory address counter. The count value of the 9th memory address counter is set by the cycle data CD, and the count value is added to the digit signal BW from the sampling column y130 to output the memory address data MA to the preset data memory 50. Furthermore, when the memory address counter (cycle data CD) is incremented to 10/number, it is set to 1j.

The other 1lII of NAND gate/3 has expansion command C.
The reduction commands Ca and Z are input to the other side 111 of the o/ga crystal gate 3, and the output of the NAND gate 13 is the other side of the ANDN gate. 2 (1) There are n inputs to the other 1111, and the output of the ANDN-gate is the input clock conversion signal OK/, and the output of the AND-gate is the output clock signal OK2. Their clock signals CK/ and OK2 are the main clock signal MOK.
, sampling color/30 digit signal BY, enlargement command C
o/, the reduction finger reduction command C eco is set.

Next, in order to explain the operation of this embodiment, 1.
/, when enlarging 7 times, when data is transferred from input buffer 10 to output buffer J, 3 pixels out of 10 pixels need to be transferred twice, so 3rd % 6th , 700th data, address 4.74g
Data "C" is set to "C", and cycle data "CD" of the memory address input/tally is set to "21".

In addition, in the case of enlargement, the car enlargement command CC7 is set to a high level of 171, and the reduction command 00j is set to a low level of 10.
′, the output of the NAND Gut force is %11 for n.
The output clock coefficient OK, which is the output of the AND gate with this output and the main clock coefficient MCK as input, is
, 2 are equal to the main clock coefficient MCtK.

On the other hand, in NAND goo)/3, since the enlargement command CCl is %l', its output follows the state of the bad digit signal B'1IO) at the output of the sampling counter 30, which is the other input. Therefore, the input clock signal OK/ is generated by the output of this NAND gate 13 and the main clock signal MOK. Then, 13' is output to the sampling counter 30 as preset data FD based on the contents of the 7' reset data memory 307J-.

The sampling counter 30 decrements according to the main clock signal MOK, and when a clock pulse one higher than the preset data FD is counted, a high level 1/I digit signal BY is output. Konoto'@
Since the inputs of the NAND gate 13 are all %/I, its output is 401, which is AND gate)/,
! 71. The input clock signal OK/ is not outputted, and the address of the input buffer IO is not changed. Therefore, the same information D! for the output buffers including the manual buffer 107i! is transferred. However, an output pulse OK signal is added to the output buffer J according to the main clock signal.
- Duplicate information of this is also output as image information @Ds.

On the other hand, since the digit signal BY of the sampling counter 30 clears the sampling counter 30 itself and counts up the memory address counter S, the MA signal 1
1' is output to the preset data memory SO, and 13# is output from the preset data memory SO(7) to the sampling counter 3o as the preset data FD corresponding to 11'.
is output to. The sample printer counter 3o performs subtraction in the same way using the main clock coefficient MOK, and at the time of the second clock pulse, the same image information as that outputted by the previous clock pulse is output as IL. At this time, as the count value of the memory address counter changes to 1-', 14c# is inputted to the sampling counter 30 as preset data PD.Then, by the subsequent main clock coefficient, the value corresponding to the j-th address is input. The image information to be output is doubled.

The above operation is shown in the time chart of Fig. 2, and the input clock signal OK/ is repeatedly paused for 3 clocks, /clocks, 3 clocks, μ clocks, and l clocks. Therefore, if the start address of the input buffer IO is 1, then 10, 1+j, 1+, etc.
The data of the river . . . is transferred to the output buffer l as information D2 for λ clocks.

The output clock signal OK2 is synchronized with the main clock signal (ff
) and output without missing.1 etc., every reference clock,
Duplicate information is output every μ clock, every j clock.
5. After all, at the end of one feed of the l line, image information D3 enlarged seven times is obtained.

Next, when performing 0.6 times #small, input buffer ic
The information transferred from the output buffer is thinned out for j pixels and λ pixels and output from the output buffer.

Therefore, we decided to thin out the second and j-th data, set data 11# to address O# of preset data memory SO, data ant 31 to address ``/1, and set cycle C of memory address counter I10.
Set D to 'll and further enlarge command cai to 10
1. Set the final small command 00.2 to Ant Og.

Since the enlargement command CO/ is %OI, the output of the WAND gate 13 is always 111. Therefore, the input clock signal CKl, which is the output of the AAND gate 12 to which f is input, is the main clock signal MOK ((series). Compete,
Therefore, information D2 is transferred from input buffer IO to output buffer at the timing of main clock signal McK. However, since the reduction command CO2 is %/I, when the sampling counter 3077 outputs the next digit signal BY, the output of the NAND gate becomes %QI.2. The output clock signal OK, which is the output of the AND gate n, is not output, and the output buffer z does not output the image data, but it is output as the image information D3 →
Sakima gravity sfl information is output.

A digit signal BY is output from the sampling counter 30,
The anchor 1 is exactly the same as the case of expansion, and the memory address counter l10 and f17c are output from the memory address information MA, and the preset data memory is set in advance to the address of the preset data memory, 0. The data FD becomes the setting value of the sampling counter 30, and the sampling counter 30 is decremented by the pulse of the main clock (MOK No. 7), and the digit signal BW is output by one more pulse than the value of the preset data FD. Please use this digit signal BW to output buffer 20.
As the output of Carr et al.'s 1fii image data is suppressed, the MA code changes to add memory address Karantake 0, and the preset data memory 5070 is designated by this changed MA code. The preset data FD stored in the reply is output to the sampling counter 3o, and the long purpose of counting becomes a joke.
The above operations are repeated71. As shown in the time chart of Figure 3, the input clock signal OK/
The output clock coefficient CK2 matches the main clock component MOK, but the output clock coefficient CK2 becomes the 41st clock with the 24th and jth clocks missing. Therefore, the input buffer 10
The information σγ is transferred from the output buffer to the output buffer 4pD, z is equal to the input information @D/, 1-1-/, 10! ,1+3.1
10 μ, river, but from the output buffer aco 0, i
10/, 1 + Hiro... information is output from the bladder 7'f, resulting in an output buffer), OJ et al.
The f+1 element is a thinning force, and the t12 friend information is transferred sequentially,
When the transfer of 1 line is completed, the image information D3 is reduced by 2, that is, 06 times, and 1f11 image information D3 is obtained, which is 7L.

In addition, in the above embodiment, the main direction and t' direction have been explained, but in the case of reduction, in the case of reduction, lines are arbitrarily thinned out in units of l lines, and when enlarged. In this case, it is good to draw W doubles of regular lines with L lines as units. In this case, since the processing time is sufficient for line-level processing, it is also possible to use a conventional method such as using a microfluorocessor. In other words, this invention can be used alone or in combination with other methods.

〔effect〕

According to the present invention, if the digit for thinning out or duplication of an image is set to 7, the sampling counter presets 1f.
The main clock signal is used to output the horn run at c1t.
'4 to 1. ? I can switch the grisset value of
Because it is based on It becomes possible.

lA Drawing 1 ('t7; (Explanation) Figure 1 is a block diagram showing the configuration and operation of the image reduction/enlargement circuit that is the key to inventiveness, and Figure 2 is a block diagram showing the initial large-scale processing by the device in Figure 7. Figure 3 is a time chart when the reduction process is executed by the first device.

10...Input buffer, of course...Output buffer, 3
0... Sappling counter, // , :ti・
・Address counter, /, 2, . 2 Yu...A I
J D gate + /J 1-3...)i A)I
D Kate 1,? 0... Sappling counter, Xun...
・Memory address counter, 3;0...F" reset data memory, MOK...Raw clock signal, FD...
・Preset data.

Claims (1)

[Claims] An input buffer that stores a predetermined amount of image information; an output buffer that transfers and stores the information in this manual buffer and prepares it for output; and an output buffer that is operated by a main clock signal and has a reduction ratio or an enlargement ratio. A sampling counter that outputs a digit signal according to a preset value, and a sampling counter that operates based on this digit signal,
A memory address counter that outputs address information, and an address & L force specified by this address information.
and a preset data memory for outputting preset data to the sampling counter, and in the case of reduction, drives the input buffer with the main clock signal and drives the output buffer with the main clock signal as the digit signal. In addition, in the case of expansion, the output buffer is driven by the main clock signal, and the input buffer is driven by a clock coefficient obtained by thinning the main clock signal by the digit signal. Image reduction/enlargement device.