JPS63226170A - Enlarging, reducing and parallel moving device for image - Google Patents

Abstract

PURPOSE:To prevent the generation of an error of an enlargement and a deduction by converting a sequential address to enlargement and reduction addresses by using an enlargement/reduction table in which the sequential address from a counter is converted in advance with high accuracy to the enlargement and reduction addresses corresponding to the enlargement and reduction rates. CONSTITUTION:A sequential address from a sequential address generating circuit 6 is converted to enlargement and reduction addresses requested in advance with high accuracy (+ or -0.5 the maximum error in all picture elements) corresponding to the enlargement and reduction rates by an enlargement/reduction table table 2 of an enlargement/reduction/parallel movement address generating circuit 1. Subsequently, it is added to a parallel moving extent (+ or -0.5 the maximum error in all picture elements) from a parallel movement table 4 by an adding circuit 5, and enlargement, reduction and parallel movement addresses are derived with high accuracy of + or -1 picture element by an error of the maximum. In such a way, the enlargement, reduction and parallel movement address can be obtained with high accuracy, and a more exact image can be obtained at a high speed.

Description

[Detailed Description of the Invention] [Summary] The present invention is an image enlargement/reduction/translation device that enlarges/reduces sequential addresses generated from a counter as they are.
Because it was a reduced address, an error occurred in the address,
In order to solve the problem of errors in enlargement and reduction, the sequential addresses from the counter are converted in advance to enlargement and reduction addresses according to the enlargement and reduction ratio with high precision.
By sequentially converting addresses into enlarged/reduced addresses using a reduction table, almost no error occurs in enlargement or reduction.

[Industrial application field]

The present invention relates to image processing, and in particular to an apparatus that inputs images continuously output from a television camera or the like and enlarges, reduces, and translates the images in the row direction. When performing such enlargement, reduction, and parallel movement, it is particularly desirable that the precision of enlargement and reduction be high, and a device that can perform enlargement and reduction with high precision is required.

[Conventional technology]

The applicant previously filed a patent application dated January 31, 1986 (No. 18
) (Name of the invention [Image processing device]), [a buffer memory for storing two sets of image data for one line, a sequential address generation circuit for generating addresses for sequentially accessing the buffer memory, and Expansion that generates the same value repeatedly at a certain rate or skips the intermediate value and generates the next value so as to satisfy the magnification condition given as the address value for accessing the buffer memory. and a reduction address generation circuit, and when input image data is stored in one buffer memory according to the address output from the sequential address generation circuit, the expansion/reduction address generation circuit outputs from the other buffer memory 1. proposed an image processing apparatus that continuously enlarges or reduces an image by alternately using two sets of buffer memories such that stored image data is read out according to the address assigned to the image. This method uses two sets of buffer memories that store one row of image data alternately, and processes the data in the other buffer memory while inputting it to one buffer memory, so that the data can be input continuously. Image processing of the television camera output, such as enlargement, reduction, and translation of the image data to be displayed, is possible, and can be realized with a simple and small amount of hardware.

[Problem that the invention seeks to solve]

However, in the device previously proposed by the applicant, the expansion and
Since expansion/reduction addresses were generated by a counter by calculating the repetition period from the reduction rate, expansion/reduction addresses with fractions were particularly important.
When dealing with reduction ratios, rounding down or rounding up is performed, which has the problem of large errors. In this case, a maximum error of ±0.5 per pixel occurs in the enlargement/reduction address, and for example, if the image size is 512 pixels, a maximum error of ±256 pixels occurs.

[Means for solving problems]

FIG. 1 shows a block diagram of the principle of the apparatus of the present invention.

As shown in FIG. 1, the device of the present invention includes two line buffer memories (91, 9z) for storing one line of image data, and sequential addresses for sequentially accessing the line buffer memories (91, 92). It has a sequential address generation circuit (6) that generates the input sequential address, and a conversion table for converting the sequential address into an enlarged/reduced address according to the enlargement/reduction ratio (α). An enlargement/reduction table (2) that converts the address into an enlargement/reduction address and outputs it, a parallel movement table (4) that outputs the amount of parallel movement according to the parallel movement ratio in the row direction, and the enlargement/reduction table (2) ) and the output of the parallel movement table (4), and outputs an enlargement/reduction/parallel movement address (5).
It consists of an enlargement/reduction/parallel movement address generation circuit (1) composed of:

[Effect]

The sequential addresses from the sequential address generation circuit 6 are determined in advance with high precision (maximum error ±0.5 for all pixels) corresponding to the expansion/reduction ratio using the expansion/reduction table 2 of the expansion/reduction/parallel movement address generation circuit 1. It is converted to the enlargement/reduction address specified by the address, and added to the translation amount from the translation table 4 (maximum error ±0.5 for all pixels) in the adder circuit 5, resulting in highly accurate enlargement with a maximum error of ±1 pixel.・Reduction/parallel movement address is required.

〔Example〕

FIG. 2(A), <8) shows a specific block diagram of the main circuit in the principle block diagram of the device of the present invention shown in FIG.
FIG. 2A shows a block diagram of an enlargement/reduction/translation address generation circuit, and FIG. 2B shows a block diagram of a sequential address generation circuit.

The enlargement/reduction/parallel movement address generation circuit 1 is shown in Fig. 2 (A
), the enlargement/reduction table 2 converts the sequential addresses from the counter (FIG. 3 (C)) described later into enlargement/reduction addresses (FIG. 3 (D)), and the row (line) signal. (Line) using (Figure 3 (B)) as a clock
Counts up every time and outputs the current line address.
A bit counter 3, a parallel movement table 4 that converts the row address from the n-bit counter 3 into the amount of parallel movement of the row (FIG. 3(E)), an enlargement/reduction address from the enlargement/reduction table 2, and a parallel movement table 4. Add the amount of parallel movement of the row from
)).

The enlargement/reduction table 2 converts input sequential addresses (Fig. 3 (C)) into enlargement/reduction addresses (Fig. 3 (D)) according to various externally set enlargement/reduction ratios with high precision. It has a conversion table in advance for converting to .

Reference numeral 6 denotes a sequential address generation circuit, which has the configuration shown in FIG. 2 (B), and has n bits that sequentially outputs addresses (FIG. 3 (C)) in synchronization with a clock signal (FIG. 3 (A)). It consists of a counter 6a. 7 is a 1-bit counter which alternately outputs 11 and 0 for each line. 8+, 82
is the 2t01 selector, and the output rI of the 1-bit counter 7
Input path A and input path B are alternately selected in accordance with J rOJ to sequentially output addresses or enlarged/reduced/parallel movement addresses. Line buffer memories 91 and 92 are switched to read mode and write mode, respectively, according to the output "1" or "0" of the 1-bit counter 7, and output image data, respectively. 10 is a 2tol selector,
Output image data from line buffer memories 91 and 92 are alternately selected and taken out.

(Here, α is the expansion/reduction ratio, and β is the translation ratio.) Considering the address generation timing of the i-th row, the amount of parallel movement j becomes j-β·1, and if the enlargement/reduction ratio α is 573 times, then the following is obtained. Since the y-coordinate does not change, in expansion/reduction table 2, only the row direction needs to be converted.
Data of f(α)-1/α is set in the enlargement/reduction table 2. On the other hand, in the parallel movement table 4, βyo is set in the Vo row.

In the expansion/reduction table 2, the n-bit counter 6a
The sequential addresses from (Fig. 3 (C)) are the enlargement/reduction ratio α
Accordingly, all pixels are converted into enlarged/reduced addresses (FIG. 3(D)) with high accuracy at a maximum error rate of ±0.5. In this case, the enlargement/reduction addresses are set in advance with high precision (error ±
0.5 pixel). On the other hand, the current row address of the n-bit counter 3 is determined by the parallel movement amount of the row according to the predetermined parallel movement ratio in the parallel movement table 4 (see Fig. 3).
E)) and the enlargement/reduction from enlargement/reduction table 2.
It is supplied to the adder circuit 5 together with the reduced address (FIG. 3(D)), where both are added to form an enlarged/reduced/parallel movement address (FIG. 3(F)).

Here, if the output of the 1-bit counter 7 is "1" in a certain row, the line buffer memory 91 is set to the write mode by the output "0" of the inverter 11, and the line buffer memory 92 is set to the read mode. , the selector 81 selects the input path B and sequentially outputs addresses, and the selector 82 selects the input path B and outputs enlargement/reduction/parallel movement addresses.

As a result, one line of input image data old n is sequentially written into the memory 91 at addresses, while one line of image data Dout, which has already been input, is read out from the memory 92 at enlargement/reduction/parallel movement addresses. By selecting the input path B of the selector 10, the image data from the memory 92 is output.

When the output of 1-bit counter 7 becomes "0" in the next line,
Contrary to the above, memory 91 is in read mode and memory 92 is in read mode.
is in the write mode, the selector 81 selects the input path A and outputs enlargement/reduction/translation addresses, and the selector 82 selects the input path and sequentially outputs addresses. As a result, the image data written in the memory 91 is read out at the enlargement/reduction/translation address, while the image data old n is newly written in the memory 92 at sequential addresses, and the input path of the selector 10 is read out. By selecting A, image data Dout from 91 is output. Thereafter, the same operation as above is repeated.

〔Effect of the invention〕

According to the present invention, since an enlargement/reduction address is used that converts a sequential address into an enlargement/reduction address according to an enlargement/reduction ratio, a circuit that previously used a sequential address from a counter as an enlargement/reduction address can be used. It is possible to obtain enlargement/reduction/parallel movement addresses with high precision compared to
It has the advantage of being able to obtain more lifelike images at high speed.

[Brief explanation of drawings]

FIG. 1 is a principle block diagram of the device of the present invention, FIG. 2 is a concrete block diagram of the main parts of the device of the present invention, and FIG. 3 is a timing chart for explaining the operation of the device of the present invention. In the figure, 1 is an expansion/reduction/parallel movement address generation circuit, 2 is an expansion/reduction table, 3.6a is an n-bit counter, 4 is a parallel movement table, 5 is an addition circuit, 6 is a sequential address generation circuit, and 7 is an 1-bit counter, 81.82.10 is a 2t01 selector, 91 and 92 are line buffer memories, and 11 is an inverter. Agent: Patent Attorney: Igata Megumi 1. Principle block diagram of the image enlargement/reduction/parallel movement device of the present invention Fig. 1 Block diagram of the enlargement/reduction parallel movement address generation circuit (A) Sequential address Sequential address generation circuit Block diagram (B) (A) Clock
, rtru 1st line address generation timing j = β-i (β: parallel movement rate) Expansion rate α = ÷ times: , HX (n-2) f! :h x (n-1)

Claims (1)

[Claims] Two line buffer memories (9_1, 9_2) that store one line of image data, and a sequential address generator that generates sequential addresses for sequentially accessing the line buffer memories (9_1, 9_2). It has a circuit (6) and a conversion table for respectively converting the sequential address into an enlarged/reduced address according to the enlargement/reduction ratio (α), and converts the input sequential address into an enlarged/reduced address. An enlargement/reduction table (2) that is converted and output, a parallel movement table (4) that outputs the amount of parallel movement according to the parallel movement ratio in the row direction, and an output of the enlargement/reduction table (2) and the parallel movement Addition circuit (5) that adds the output of the movement table (4) and outputs the enlargement/reduction/parallel movement address
It is equipped with an enlargement/reduction/parallel movement address generation circuit (1) consisting of an enlargement/reduction/parallel movement address generation circuit (1), and input image data is input into one line buffer memory (9_1) according to the sequential addresses outputted from the sequential address generation circuit (6). While writing, read the image data that has already been written from the other line buffer memory (9_2) according to the enlargement/reduction/parallel movement address output from the enlargement/reduction/parallel movement address generation circuit (1). The two line buffer memories (9_1, 9
_2) An image enlargement, reduction, and translation device that performs continuous enlargement, reduction, and translation of image data by alternately using _2).