JP3077018B2 - Correction waveform generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a correction waveform generator used for correcting deflection distortion and dynamic focus of a CRT display device.

[0002]

2. Description of the Related Art In a CRT display device, a correction waveform having a vertical / horizontal cycle is generated and corrected in order to correct deflection distortion and homogenize a screen by dynamic focus. In the related art, the generation of these correction waveforms is mainly performed by using an analog circuit and combining a sawtooth wave and a parabolic wave. However, in recent years, a CRT display device has a larger screen and a higher definition, and a demand for image quality has been increased, so that a conventional correction circuit using an analog circuit cannot provide sufficient compensation. Therefore, in order to satisfy these demands, a digital correction waveform generator in which a memory storing a correction waveform, a digital circuit, and a D / A converter are combined has been increasingly used.

Hereinafter, a conventional corrected waveform generator will be described with reference to FIG.

FIG. 11 is a block diagram showing a configuration of a conventional correction waveform generator. In FIG. 11, reference numeral 11 denotes a memory for storing correction waveforms, and reference numeral 12 denotes a timing generation circuit, which synchronizes a clock signal c and an address in synchronization with vertical / horizontal synchronization signals v and h provided from an external device (not shown) such as a computer. Generate signal a. 13 is a register and 14 is a D / A converter.

Next, the operation will be described. The timing generation circuit 12 outputs to the memory 11 an address signal a corresponding to the position of the scanning line on the screen. The memory 11 stores correction waveform data d written in advance for each address signal a.
Is output. The register 13 captures the data d input from the memory 11 at the timing of the clock signal c, and
Output to converter 14. The D / A converter 14 converts the input digital value into an analog value and outputs the analog value to a CRT drive circuit (not shown). As a system adopting this method, for example, an LSI that uses a memory having a storage capacity of 256 words and outputs a pincushion correction waveform in the vertical direction of a CRT (ST7271 type LSI manufactured by SGS Thomson)
I) are commercially available.

[0006]

However, in the above configuration, the data output from the memory is directly used as the value of the correction waveform. However, the number of scanning lines of a recent CRT display device is about 500 to 2,000. Therefore, for example, when a memory having a storage capacity of 256 words is used, a step-like pattern updated every 2 to 4 scanning lines is used. Can generate only the correction waveform of. Therefore, in order to increase the number of updates of the correction waveform in order to improve the correction quality, it is necessary to store more data and increase the number of times of reading the correction waveform data. Therefore, there is a problem that the memory capacity increases and the circuit cost increases.

In an actual CRT display device,
A plurality of waveforms such as linearity correction of vertical deflection waveform (so-called S-shape correction), pincushion correction of horizontal deflection circuit, and dynamic focus waveform are required.
It is necessary to drive circuits of the same configuration including the memory in parallel. For example, if a CRT display device having 1200 scanning lines is to generate six types of correction waveforms that change for each scanning line, a memory capacity of 7,200 words is required, and the circuit cost is further increased. There was a point.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems. A large number of fine correction waveforms for each scanning line can be simultaneously generated while greatly reducing the memory capacity. It is an object of the present invention to provide a corrected waveform generator that realizes a CRT display device at low cost.

[0009]

In order to achieve the above object, a correction waveform generator according to the present invention uses a unit block from a certain scanning line to a scanning line advanced by a certain number K, and changes the correction data of the unit block. The amount is divided into a multiple part of the number K of scanning lines in between and a part less than K, and for the multiple part of K, a constant number is added to the correction value every clock, and for the part less than K, Using a method of generating a straight line by digital difference analysis, it controls whether 1 is added to the correction value to a value such that the value error is always ± 1/2 or less, and the correction data is calculated based on the number of scanning lines K. Of the CRT is also processed.
Since a plurality of smooth correction waveforms that change for each scanning line required for various image corrections of the display device can be generated with an extremely small memory capacity and a circuit configuration shared by the correction waveforms, a circuit Reduce costs,
A high-quality CRT display device can be provided at low cost.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A corrected waveform generator according to the present invention has an M
A first register group storing M types of correction waveform data and having at least a 3-bit parallel output, a M group of registers connected in parallel, and reading / writing any one register by a register selection signal; A first input A connecting at least one bit of the output of the memory;
A second input W connected to the output of the first register group;
, A third input K to which a constant value K is connected, and a first output U
And secondly, an output B, wherein when the value of the first input A is greater than or equal to the value of the second input W, the first output U has the value AW, the second Outputting the value 0 to the output B, and when the value of the first input A is smaller than the value of the second input W, the value A−W + K is output to the first output U, and the value is output to the second output B. A first arithmetic circuit configured by a logic circuit that outputs 1 and M registers are connected in parallel;
A second register group for reading / writing any one register by a register selection signal; a first input E to which at least one bit of the memory output is connected; and a second input group to which one bit of the memory output is connected. 2 input S, a third input V connecting the output of the second register group, a fourth input C connecting a second output B of the first arithmetic circuit, and an output Y. When the value of the second input S is 0, a value V + E + C is output to the output Y, and when the value of the second input S is 1, VEC is output to the output Y. A constant value equal to or less than the constant value K is selected when the second arithmetic circuit constituted by a logic circuit and the first selection signal are valid, and when the first selection signal is invalid. Selecting a first output U of the first arithmetic circuit and outputting it to the first register group; 1 selector and all outputs of the memory when the second selection signal is valid, and selects the output Y of the second arithmetic circuit when the second selection signal is invalid. A second selector that outputs to a second register group, an address signal for the memory, a common register selection signal and a common clock signal for the first register group and the second register group, It has a configuration including a timing generation circuit that generates a first selection signal to the selector and a second selection signal to the second selector.

With this configuration, the M kinds of original correction waveforms are shifted from the starting point of the waveform by the clock signal with respect to time as K
For a series of M sets of correction values of the 0th block to the Nth block sampled for each clock signal, smoothing is performed between the data of the respective waveforms by interpolation calculation by the first and second arithmetic circuits. Since the correction waveform can be generated, the storage capacity of the memory can be reduced, and a plurality of correction waveforms are processed by the same arithmetic circuit, so that the circuit scale can be reduced. CRT
The display device can be provided at low cost.

(Embodiment) An embodiment of a correction waveform generator according to the present invention will be described below with reference to FIGS.

FIG. 1 is a block diagram showing a configuration of a correction waveform generator according to an embodiment of the present invention. In FIG. 1, 1 is a memory, 2 is a first register group, 3 is an input K,
A first arithmetic circuit having W, A and outputs U, B,
U = A−W and B = 0 when ≧ W, U = A when A <W
The operation of -W + K and B = 1 is performed. 4 is a first selector, 5 is a second register group, 6 is an input C,
A second arithmetic circuit having S, E, V and an output Y;
= 0, Y = V + E + C, and S = 1, Y = VE-
C is performed. 7 is a second selector, 8
Is a timing generation circuit which synchronizes with a horizontal synchronizing signal h, a vertical synchronizing signal v and a clock signal c to generate a first selection signal S1, a second selection signal S2, a common register selection signal S3 and an address signal a. To be generated. 9
Is a D / A converter group. Note that the first arithmetic circuit 3
The constant value K to the first selector 4 and the constant value 1 / 2K to the first selector 4 are given by an external circuit (not shown), for example, a register.

Hereinafter, there are three types of correction waveforms.
The case where the second register groups 2 and 5 each include three registers will be described as an example.

FIG. 2 is a block diagram showing a configuration of a specific example of the first arithmetic circuit 3 in FIG. In FIG. 2, reference numerals A, B, K, U, and W are the same as those in FIG. 1, and a description thereof will be omitted. Here, 31 is a subtractor, which performs subtraction between the minuend input A from the memory 1 of FIG. 1 and the subtrahend input W of the first register group 2, and outputs A-W as a subtraction output.
When A ≧ W, 0 is output to the deferred output B, and when A <W, 1 is output to the deferred output B. Reference numeral 32 denotes a first adder, which receives an input from a gate circuit 33 described later.
(1) (constant value K) and input from the subtractor 31 (2) (subtraction output)
And outputs the result to the first selector 4 of FIG. 1 as an addition output U. The aforementioned gate circuit 33 passes the constant value K input when the carry-out output B from the subtractor 31 is 1, and outputs the same as the input (1) to the first adder 32.

With the above configuration, the addition output U of the first adder 32 becomes U = A−W when A ≧ W (B = 0) and A <A
When W (B = 1), U = A−W + K. Note that FIG.
The first arithmetic circuit 3 can be realized by another logic circuit having an equivalent arithmetic function, and the arithmetic function can be realized by, for example, a gate array or a memory.

FIG. 3 is a block diagram showing a configuration of a specific example of the second arithmetic circuit 6 in FIG. In FIG. 3, reference numerals C, E, S, V, and Y are the same as those in FIG. 1, and a description thereof will be omitted. Here, reference numeral 61 denotes a second adder.
The input E from the memory 1 is input (1), and the output B from the first arithmetic circuit 3 in FIG. 2, that is, the input C is input (2) and added and output. Reference numeral 62 denotes a two's complementer, which inputs the added output of the second adder 61 and outputs a complemented output to a third selector 63 described later. The third selector 63 receives the sum output of the second adder 61 as an input (1) and the complement output of the two's complementer 62 as an input (2), and By the selection control of S (S = 0 or 1), the addition output of the second adder 61 and the output of the two's complementer 62 are selected. Reference numeral 64 denotes a third adder. The output of the third selector 63 is used as an input (1), the input V from the second register group 5 in FIG. 1 is used as an input (2), and both inputs are added and output. As Y, the second selector 7 in FIG.
Output to

With the above configuration, when the input S from the memory 1 is 0, the output of the third selector 63 is E + C,
When the input S is 1, it becomes -EC. The third adder 64 outputs an addition value of the output (input (1)) of the third selector 63 and the input V (input (2)) from the second register group 5 as an addition output Y. I do. That is, when S = 0,
Y = V + E + C, and when S = 1, Y = V−E−C is output. The second arithmetic circuit 6 can be realized by another logic circuit having the same arithmetic function as in FIG. 2, and the arithmetic function can be realized by, for example, a gate array or a memory.

FIG. 4 shows the first register group 2 shown in FIG.
FIG. 3 is a block diagram showing a configuration of a specific example of FIG. In FIG. 4, the reference numerals c, S3, and W are the same as those in FIG. 1, and a description thereof will be omitted. Here, 20, 21, and 22 are registers R10, R
Reference numerals 11, R12, and 23 denote a first decoder, which converts a clock signal c into registers 20, 21, 22 based on a register selection signal S3.
Is output to any one of. Reference numeral 24 denotes a fourth selector, which registers 20, 21, 2 based on a register selection signal S3.
2, and the output from the first selector 4 is selected and output. As a matter of course, the register selected by the first decoder 23 and the register selected by the fourth selector 24 always match. The output of the fourth selector 24 becomes the input W of the first arithmetic circuit 3 in FIG.

FIG. 5 shows the second register group 5 in FIG.
FIG. 3 is a block diagram showing a configuration of a specific example of FIG. The configuration of FIG. 5 is basically the same as the configuration of FIG.
Have the same reference numerals as in FIG. 1, and a description thereof will be omitted. here,
Reference numerals 50, 51, 52 denote registers R20, R21, R22, 53 denotes a second decoder, and 54 denotes a fifth selector. The only difference is that the outputs to the D / A converter group 9 are provided in parallel. 4 and 5, the number of registers is three for convenience of explanation.

FIG. 6 is a diagram showing an example of a storage format of the memory 1 in FIG. In the example of FIG. 6, the data of the 0th block in the first row of the bit column stores the initial value using all 8 bits, and the data of the other blocks in the second row (after the first block) are 8 bits (1 word) are divided, S (1 bit) indicating increase / decrease of the correction value, absolute value part E (4 bits) in which constant value K is a multiple, and remaining absolute value part A
(3 bits). In the description of the present embodiment, the constant value K is set to 6. When the number of bits to be assigned to A is (a),
(a) It is sufficient that the power is larger than the constant value K. When the constant value K is 6, 3 bits are sufficient.

FIG. 7 is a diagram showing a storage example of the memory 1 in FIG. For convenience of explanation, there are three types of correction waveforms.

The memory address shown at the left end of FIG. 7 is uniquely determined from a block number indicating one of the blocks and a register number which is a value of a register selection signal. In the 0th block of the memory 1, the initial value of each waveform is stored as data. For example, in FIG. 7, the value of the register number 0 of the 0th block is 11 in decimal, and is stored in the memory as a binary number 000010111.

The correction values for the first block and thereafter are S (0 is positive, 1 is negative) indicating an increase or decrease of the change amount D with respect to each correction value of the immediately preceding block, and a multiple component E ( 0 or a positive number) and a component A (0 or a positive number) smaller than the constant value K are stored.

Here, if a variable p having a value of 1 or −1 is used, the amount of change D can be expressed by the equation D = p (EK + A). S is a value 0 when the variable p is 1, and -1
Takes the value 1 when. For example, in FIG. 7, the value of the register number 0 of the first block is 43 in decimal, and the change amount D with respect to the value 11 of the 0th block is D = + 32. Therefore, if this is applied to the above equation with K = 6, then p = + 1, E
= 5, A = 2, and the binary number 0010101 is stored in the memory.
Store as 0.

FIGS. 8, 9 and 10 are diagrams showing examples of changes in the values of the respective parts in FIG. 1 during the operation of the present embodiment.
The above three FIGS. 8 to 10 are chronologically continuous, FIG. 8 shows time -1 to 5, FIG. 9 shows time 6 to 11, and FIG. 10 shows time 12 to 17. In these figures, one horizontal row corresponds to one clock operation. The time indicates the time in units of one scanning line. The operation of FIG. 1 will be described below with reference to FIGS.

At time (-1) in FIG. 8, the first selection signal S1 is made valid by the timing generation circuit 8 in FIG. 1, and the constant value 1 / 2K, that is, 3 in decimal, activates the first selector 4. A path that is directly input to the first register group 2 via the first register group 2 is formed. Similarly, the second selection signal S2 is also enabled by the timing generation circuit 8, and the output of the memory 1
Is directly input to the second register group 5 via the selector 7 of FIG. At this time, the address sequentially indicates the 0th block of the memory 1 in conjunction with the register selection signal S3, and the first register group 2 has a constant value of 1 / 2K, that is, 3 in decimal, and the second register group 5 has Is the initial value (11,250,5 in decimal) of the corrected waveform is the clock signal c
Are sequentially set.

Next, from time (0) to time (5) in FIG. 8, both the first selection signal S1 and the second selection signal S2 are invalidated.
The output of the first register group 2 and the output of the memory 1 are respectively passed through the first arithmetic circuit 3 to the first register group 2
, The output of the second register group 5 and the memory 1
A path for returning the output from the second register group 5 via the second arithmetic circuit 6 is formed. The second selection signal S2 remains invalid until a series of operations is completed.

Next, at time (0), the first register group 2 has a constant value of 1 / 2K, that is, 3 in decimal.
Is stored, and 3 is input to the input W of the first arithmetic circuit 3. Here, the address sequentially indicates the first block of the memory 1 in conjunction with the register selection signal S3,
The difference between the correction value of the first block and the 0th block is output in the format of FIG. Hereinafter, only the register number 0 will be described for simplicity. 2 is input as a decimal number from the memory 1 to the input A of the first arithmetic circuit 3. Therefore, the output U of the first arithmetic circuit 3 is 3 in decimal.
-2 = 1, and the output B outputs 0. The first register group 2 is updated to a new value 1 by the clock signal c.

On the other hand, the second register group 5 has 11 decimal digits.
(Initial value) is stored, and 11 is input to the input V of the second arithmetic circuit 6. 0 is input to the input S of the second arithmetic circuit 6 from the memory 1 and 5 is input to the input E as a decimal number. Further, 0 is input to the input C of the first arithmetic circuit 3 to the second arithmetic circuit 6. Therefore, the output Y of the second arithmetic circuit 6 outputs 11 + 5 = 16 in decimal. Therefore, the second register group 5 is updated to a new value 16 increased by 5 by the clock signal c.

The operation at time (1) is similar,
Since the input W of the first arithmetic operation circuit 3 has changed to a new value 1, the output U of the first arithmetic operation circuit 3 is 1-2 + 6 =
5. The output B becomes 1.

The input V of the second arithmetic circuit 6 also has a new value.
In addition to the change to 16, the input C becomes 1, and the second register group 5 is updated to a new value 22 increased by 5 + 1 by the clock signal c.

Thereafter, the same operation is repeated until time (5).
As is clear from FIGS. 8, 9 and 10, the value E of the first block of the memory 1 for the second register group 5 during this period, that is, 5 in decimal, is 6 times, the same number of times as the constant value K. Add
And the value 1 is the value A of the first block of the memory 1, that is, 2
As a result, for register number 0, a value obtained by smoothly linearly interpolating the correction value from decimal 11 (initial value) to 43 (final value of the first block) is obtained. . At the last time (5) of the block, the first register group 2 is re-initialized by the first selection signal S1.

Next, from time (6) to time (11) in FIG. 9, the address sequentially indicates the second block of the memory 1. The first selection signal S1 is valid only during the first time (6) of this block. Therefore, although the data output from the memory 1 changes, the basic operation is the same. However, memory 1
Since 1 is input to the input S of the second arithmetic circuit 6, the second register group 5 is supplied to the second block of the memory 1 during this period as is apparent from FIGS. , Ie, 1 is subtracted six times the same number of times as the constant value K, and the value 1 is subtracted the same number of times as the value A of the second block of the memory 1, ie, 1. As a result, for example, the register number For 0, the correction value is a decimal number 43 (first
The values obtained by smooth linear interpolation from the last value of the block to 36 (the last value of the second block) are obtained.

Next, from time (12) to time (17) in FIG. 10, the operation is exactly the same except that the address sequentially indicates the third block, and the same operation is repeated for the subsequent time. It goes without saying that the basic operations are the same for the correction waveforms 1 and 2 as well.

As described above, by configuring the circuit and setting the contents of the memory, it is possible to output linearly interpolated between the correction points for each of the plurality of correction waveforms. Unlike conventional correction waveform generators, without storing many correction point values in memory,
A correction waveform that changes for each scanning line can be generated, and the memory capacity can be significantly reduced.

In an actual CRT display device,
For example, if the height of the screen is about 30 cm, and if the number of correction data in the vertical direction is 40 points, the width of one block on the screen is about 7.5 mm, which is sufficiently practical for visual observation.
Due to the physical properties of the CRT, the shape of the correction waveform is continuous including the change in the curvature, and it is unlikely that there will be an extreme change in part. Therefore, even if finer correction data is stored in the memory, there is almost no accuracy. There is no improvement.

When the present invention is applied, even a correction waveform generator that generates six types of correction waveforms, each of which only has 40 words per type, has only one thirtieth of the conventional technology, and has only 240
It is an object of the present invention to provide a CRT display device having the same accuracy as a word memory.

Note that the sign of the value E of the first arithmetic circuit 3 and the memory 1 shown in FIG. 1 of the embodiment of the present invention is relative. For example, if the value of E is represented by a negative number, ,
Subtractor in specific example of first arithmetic circuit 3 shown in FIG.
It is also possible to use the carry output instead of the carry output by using 31 as an adder. Also, due to the operation of the circuit,
If there is no possibility of erroneous calculation even if the re-initialization of the first register group at the end of each block period is omitted, the first selection signal S1 in FIG. 1 is substituted by the second selection signal S2, The timing generation circuit 8 can be simplified.

[0040]

As described above, the correction waveform generator of the present invention shares a smooth correction waveform that changes for each of M types of scanning lines with a memory storage capacity of 1/30 of the conventional memory and a plurality of waveforms. Since it can be generated with the circuit configuration described above, reduction in circuit cost can be realized, and a high-quality CRT display device can be provided at low cost.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a correction waveform generator according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a specific example of a first arithmetic circuit 3 in FIG.

FIG. 3 is a block diagram showing a configuration of a specific example of a second arithmetic circuit 6 in FIG. 1;

FIG. 4 is a block diagram showing a configuration of a specific example of a first register group 2 in FIG. 1;

FIG. 5 is a block diagram showing a configuration of a specific example of a second register group 5 in FIG. 1;

FIG. 6 is a diagram showing an example of a storage format of a memory 1 in FIG.

FIG. 7 is a diagram showing a storage example of a memory 1 in FIG. 1;

FIG. 8 is a diagram illustrating an example of a change in a value at each point in FIG. 1 during operation of the present embodiment.

FIG. 9 is a diagram illustrating an example of a change in a value at each point in FIG. 1 during operation of the embodiment.

FIG. 10 is a diagram illustrating an example of a change in a value at each point in FIG. 1 during operation of the embodiment.

FIG. 11 is a block diagram showing a configuration of a conventional correction waveform generator.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... memory, 2 ... 1st register group, 3 ... 1st arithmetic circuit, 4 ... 1st selector, 5 ... 2nd register group, 6 ... 2nd arithmetic circuit, 7 ... 2nd selector
8 timing generation circuit 9 D / A converter group
, 20-22, 50-52 ... register, 23 ... first decoder, 24 ... fourth selector, 31 ... subtractor, 32 ... first adder, 33 ... gate circuit, 53 ... second decoder,
54 ... fifth selector, 61 ... second adder, 62 ... two's complementer, 63 ... third selector, 64 ... third adder.

Continuation of the front page (56) References JP-A-7-283960 (JP, A) JP-A-7-240853 (JP, A) JP-A-6-90374 (JP, A) JP-A-4-70692 (JP) JP-A-6-311383 (JP, A) JP-A-5-191667 (JP, A) JP-A-5-199427 (JP, A) JP-A-6-38067 (JP, A) JP-A-7-162700 (JP, A) JP-A-61-184054 (JP, A) JP-A-60-134584 (JP, A) JP-A-63-158668 (JP, A) A) Japanese Patent Publication No. 52-20298 (JP, B2) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 3/23 H04N 3/26 G06T 11/20 H03K 4/00

Claims (5)

(57) [Claims] 1. A unit from a certain scanning line to a scanning line advanced by a certain number of K as a unit block, and the amount of change in correction data of the unit block is divided into a multiple portion of the number K of scanning lines and a portion less than K. For a multiple part of the K, a fixed number is added to the correction value every clock, and for a part less than the K, a straight line generation method by digital difference analysis is used. A correction waveform characterized by controlling whether 1 is added to a correction value or not to a value of 2 or less, and processing a waveform in which a change in correction data is larger than the number of scanning lines K. Generator. 2. A memory which stores M kinds of corrected waveform data and has at least 3-bit parallel output, and M registers connected in parallel, and reads / writes any one register by a register selection signal. A first input A connected to at least one bit of the output of the register group and the memory, a second input W connected to the output of the first register group, and a third input connected to a constant value K. Input K of
A first output U and a second output B, wherein when the value of the first input A is greater than or equal to the value of the second input W, the value A- W, outputting a value 0 to the second output B, and when the value of the first input A is smaller than the value of the second input W, the value A−W + K to the first output U; A first arithmetic circuit composed of a logic circuit that outputs a value 1 to the output B of the second and a M number of registers are connected in parallel, and a second operation of reading and writing an arbitrary register by a register selection signal A group of registers, a first input E connected to at least one bit of the output of the memory, and a second input E connected to one bit of the memory output.
, A third input V connected to the output of the second register group, a fourth input C connected to a second output B of the first arithmetic circuit, and an output Y. When the value of the second input S is 0, the value V + E + C is output to the output Y. When the value of the second input S is 1, the value VEC is output to the output Y. When the second arithmetic circuit and the first selection signal are valid, and when the first selection signal is valid, an arbitrary constant value equal to or less than the constant value K is selected, and when the first selection signal is invalid, A first selector for selecting a first output U of the first arithmetic circuit and outputting the selected output to the first register group; and selecting all outputs of the memory when a second selection signal is valid. A second selection circuit that selects the output Y of the second arithmetic circuit when the second selection signal is invalid, and outputs the output to the second register group. An address signal for the memory, a common register selection signal and a common clock signal for the first register group and the second register group, a first selection signal to the first selector, And a timing generating circuit for generating a second selection signal to the second selector. 3. A series of 0-th to N-th blocks in which M types of original correction waveforms each having a value of 0 or a positive integer are sampled for each K clock signal from the start point of the waveform with the clock signal as a time reference. With respect to the M sets of correction values, the 0th block correction values are stored as they are as one word data in the M sets of correction values in the memory, and the correction values of the first to Nth blocks are , The change amount D for each of the correction values of the immediately preceding block is represented by a constant value K, a variable p having a value of 1 or −1, a variable E having an integer value, and a variable A having an integer value, D = p ( EK +
A), the 1-bit variable S indicating the sign of the variable p and the three variables E and A are expressed by M
3. The correction waveform generator according to claim 2, wherein each set is combined with one word of data and stored in the memory as a correction value of M sets × N blocks. 4. A first arithmetic circuit comprising: a subtractor having a subtrahend input and a subtrahend input, a subtraction output, and a decrement output; and a first adder having first and second inputs and an addition output. , An input and an output, and a gate circuit having a control input, wherein the minuend input of the subtractor is the first input A of the first arithmetic circuit, and the subtraction input of the subtractor is the second input A of the first arithmetic circuit. , The input of the gate circuit is the third input K of the first arithmetic circuit, the output of the first adder is the first output U of the first arithmetic circuit, An output is a second output B of the first arithmetic circuit, an output of the gate circuit is a first input of the first adder, and a subtraction output of the subtractor is a second output of the first adder. The input of the subtractor and the control output of the gate circuit, 3. The correction waveform generator according to claim 2, wherein the correction waveform generator is connected to be a second input C of the arithmetic circuit. 5. A second arithmetic circuit, comprising: a second adder having a first input and a second input; an addition output; a two's complementer having an input and an output; A third selector having an input, a second input, an output, and a control input; and a third adder having a first input, a second input, and an addition output. The first input is a first input E of a second arithmetic circuit, the second input of the second adder is a second input C of a second arithmetic circuit, and the control of the third selector An input is a second input S of the second arithmetic circuit, a second input of the third adder is a third input V of the second arithmetic circuit, and an addition output of the third adder is The output Y of the second arithmetic circuit is used as the output of the second adder.
, The output of the third selector as the first input of the third adder, and the output of the two's complementer as the second input of the third selector. 3. The correction waveform generator according to claim 2, wherein the correction waveform generator is connected to the correction waveform generator.