JPH07105938B2 - Motion vector detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Industrial field of application) The present invention detects the amount of movement between frames of a video signal and electrically reverse-corrects the vibration of the screen to reduce the vibration component. The present invention relates to a motion vector detection circuit that is used for removal or for motion correction processing for still image processing.

(Prior Art) In order to detect the amount of image movement between frames, it is ideal to calculate in which direction all pixels in the image have moved and in what direction, and there is no more vector detection accuracy. . However, it requires a large amount of hardware and time, and is difficult to realize. Therefore, generally, a method of focusing on some pixels (hereinafter referred to as representative points) of the screen and determining a vector of the entire screen from the movement amount of these pixels is adopted.

FIG. 6 is a block diagram of a general representative point arithmetic circuit.
The input video signal 10 is input to the representative point memory 11, and a predetermined pixel in the block written therein becomes a representative point. On the other hand, the output of the representative point memory 11 is the representative point written one frame before, and this is read in block units. The video signal 10 input into this block and the representative point are subtractor 12
Is calculated by These are performed for blocks of the number of representative points, and the output signal 13 is added to the same address of each block one after another, and finally the position of the image representative point of one frame is moved in which direction by one block address and the addition result. That is, the vector value is decided.

FIG. 7 shows the relationship between the image block and the representative point in the above general representative point calculation. It is shown that the calculation of the pixel 22 input into the block 21 and the representative point level is performed in each block based on the representative point 20 extracted one frame before. Here, one block centering on the representative point indicates the size of the vector, that is, the range in which the image can be corrected by the vector. Therefore, if the block is made large and the vector detection range is widened, the total number of representative points on the screen is reduced. This means that the error signal is probably included in the result of cumulative addition and the vector detection accuracy is reduced. Will lead to a decline.

Therefore, as shown in FIG. 8, a method of arranging the configurations shown in FIG. 6 in parallel has been considered. That is, it is a method of arranging the representative points by shifting in the horizontal direction (H) or the vertical direction (V). The input signal 30 is calculated by the representative point calculator of 31, 32, 33, 34 to obtain outputs 35, 36, 37, 38. These output signals have a block delay in the horizontal or vertical direction, and in the subsequent cumulative addition, the addition is repeated for each address of the block.

FIG. 9 shows the arrangement of the representative points in the configuration shifted in the horizontal direction. If the representative point 40 of the H1 arithmetic unit and the representative points 41, 42 and 43 of H2, H3 and H4 are arranged as shown in the figure,
As shown in Figure 10, the density of representative points can be increased. FIG. 11 shows the arrangement of the representative points in the structure shifted in the vertical direction. 50 representative points of V1 arithmetic unit, also V2, V3,
When the representative points 61, 62 and 63 of V4 are arranged as shown in the figure, the density of the representative points can be increased as shown in FIG.

In order to perform these calculations at the same time, the configuration shown in FIG. 13 can be considered. The H1, H2, H3, and H4 calculation units perform horizontal representative point calculation, and the V1, V2, V3, and V4 calculation perform vertical representative point calculation. Cumulative addition of these output signals by matching the address in the block of each representative point 88, 89,
Take 90.

However, in the conventional motion vector detection circuit having the above-mentioned configuration, although the density of the representative points can be increased, the cumulative addition is complicated, and thus the hardware is inevitably large.

(Problems to be Solved by the Invention) As described above, in the conventional motion vector detection circuit, in order to expand the vector detection area and increase the number of representative points, the horizontal and vertical directions are used as the representative point calculation means. Since the representative point blocks are delayed and overlapped, the cumulative addition becomes complicated and the hardware becomes large in scale.

The present invention has been made to solve the above problems,
Cumulative addition is relatively easy, the hardware is small, and the number of representative points can be increased for calculation.
An object is to provide a motion vector detection circuit with high vector detection accuracy.

[Structure of the Invention] (Means for Solving the Problems) That is, the motion vector detection circuit according to the present invention has the same size by shifting a predetermined number of pixels in each of the vertical and horizontal directions so as to partially overlap in the screen. Of a plurality of blocks, set a representative point for each block, and group the representative points arranged in one direction in the vertical direction or the horizontal direction. In the representative point storage unit that holds the representative points of 1 frame for one frame, a plurality of in-block comparison operation units that read out different representative points from the representative point storage unit and perform a comparison operation with the pixels in the corresponding block. A plurality of intra-group arithmetic processing units having an accumulative addition unit for accumulatively adding the comparative arithmetic data in the detected plural blocks, and detection of these intra-group arithmetic processing units. Results and full-screen processing unit for cumulatively adding the configured by and a moving amount detecting means for determining the pixel shift amount of the entire screen from the cumulative addition result obtained by the full-screen processing unit.

(Operation) In the motion vector detection circuit having the above-described configuration, the blocks are specified by shifting them by a predetermined number of pixels in the vertical and horizontal directions so as to partially overlap each other, and the number of representative points is set by setting a representative point in each block. This increases the accuracy of motion vector detection. Specifically, in the vertical direction,
Representative points arranged in any one of the horizontal directions are grouped, and first, in each group, a representative pixel is compared with corresponding pixels in the block, and cumulative addition is performed by cumulative addition, Then, the cumulative addition value in each block is cumulatively added to obtain the cumulative addition value in the group. Further, the cumulative addition value of the entire screen is obtained by cumulatively adding the cumulative addition values in each group, and the motion vector of the entire screen is detected from the cumulative addition value of the entire screen. At this time, in each group,
By storing a plurality of representative points in a storage unit (memory), sequentially reading the representative points from the storage unit, and obtaining the cumulative addition value in each block in the group, the number of memories can be reduced and The cumulative addition value in each block is cumulatively added, and then the cumulative addition value in each group is cumulatively added to simplify the cumulative addition configuration.

(Embodiment) An embodiment of the present invention will be described below with reference to FIGS. 1 to 5.

FIG. 1 shows the overall structure thereof, and is a structure in which the same result as the conventional circuit shown in FIG. 13 can be obtained. That is, the arithmetic units 91, 92, 93, 94 fix the horizontal representative points at the positions H1, H2, H3, H4 shown in FIG. 10, and shift them in the vertical direction shown in FIG. It calculates the representative points of V1, V2, V3, and V4. Based on these V1, V2, V3, and V4, vertical calculation is performed for each block, and their outputs are delayed and added. Then output. These calculation units 91, 9
The outputs of 2,93,94 are aggregated into one block after the respective delays of H1, H2, H3, and H4 are added in the accumulator 95, and the output line
Sent to 96.

FIG. 2 shows a representative point arrangement with the configuration shown in FIG.
The representative points calculated by the calculation unit 91 are (H1, V1), (H1, V
2), (H1, V3), (H1, V4), the representative points calculated by the calculation unit 92 are (H2, V1), (H2, V2), (H2, V3), (H2, V
4), the representative points calculated by the calculation unit 93 are (H3, V1), (H
3, V2), (H3, V3), (H3, V4), the representative points calculated by the calculation unit 94 are (H4, V1), (H4, V2), (H4, V3), (H4, V
4). Representative points are arranged in all the blocks at these densities, and the respective calculation units perform calculation in the vertical direction for each block.

FIG. 3 is a circuit diagram showing one configuration of the arithmetic unit shown in FIG. In FIG. 3, an input video signal 110 passes through a latch circuit 111, is input to a representative point memory 112, and is simultaneously input to an adder 115 to be operated with a representative point. In the representative point memory 112, every n / 4 lines (n: the number of lines in one block), one pixel is written in a horizontal block, and four representative points are read in the vertical direction at the same time in reading. As a result, the input pixels are calculated with different representative point levels in the vertical direction.

For example, in the calculation unit 91, for the input video signals of the blocks A, B, C, and D, the representative points (H
1, V1) level and the adder 115A performs calculation, and for the video signal input to the block B, the representative point (H1, V
Calculation is performed in the level of 2) and the adder 115B. The same applies to blocks C and D. Each representative point level is read from the representative point memory 112, and the latch circuit 113
The data is read by the latch circuits 114A to 114D via A to 113D, and these readings are instructed by the memory address control circuit 118. These commands are issued in synchronization with the television sync signal SV.

As a result of the above calculation, the address of the block is delayed by n / 4 lines. Therefore, the adder 116A, 1 that delays them and adds them to the next operation output is added.
By repeating the addition operation with 16B and 116C, the final addition output 117
Is equal to four cumulative additions in the vertical direction. The same is done in the other arithmetic units 92, 93, 94.

A memory address control circuit 118 for controlling the representative point memory 112 will be described with reference to FIGS. 4 and 5.

FIG. 4 shows the writing control of the representative point pixel in the representative point memory 112. Reference numeral 122 is an input address signal to the memory, and a portion between 120 and 121 indicates one horizontal block. The first half of this horizontal block is used as a write address area, and X, Y, and Z indicate addresses at which representative points are written. The representative point for writing is x0, y0, z0 indicated by 125, for example x
0 is taken as the representative point in the block immediately before the 120 and 121 blocks. 123 and 124 are write control signals.
Control signal of x0 to the X address, y0 to the Y address,
The representative point of z0 is written in the Z address. Further, as shown by 124, writing is prohibited on the line not taken up as a representative point. Here, one pixel at the center of the horizontal block is written as a representative point for every n / 4 lines.

Next, referring to FIG. 5, the reading control of the representative point in the representative point memory 112 will be described.

130 to 131 indicate one horizontal block. Since the latter half of this horizontal block is used as a read address area and four representative points are read here, addresses A, B, C and D are given to the representative point memory 112. In this address period, the memory 112 is brought into a read state. The latch circuit 113 at the output stage of the representative point memory 112 in FIG.
Then, the representative point shown at 132 is latched.
The clock e is applied to the subsequent latch circuit 114, and the representative point for each block shown in 133 is prepared. The calculation of these representative points and the input signal is performed by the adder 115.

These four representative points in the vertical direction are pixels arranged in every n / 4 line. Therefore, it is clear from the fact that the representative point is located at the center of the block that the input pixels calculated as a0, b0, c0, d0 shown in FIG. Therefore, a0, b0, c0, d0
Are delayed by n / 4 lines, and it is necessary to hold them for n line periods.

With the above memory control, the configuration has been shown in which four representative points are read at one time, but the number of representative points can be further increased if there is a margin in the period excluding the writing period within one horizontal block. Is. As an example, an address for reading out the eight representative points is shown at 134 in FIG.

Further, by applying the above configuration, it is possible to shift the representative point in the horizontal direction and perform the same as above to detect the vector of the entire screen.

Therefore, the motion vector detection circuit having the above configuration is
The number of representative points can be increased without increasing the hardware of the representative point calculation unit for detecting the motion vector, and the process of cumulative addition is also simple. Also, as is clear from FIG. 3, since the circuit operates repeatedly,
It has an advantageous effect for IC conversion.

[Effects of the Invention] As described above, according to the present invention, cumulative addition is relatively easy, the hardware is small, and the number of representative points can be increased to perform calculation. It is possible to provide a high motion vector detection circuit.

[Brief description of drawings]

1 to 5 are views for explaining one embodiment of a motion vector detecting circuit according to the present invention, respectively. FIG. 1 is an overall configuration diagram, FIG. 2 is a diagram showing representative point arrangement, and FIG. FIG. 4 is a circuit diagram showing the configuration of the arithmetic unit of FIG. 1, FIGS. 4 and 5 are timing charts for explaining the operation of the same embodiment,
FIG. 6 is a block diagram of a conventional general representative point arithmetic circuit, FIG.
FIG. 8 is a diagram showing the positional relationship between the screen and the representative points in the calculation of FIG. 6, FIG. 8 is a circuit diagram showing the configuration for increasing the representative points, and FIG. 9 is the configuration of FIG. 8 in the horizontal direction. FIG. 10 is a diagram showing the positional relationship between the blocks and the representative points when they are displaced, FIG. 10 is a diagram showing that the number of representative points in the horizontal direction is increased, and FIG. 11 is a diagram showing the arrangement in the vertical direction in the configuration of FIG. Showing the positional relationship between the blocks and the representative points, FIG. 12 shows an increase in the number of representative points in the vertical direction as a whole, and FIG. 13 shows a configuration for increasing the representative points in the horizontal and vertical directions. It is a block diagram. 10 …… input video signal, 11 …… representative point memory, 12 …… subtractor, 13 …… computation output signal, 14,15,16 …… latch circuit, 20
...... 1 frame before the representative point, 21 ...... Block, 22 ...... Representative point level to be compared with input, 30 ...... Input video signal, 31, 3
2,33,34 ...... Representative point calculation unit, 35,36,37,38 ...... Representative point calculation output signal, 40,41,42,43 ...... Representative points arranged horizontally offset, 60,61, 62,63 …… Representative points displaced vertically, 80,81,82,83 …… Representative point calculation unit in the horizontal direction, 84,8
5,86,87 …… Vertical direction representative point calculation unit, 88,89,90 …… Cumulative addition unit, 91,92,93,94 …… Calculation unit, 95 …… Cumulative addition unit, 96 …… Cumulative addition Output, 110 ... Input video signal, 111 ...
Input signal latch, 112 ... Representative point memory, 113 ... Representative point read data latch, 114 ... Representative point for each block, 1
15 ... Adder, 116 ... Circuit for adding delays of representative point calculation output together, 117 ... Cumulative addition output, 118 ... Memory address control section, 122 ... Address signal, 123, 124 ... Write control signal, 125 …… Write data, 120,121,130,131
...... Block address change point, 132 …… Memory output by the representative point latch, 133 …… Representative point for each block, 134 ……
Memory address (when there are 8 representative points).

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Minoru Abe Minoru Abe, Komukai Toshiba Town, Kouki-ku, Kawasaki City, Kanagawa Prefecture Komu Factory, Toshiba Corporation (72) Kenjiro Kai, 2-2 Jinnan, Shibuya-ku, Tokyo No. 1 Inside the Japan Broadcasting Corporation Broadcasting Center (72) Inventor Shigeru Ujihara 2-2-1 Jinnan, Shibuya-ku, Tokyo Inside the Japan Broadcasting Corporation Broadcasting Center (72) Inventor Yuuo Kajo 2-2 Minami, Shibuya-ku, Tokyo 2-1 In the Japan Broadcasting Corporation Broadcast Center (72) Inventor Katsunori Chiba 2-2-1, Jinnan, Shibuya-ku, Tokyo Inside the Japan Broadcasting Corporation Broadcast Center (72) Inventor Masayuki Fukuda 2-Jinnan, Shibuya-ku, Tokyo 2-1 Broadcasting Center of Japan Broadcasting Corporation (56) References JP-A-61-201587 (JP, A)

Claims (1)

[Claims] 1. A plurality of blocks having the same size are specified by shifting a predetermined number of pixels in the vertical and horizontal directions so as to partially overlap each other in a screen, and a representative point is set for each block. Representative points arranged in one of the horizontal directions are grouped, and the representative point storage unit is provided for each group and holds the representative points in the group for one frame, and the representative point storage units are different from each other. A plurality of in-block comparison operation units that read out representative points and perform a comparison operation with the pixels in the corresponding block, and a plurality of cumulative addition units that cumulatively add the comparison operation data in the plurality of blocks detected by these comparison operation units Intra-group arithmetic processing unit, full-screen arithmetic processing unit that cumulatively adds detection results of these intra-group arithmetic processing units, and cumulative addition result obtained by this full-screen arithmetic processing unit. Motion vector detecting circuit and a moving amount detecting means for determining the pixel shift amount of the entire screen from.