JPH08237521A - Flaw correcting circuit for solid-state image pickup element - Google Patents

Abstract

PURPOSE: To perform the efficient flaw correction of a solid-state image pickup element with small scale configuration. CONSTITUTION: A picture dividing circuit 49 divides a picture into plural areas from high-order bits 39 of horizontal information from a horizontal counter 15 and an adder 37 and high-order bits 45 of vertical information from a vertical counter 21 and an adder 43. Memories 59 and 69 respectively store flaw position information and flaw presence/absence information for each area and switches 67 and 77 successively select that information from the memories 59 and 69 corresponding to an output 51 of the picture dividing circuit 49 and supply it to a comparator 79 and an AND circuit 83. Low-order bits 41 and 47 of the horizontal information and the vertical information are inputted to the comparator 79 and compared with the flaw position information and when they are matched, a pulse 81 is supplied to the AND circuit 83. When there is any flaw, the AND circuit 83 supplies an output 85 to a switch 95. When there is the output 85, the switch 95 outputs an output 93 of an interpolate signal generating circuit 91 but when there is no output 83, a source signal 89 of the solid-state imaging device is outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a defect correction circuit for a solid-state image pickup device.

[0002]

2. Description of the Related Art In the conventional flaw correction of a solid-state image pickup device, the absolute position of the flaw or the relative position of the flaw is temporarily written in an external ROM, and this information is read into an internal memory using a dedicated interface (I / F). There is. The absolute position of the scratch is a case where the position of the scratch corresponding to the scanning position is described in the external ROM as it is. The relative position of the scratch is a case where the distance from the scratch to the scratch is described in the external ROM.

FIG. 7 shows a first conventional flaw correction circuit. In the external ROM 119, the position of the scratch corresponding to the scanning position is described as it is. External ROM 11
9 reads the stored contents according to the address 117 from the address counter 115, and the dedicated interface (I / I
F) 123 to the internal memory 125. The internal memory 125 is composed of registers corresponding to the number of flaws, and the position information of the flaws is stored in each register, and the position information 127, 129, 131 of each flaw is stored in the comparators 133, 135, 137 having the number of flaws. Supply each.

The input terminal 101 is supplied with a master clock 103 for driving the solid-state image pickup device and the video camera signal processing circuit. The horizontal counter 105 counts the clock 103, outputs horizontal information (address) 107, and outputs the clock 10 every time one horizontal period of the screen is counted.
9 is supplied to the vertical counter 111. Vertical counter 11
1 counts the clock 109 and outputs vertical information (address). The horizontal information 107 and the vertical information 113 are
It is supplied to the comparators 133, 135, 137.

Each of the comparators 133, 135, 137 has horizontal information 107, vertical information 113, and positional information 127 for scratches.
129 and 131 are compared, and if they match, a pulse is supplied to the OR circuit 139. Output 1 from OR circuit 139
If there is 41, it means that there are scratches.

An original signal 145 from a solid-state image sensor (not shown) is input to the input terminal 143. Original signal 145
Is supplied to the first input terminal of the switch 151 and is also supplied to the interpolation signal generation circuit 147. The interpolation signal generation circuit 147 interpolates the original signal 145, and
51 to the second input terminal.

The switch 151 selects the first input terminal when the output 141 from the OR circuit 139 does not exist, and selects the second input terminal when the output 141 exists, and the defect-corrected signal 1 is selected.
51 is output to the output terminal 155.

This conventional flaw correction circuit has the following drawbacks. Since the information supplied from the external ROM 119 to the internal memory 125 is the data of the entire screen, a dedicated interface is required. As many comparators as scratches are required. The scratches on the screen are noticeable at the center of the screen, but no attention is paid to the scratches at the center of the screen.

FIG. 8 shows a second conventional flaw correction circuit. The external ROM 213 describes the relative position information of scratches on the entire screen. The external ROM 213 reads the stored contents according to the address 211 from the address counter 209, and the dedicated interface (I / F) 217
Is supplied to the internal memory 219 via the. Internal memory 2
19 is composed of registers corresponding to the number of relative positions of scratches, and the relative positions of the scratches are stored in each register.
The relative position information 221, 223, 225 of each flaw is output.

The first switch 227 sequentially selects the relative position information 221, 223, 225 of the scratch by the output 235 from the scratch number counter 233 described later and supplies it to the comparator 229.

The aforementioned master clock 203 is supplied to the input terminal 201. Counter 205 is clock 2
03 is counted and the count value 207 is output to the comparator 229. The comparator 229 outputs the pulse 2 when the predetermined count value and the relative position information 221, 223, 225 match.
31 is output. The counter 205 returns to the initial value based on the input of the pulse 231, and restarts the counting operation. The flaw number counter 233 outputs a signal 235 each time the pulse 231 is input.

This conventional flaw correction circuit also has the following drawbacks. Since the amount of data supplied from the external ROM 213 to the internal memory 219 is large, a dedicated interface is required. In addition to a horizontal counter and a vertical counter that generate a synchronization signal, counters 205 and 2 for correcting a flaw
33 is needed. In this conventional example as well, no attention is paid to scratches at the center of the screen.

[0013]

The conventional flaw correction circuit has a large-scale circuit configuration and does not pay attention to flaws in the center of the screen.

It is an object of the present invention to provide a flaw correction circuit that efficiently performs flaw correction with a small-scale configuration.

[0015]

A scan information generating means for generating scan information from a clock input, a screen dividing means for dividing a screen into a plurality of areas by the scan information from the scan information generating means, and each of the areas. First memory means for storing the positional information of the scratch, and first selecting means for selecting and outputting the positional information of the scratch of the corresponding area from the first memory means by the output from the screen dividing means, It comprises a comparison means for comparing the scan information from the scan information generating means with the position information of the scratch from the first selecting means, and the output of the comparing means is the original signal from the solid-state image sensor or the original signal. Select whether the signal is an interpolated signal.

[0016]

The scanning information generating means generates scanning information from the input clock. The screen dividing unit divides the screen into a plurality of areas according to the scan information (upper bits) from the scan information generating unit.

The first memory means stores the positional information of the scratch for each of the areas measured earlier.

The first selecting means selects the positional information of the flaw of the corresponding area from the first memory means by the output from the screen dividing means and supplies it to the comparing means. The comparing means compares the scanning information (lower bit) from the scanning information generating means with the position information of the flaw to determine whether or not the positions match.

The output of the comparison means selects the original signal from the solid-state image pickup device or an interpolation signal obtained by interpolating the original signal. Thereby, the flaw is corrected.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a flaw correction circuit of the present invention. The input terminal 11 is supplied with a mask clock 13 for driving a solid-state image sensor (eg, CCD) and a video camera signal processing circuit. The horizontal counter 15 counts the clock 13 and outputs horizontal information (address) 17. Horizontal counter 1
5 also supplies the clock 19 to the vertical counter 19 every time one horizontal period of the screen is counted. Vertical counter 2
1 counts the clock 19 and outputs vertical information (address) 23.

The synchronizing signal generating circuit 25 uses the horizontal information 17 and the vertical information 23 to generate various synchronizing pulses 27 according to the broadcasting system.
Through 35 are generated.

The first adder 37 adds the first to the horizontal information 17.
The constant K1 of is added. The second adder 43 adds the second constant K2 to the vertical information 23. Thus the constant K1
And K2 are added in the horizontal information at the center of the screen.
And to invert the most significant bit (MSB) of the vertical information 23.

The upper bits 39 and 45 of the output signals of the first and second adders 37 and 43 are supplied to the screen division circuit 49, and the lower bits 41 and 47 are supplied to the comparator 79.

The screen division circuit 49 divides the screen into a plurality of areas from the upper bits 39 of the horizontal information and the upper bits 45 of the vertical information. Examples of screen division are shown in FIGS. 2 to 6. As can be seen from FIGS. 2 to 6, the central part of the screen is subdivided into small regions. Output signal 51 of screen division circuit 49
Is supplied to the control terminals of the first and second switch means 67 and 77. The output signal 51 is also output via the output terminal 53 and is used for controlling the iris, the integrator for white balance and the like.

The position information of scratches is measured in advance for each of the areas divided by the screen division circuit 49, and the position information of the scratches for each area and the information 5 as to whether or not there are any flaws in each area 5
7 is supplied to the internal memories 59 and 69 for the scratch position and presence / absence of the scratch via the interface 55. The data input to the interface 55 is position information (all bits) of the entire screen in the past, but the present invention is position information (lower bits) for each area. Therefore, the interface 55 can use the original signal processing interface.

The scratch position internal memory 59 is composed of, for example, registers corresponding to the number of divided areas, and stores the scratch position information 61, 63, and 65 in each register, and the input terminal of the first switch means 67. Output to. The scratch presence / absence internal memory 69 is composed of, for example, registers of the number of divided areas, and stores the presence / absence information of flaws 71, 73, and 75 in each register, and at the input terminal of the second switch means 77. The position information of the scratch and the presence / absence information of the scratch may be stored in one register at the same time.

The first switch means 67 sequentially selects the position information 61, 63, 65 of the input flaws by the output signal 51 from the screen division circuit 49 and supplies it to the comparator 79. The lower bit 41 of horizontal information and the lower bit 47 of vertical information are also input to the comparator 79. Comparator 79
Compares the three inputs and supplies a positive pulse 81 to the AND circuit 83 when they match.

The second switch means 77 sequentially selects the presence / absence information 71, 73, 75 of the input flaws by the output signal 51 from the screen division circuit 49 and supplies it to the AND circuit 83.

The AND circuit 83 has a defect presence / absence information 71,
An output signal 85 is output when 73 and 75 are at a high level indicating that there are scratches. In this way, the AND circuit 83
Are provided to prevent malfunction. Incidentally, AN
The gate circuit is not limited to the D circuit 83 and may be any gate circuit. At this time, the polarity of the output pulse of the comparator 79 and the polarity of the flaw presence / absence information can be arbitrarily selected.

An original signal 89 from a solid-state image sensor (not shown) is input to the input terminal 87. The original signal 89 is supplied to the first input terminal of the third switch means 95 and the interpolation signal generating circuit 91. The interpolation signal generation circuit 91 interpolates the original signal 89 to generate an interpolation signal 93 and supplies the interpolation signal 93 to the second input terminal of the third switch means 95.

The third switch means 95 is an AND circuit 8
The output 85 from 3 selects the first input terminal or the second input terminal. In other words, the first place where there is no scratch
The second input terminal is selected as the input terminal of No. 2 where there is a flaw, and the flaw-corrected signal 97 is output to the output terminal 99.

In the present embodiment, one point of flaw correction is realized in one area. However, when several points of flaw correction are performed in one area, the internal memories 59 and 69, the comparator 79 and the AN are used.
The number of D circuits 83 may be used.

In the past, as many comparators as required for the number of flaws were required, but in the present invention, only the number of flaw corrections for the divided areas is required. Further, the counter requires a horizontal counter 15 and a vertical counter 21, which are originally those used for the synchronization signal generating circuit 25. Furthermore, by dividing the screen central portion into small areas, it is possible to correct the flaw in the most prominent screen central portion.

[0034]

According to the present invention, it is possible to efficiently perform flaw correction with a small scale configuration.

[Brief description of drawings]

FIG. 1 is a block diagram showing a defect correction circuit of the present invention.

FIG. 2 is a diagram showing an example of screen division.

FIG. 3 is a diagram showing an example of screen division.

FIG. 4 is a diagram showing an example of screen division.

FIG. 5 is a diagram showing an example of screen division.

FIG. 6 is a diagram showing an example of screen division.

FIG. 7 is a block diagram showing a conventional flaw correction circuit.

FIG. 8 is a block diagram showing a conventional flaw correction circuit.

[Explanation of symbols]

15 ... Horizontal counter, 21 ... Vertical counter, 25 ... Sync signal generating circuit, 37 ... First adder, 43 ... Second adder, 49 ... Screen dividing circuit, 59 ... Scratch position internal memory, 67 ... 1 switch means, 69 ... Internal memory for existence of scratches, 77 ... Second switch means, 79 ... Comparator, 8
3 ... AND circuit, 91 ... Interpolation signal generating circuit, 95 ... Third
Switch means.

Claims (7)

[Claims] 1. A scan information generating means for generating scan information from a clock input, a screen dividing means for dividing a screen into a plurality of areas based on the scan information from the scan information generating means, and positional information of scratches for each area. A first memory means for storing the information, a first selecting means for selecting and outputting the positional information of the scratch of the corresponding area from the first memory means by the output from the screen dividing means, and the scanning information generation Comparing means for comparing the scanning information from the means with the positional information of the flaw from the first selecting means, and the output of the comparing means is the original signal from the solid-state image sensor or the original signal is interpolated. A defect correction circuit for a solid-state image pickup device, characterized in that it is selected as an interpolation signal. 2. The scanning information generating means, a horizontal counting means for measuring the clock input, a first adding means for adding a first constant to the horizontal information from the horizontal counting means, and the horizontal counting means. 2. The scratch of the solid-state image pickup device according to claim 1, further comprising: a vertical counting unit that measures the output of the solid state image pickup device; and a second adding unit that secondly adds a constant to the vertical information from the vertical counting unit. Correction circuit. 3. The high-order bit in the output of the first adding means and the high-order bit in the output of the second adding means are input to the screen dividing means. Item 2. A defect correction circuit for a solid-state image sensor according to item 2. 4. The comparison means is inputted with the lower bits of the output of the first adding means and the lower bits of the output of the second adding means. A defect correction circuit for the solid-state image pickup device according to 2 or 3. 5. The first memory means stores defect presence / absence information for each area, and the defect presence / absence information of the corresponding area from the first memory means is output by the screen dividing means. 5. A second selection means for selecting and outputting the signal, and a gate means for receiving the output of the comparison means and the output of the second selection means. Any one of the defect correction circuits of the solid-state image sensor. 6. A second memory means for storing defect presence / absence information for each area, and the defect presence / absence information of the corresponding area is selected from the second memory means by an output from the screen dividing means. 2. A second selection means for outputting, and a gate means for comparing the output of the comparison means with the output of the second selection means.
4. A defect correction circuit for a solid-state image sensor according to any one of 4 to 4. 7. The screen dividing means divides the screen central portion into areas having a small area when dividing the screen into a plurality of areas. A defect correction circuit for a solid-state image sensor.