JPH0566965A - Break signal generating means, evaluating logical lsi, and register and mask bit of lsi - Google Patents

Abstract

PURPOSE:To increase the response speed of a break signal together with prevention of the increase of area of a logical LSI for mass production by building a break signal generating circuit that is so far built in an ICE (i-circuit emulator) into an evaluating logical LSI-only logical part of an evaluating logical LSI. CONSTITUTION:The desired conditions to be broken are previously set to a break point setting register 104 through an ICE data bus 202. When a logical LSI 102 for mass production is actuated, the value is outputted to an address bus 201. This value is compared with the break conditions by a comparator 107. Then a break signal is outputted through a break signal line 200 when the coincidence is obtained between the output value and the break conditions. Then the response speed of the break signal is increased owing to a short distance set between the LSI 102 and a break signal generating signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic LSI such as a microprocessor having a built-in program debug function, and in particular, it enables quick response of a break signal without increasing the area of a mass production microprocessor. Regarding the logic LSIs.

[0002]

2. Description of the Related Art Support hardware ICE (In Circui) for program debugging of a conventional microprocessor
t Emulator), for example, a single-chip microcomputer
ASE for HD6475328 is known.

In this example, an explanatory view of hardware for realizing a break function for stopping the execution of the user program is shown in FIG. The hardware for realizing the break function shown in FIG. 3 includes an evaluation logic LSI 101 and an ICE main unit 109.

The mass production logic LSI 101 is an evaluation logic L.
It is composed of an SI dedicated logic section, a bonding pad 108 of an evaluation logic LSI, and a mass production logic LSI 102. The mass production logic LSI 102 incorporates an internal logic circuit and a bonding pad 103 for the mass production logic LSI. The ICE main unit 109 includes a break signal generation circuit 10
Built-in 0. The break signal generation circuit 100 includes a break point setting register 104 and an AND circuit 10.
5, 106 and a comparator 107.

From the mass production logic LSI 102, the mass production logic LSI bonding pad 103, the evaluation logic LSI dedicated logic section, and the evaluation logic LSI bonding pad 10 are formed.
8, the address bus 201 is connected to the comparator 107 in the break signal generation circuit 100. The address decode line 203 for the breakpoint setting register generated in the ICE main unit 109 is the AND circuit 105,
It is connected to 106. The read signal line 204 generated in the ICE main unit 109 is connected to the AND circuit 105. The write signal line 205 generated in the ICE main unit 109 is connected to the AND circuit 106. A
From the ND circuit 105, the signal line 206 is connected to the breakpoint setting register 104. AND circuit 1
From 06, the signal line 207 is connected to the breakpoint setting register 104.

The ICE data bus 202 is connected to the breakpoint setting register 104. A signal line 208 is connected to the comparator 107 from the breakpoint setting register 104. From the comparator 107, the break signal line 200 is connected to the bonding pad 108 of the evaluation logic LSI, the evaluation logic LSI dedicated logic section, and the mass production logic L.
Mass production logic L through SI bonding pad 103
It is connected to SI102.

FIG. 4 shows a time chart of the circuit shown in FIG. The address decode line 203 for break point setting register and the write signal line 205 are set to high level. Address decode line 20 for breakpoint setting register
The write signal line 205 is a valid signal line at high level. The output signal line 207 from the AND circuit 106 is
High level. In this state, the value of the address to be broken is set in the break point setting register 104 from the ICE data bus. The operation up to this point is shown in FIG.
Not shown in. From the mass production logic LSI 102 to FIG.
Address bus 201 output at the timing indicated by A
Value of the break signal generation circuit 1 at the timing of FIG. 4C.
It reaches the comparator 107 in 00. AC in FIG. 4 is a circuit and wiring capacity in the evaluation logic LSI 101, and an evaluation logic L.
This is a delay time caused by two wiring capacities between the SI 101 and the ICE main unit 109. The value of the address bus 201 reaching the comparator 107 is passed through the signal line 208 between CEs in FIG.
Is compared to the value of. When the two values match, the break signal line 20 is released from the comparator 107 at the timing E in FIG.
Output a break signal to 0. Between CEs in FIG. 4 is a decoding time. Break signal line 2 at the timing E in FIG.
When a break signal is output to 00, the break is applied to the mass production logic LSI 102 at the timing G in FIG. The GE shown in FIG. 4 is the setup time, which is generated from the setup time due to the wiring capacity between the ICE main unit 109 and the evaluation logic LSI 101, and the setup time due to the circuit in the evaluation logic LSI 101 and the wiring capacity.

As a second conventional example, a 32-bit microprocessor H32 / 200 (manufactured by Hitachi, Ltd.) is known. The basic configuration diagram is shown in FIG. In this case, the mass production logic LSI 102 includes the CPU main body 110,
The break signal generating circuit 100 and a bonding pad 103 of a mass production logic LSI are included. The configuration of the break signal generation circuit 100 is the same as that of the break signal generation circuit 100 of FIG. The connection relationship is the same as that of FIG. 3 is different from that of FIG. 3 in order to control the break signal generation circuit 100 by the CPU main body 110, in order to control the break point setting register address decode line 203, read signal line 204, and write signal line 20.
5, the data bus 209 is output from the CPU body 110.

FIG. 6 shows a time chart of the circuit shown in FIG. The operation is basically the same as in the case of FIG. However, in FIG. 6, since the delay time and the setup time due to the wiring capacitance between the evaluation logic LSI 101 and the ICE main unit 109 of FIG. 3 are deleted, the response speed of the break signal becomes faster. Therefore, even if the value is output to the address bus 201 at the timing A as shown in FIG. 6, the break signal can be applied at the timing G.

[0010]

In the configuration of the first conventional example, no consideration has been given to the delay of the response speed of the break time due to the delay time of the address signal line and the setup time of the break signal line.

Further, in the configuration of the second conventional example, no consideration has been given to the increase in the LSI area due to the built-in break signal generation circuit in the mass production logic LSI. An object of the present invention is to provide a system in which the response speed of a break signal is increased without increasing the area of a mass production logic LSI.

[0012]

[Means for Solving the Problems] A means for allowing a break signal generation circuit to be controlled from an ICE main unit by incorporating a break signal generation circuit in a dedicated logic part of an evaluation logic LSI, and a mass production LSI completely from a test LSI. The above-mentioned problems are solved by means of making the mask pattern separable.

[0013]

By incorporating the break signal generation circuit controllable from the ICE main unit in the logic unit dedicated to the evaluation logic LSI, the signal delay and the setup time due to the wiring capacity outside the evaluation logic LSI can be shortened. As a result, the response speed of the break signal can be increased.

On the other hand, the break signal generation circuit controllable from the ICE main unit incorporated in the logic unit dedicated to the evaluation logic LSI has a structure capable of being separated from the mask pattern of the mass production logic LSI. This makes it possible to prevent an increase in the area of the mass-produced logic LSI.

[0015]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. FIG. 1 shows an evaluation logic LSI 1 capable of increasing the response speed of a break signal while preventing an increase in the area of a mass production logic LSI.
It is a figure which shows 01.

The evaluation logic LSI 101 is a mass production logic L.
The SI 102, the logic unit dedicated to the evaluation logic LSI, the break signal generation circuit 100, and the bonding pad 108 of the evaluation logic LSI. Mass production logic LSI1
Reference numeral 02 includes an internal logic circuit and a bonding pad 103 of a mass production logic LSI. The break signal generation circuit 100 includes a break point setting register 104,
It is composed of AND circuits 105, 106 and a comparator 107.

The connection relationship is shown below. Mass production logic LSI
From 102, the address bus 201 is connected to the comparator 107 through the bonding pad 103 of the mass production logic LSI. The break point setting register address decode line 203 is connected to the AND circuits 105 and 106. The read signal line 204 is connected to the AND circuit 105. The write signal line 205 is the AND circuit 1
It is connected to 06. The address decode line 203 for the breakpoint setting register 203, the read signal line 204, and the write signal line 205 are directly bonded to the bonding pad of the evaluation logic LSI so as to be directly controllable from the ICE main unit 109) (not shown in FIG. 1). Connected to 108. The output signal line 206 of the AND circuit 105 is connected to the breakpoint setting register 104. A
The output signal line 207 of the ND circuit 106 is connected to the breakpoint setting register 104. In addition, the breakpoint setting register 104 has an ICE data bus 2
03 is connected through the bonding pad 108 of the evaluation logic LSI. Breakpoint setting register 1
From 04, the signal line 208 is connected to the comparator 107. From the comparator 107, the break signal line 200 is connected to the mass production logic LSI 102 through the bonding pad 103 of the mass production logic LSI.

The details of the operation of the present invention will be described with reference to the time chart of FIG.

The break point setting register address decode line 203 and the write signal line 205 are set to the high level. The address decode line 203 for the breakpoint setting register and the write signal line 205 are valid signal lines at a high level. Output signal line 2 from AND circuit 106
07 becomes high level. In this state, the value to be broken from the ICE data bus 202 is set in the break point setting register 104. The operation up to this point is not shown in the time chart of FIG. After setting the values in the breakpoint setting register 104, the evaluation logic LSI 101 is operated. A value is output to the address bus 201 at the timing shown by A in FIG. The output value reaches the comparator 107 at the timing of B in FIG. Between AB in FIG. 2 is a delay time caused by the circuit and wiring capacitance in the chip. The comparator 107 is B in FIG.
At this timing, the value of the address bus 201 input is compared with the value of the breakpoint setting register 104 input via the signal line 208. If both values match, a break signal is output to the break point setting register 200. Break signal is break signal line 200
The timing of outputting to is the timing of D in FIG.
The time (between BD in FIG. 2) until the value of the address bus 201 is input to the comparator 107 and the break signal is output from the break signal line 200 is the decoding time. In order to apply the break signal to the evaluation logic LSI 101 at the timing shown by E in FIG. 2, a setup time (between DEs in FIG. 2) generated by the circuit and wiring capacitance in the evaluation logic LSI 101 is required. In the conventional example, as shown in FIG. 4, the circuit and wiring capacitance in the evaluation chip, the evaluation chip and the IC
E The response speed of the break signal was slow due to the delay due to the wiring capacitance between the main bodies and the setup time.

In the present invention, by implementing the main body chip and the break signal generating circuit on the same chip, the delay and the setup time due to the wiring capacity between the evaluation logic LSI 101 and the ICE main body device can be eliminated, so that the break The signal response speed can be increased. Further, by controlling the break signal generation circuit from the ICE main unit, it is not necessary to provide bonding pads for the logic for the break signal generation circuit and the control signal lines inside the mass production logic LSI, and the mass production logic LSI Area increase can be prevented.

A second embodiment of the break signal generating circuit is shown in FIG. FIG. 7 is a diagram showing an evaluation logic LSI 101 newly provided with a function of masking a break signal. The evaluation logic LSI 101 includes a mass production logic LSI 102, an evaluation logic LSI dedicated logic unit, and a break signal generation circuit 10.
0, a bonding pad 108 of the evaluation logic LSI. The mass-production logic LSI 102 is composed of an internal logic circuit and a bonding pad 103 of the mass-production logic LSI. The break signal generation circuit 100 includes a break point setting register 104, an AND circuit 105,
106, 112, 113, 114, a comparator 107, and a mask bit 111.

The connection relationship is shown below. Mass production logic LSI
From 102, the address bus 201 is connected to the comparator 107 through the bonding pad 103 of the mass production logic LSI. The break point setting register address decode line 203 is connected to the AND circuits 105 and 106. Mask bit address decode line 210
Is connected to AND circuits 112 and 113. The read signal line 204 is connected to the AND circuits 105 and 112. The write signal line 205 is connected to the AND circuits 106 and 113.
It is connected to the. Breakpoint setting register address decode line 203, mask bit address decode line 210, read signal line 204, write signal line 20
5 is an evaluation logic LSI so that it can be directly controlled by the ICE main unit 109 (not shown in FIG. 1).
Connected to the bonding pad 108. AND
The output signal line 206 of the circuit 105 is connected to the breakpoint setting register 104. AND circuit 106
The signal line 207 output from is connected to the breakpoint setting register 104. An ICE data bus 202 is connected to the breakpoint setting register 104. The signal line 211 output from the AND circuit 112 is
It is connected to the mask bit 111. AND circuit 11
The signal line 212 from 3 is connected to the mask bit 111. The ICE data bus 203 is connected to the mask bit 111 through the bonding pad 108 of the evaluation logic LSI. A signal line 208 is connected to the comparator 107 from the breakpoint setting register 104. A signal line 214 is connected to the AND circuit 114 from the comparator 107. Mask bit 11
From 1, the signal line 213 is connected to the AND circuit 114. From the AND circuit 114, the break signal line 20
0 is connected to the mass production logic LSI 102 through the bonding pad 103 of the mass production logic LSI.

The operation will be described. The mask bit address decode line 210 and the write signal line 205 are set to the high level. The mask bit address decode line 210 and the write signal line 205 are valid signal lines at a high level. The output signal line 212 of the AND circuit 113 becomes high level. In this state, a value is set in the mask bit 111 from the ICE data bus 202. When the set value is 1, the subsequent operation is exactly the same as the operation in FIG. When the set value is 0, the comparison match signal output from the comparator 107 to the signal line 214 is masked by the AND circuit 114. Therefore, no break signal is output to the break signal line 200.

Since the present invention realizes the break signal generation circuit outside the mass production logic LSI, the break condition is satisfied, the memory read condition is not limited to the address condition and the mask condition as described above. , Memory write condition, memory area condition, external probe condition, external interrupt condition, delay after break condition is satisfied, break, break when specified condition is not satisfied, sequential break, etc. It can also be applied to multiple break functions while preventing this.

A third embodiment is shown in FIG. FIG. 8 shows a case where the break signal generation circuit is modularized, in which the break signal generation module 115 and the mass production logic LSI 102 are configured on one chip.
The configuration and connection relationship of the break signal generation module 115 are the same as those of the break signal generation circuit 10 shown in the first embodiment.
Basically equal to 0. The difference from the first embodiment is that the break signal generation module 115 is provided with a bonding pad so that the break signal generation module can be controlled from the ICE main unit.

In the case of the third embodiment as well, as in the first embodiment, it is constructed by one chip. The delay time and the setup time due to the wiring capacitance between the chip and the ICE main unit unlike the first conventional example are not required. Therefore, the response speed of the break signal is increased. Further, the break signal generation module is controlled by the ICE main unit.
There is no need for a dedicated signal line or bonding pad for controlling the break signal generation module from the mass production logic LSI. Therefore, the signal lines required to be connected between the mass production logic LSI and the break signal generation module are the address bus 201 and the break signal line 200. Bonding pads for the address bus 201 and the break signal line 200 are provided in all types of CPU bodies.
Therefore, it is not necessary to create a break signal generation module suitable for various mass-production logic LSIs. Also, to connect a break signal generation module, a logic LS for mass production is used.
There is no need to change I. Therefore, it is possible to connect and disconnect the mass production logic LSI and the break signal generation module without performing any special processing at the mask level of the LSI. Further, in the third embodiment, unlike the first embodiment, the bonding pad 10 of the mass production logic LSI is used.
3 can be used as a chip bonding pad. Therefore, the evaluation logic LSI can be realized in an area smaller than that of the first embodiment.

A fourth embodiment is shown in FIG. FIG. 9 shows a case where the break signal generation circuit is made into a chip. The break signal generation logic LSI 116 and the mass production logic LS are shown.
The hybrid IC 117 is configured by combining I102. The configuration and connection relationship of the break signal generation logic LSI 116 are basically the same as those of the break signal generation circuit 100 shown in the first embodiment. The difference from the first embodiment is that the break signal generation logic LSI 116 and the mass production logic L
SI102 is connected by wire bonding,
That is, it is not a single chip.

In the case of the fourth embodiment, unlike the first embodiment, since it is not constructed in one chip, the chip and the IC are
E Delay time between main units and setup time are required. Therefore, the response speed of the break signal is not as high as that of the first embodiment. However, since the break signal generation logic LSI 116 and the mass production logic LSI 102 are very close to each other, the break signal response speed can be increased as compared with the first conventional example. Furthermore, the break signal generation logic LSI 116 of the fourth embodiment is
It is controlled from the main unit. A dedicated signal line for controlling the break signal generation logic LSI from the mass production logic LSI,
Does not require bonding pads. Therefore, the signal lines required to be connected between the mass production logic LSI and the break signal generation logic LSI are the break signal line 215 by wire bonding and the address bus 216 by wire bonding. Address bus 216 by wire bonding, break signal line 21 by wire bonding
Bonding pads for 5 are provided on all kinds of mass-production logic LSIs. Therefore, it is not necessary to create a break signal generation logic LSI suitable for various mass production logic LSIs. A mass production logic LSI and a break signal generation logic LSI are individually manufactured and wire-bonded to form a hybrid IC. When manufacturing like this,
Since an LSI having an area smaller than that of the evaluation logic LSI is manufactured, the yield of the LSI can be improved.

Since the present invention realizes a break signal generation module and a break signal generation logic LSI for generating a break signal outside the mass production logic LSI,
As described above, not only the address condition but also the number of times the mask condition and the break condition are satisfied, the memory read condition, the memory write condition, the memory area condition, the external probe condition, the external interrupt condition, and the delay after the break condition is satisfied. Mass production logic LS, such as breaks by multiplying, breaks when specified conditions are not satisfied, sequential breaks, etc.
It can be applied to the multi-functionalization of the break function while preventing an increase in the area of I.

[0031]

According to the present invention, by incorporating the break signal generation circuit in the logic part dedicated to the evaluation logic LSI,
Since the delay and the setup time due to the wiring capacity between the conventional evaluation logic LSI and the ICE main unit can be eliminated, the break signal response speed can be increased. Furthermore, a break signal generation circuit is added to the mass production logic LSI.
By separating from the above, it is possible to prevent an increase in the area of the mass production logic LSI.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing an evaluation logic LSI including a break signal generation circuit that can be controlled from outside the evaluation logic LSI.

FIG. 2 is a time chart of the circuit of FIG.

FIG. 3 is an explanatory diagram showing a first conventional example.

FIG. 4 is a time chart of the circuit of FIG.

FIG. 5 is an explanatory diagram showing a second conventional example.

6 is a time chart of the circuit of FIG.

FIG. 7 is an explanatory diagram showing an evaluation logic LSI having a built-in break signal generation circuit having break signal mask bits which can be controlled from the outside of the evaluation logic LSI.

FIG. 8 is an explanatory diagram showing an evaluation logic LSI including a break signal generation module that can be controlled from outside the evaluation logic LSI.

FIG. 9 is a break signal generation logic LS that can be externally controlled.
Explanatory drawing which shows the hybrid IC which incorporated I. FIG.

[Explanation of symbols]

100 ... Break signal generation circuit, 101 ... Evaluation logic L
SI, 102 ... Mass production logic LSI, 103, 108 ... Bonding pad, 104 ... Break point setting register, 105, 106 ... AND circuit, 107 ... Comparator,
200 ... Break signal line, 201 ... Address bus, 20
2 ... ICE data bus, 203 ... Address decode line,
204 ... Read signal line, 205 ... Write signal line, 20
6, 207, 208 ... Signal lines.

Claims (6)

[Claims] 1. In an evaluation logic LSI configured by synthesizing mask patterns of a mass production logic LSI and an evaluation logic LSI dedicated circuit, break signal generating means for program debugging is provided in a dedicated circuit section of the evaluation logic LSI. An evaluation logic LSI, which is built-in and enables control of the break signal generation means from outside the evaluation logic LSI. 2. The logic LSI for mass production according to claim 1.
And the break signal generating means are connected to an address bus by a break signal line, and the break signal generating means allows a break address value to be set from outside the evaluation logic LSI, so that the data bus is connected from outside. Evaluation logic LSI 3. The break signal generating means according to claim 1, wherein the break signal generating means comprises one or more address bus comparison registers and a comparator. 4. The address bus comparison register according to claim 1, wherein the address bus comparison register is readable / writable from outside the evaluation logic LSI. 5. The break signal mask bit according to claim 1, 2, 3 or 4, wherein the break signal generating means includes one or more break signal mask bits. 6. The method according to claim 1, 2, 3, 4 or 5.
The break signal mask bit is the evaluation logic LS.
Break signal mask bit that can be read and written from outside I.