JP3158884B2 - Integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test circuit for an integrated circuit including a master circuit serving as a bus master and its slave circuit.

[0002]

2. Description of the Related Art In recent years, a semiconductor integrated circuit which has been designed in a plurality of chips until now has been often integrated into one chip. This is equivalent to building the system on one chip. In addition, in many cases, data designed as a plurality of chips is diverted in order to improve development efficiency. Because of this, such L
The SI test is performed by providing a mode for allocating an external signal of the circuit to an external terminal for each of the circuits that have been designed to be divided into a plurality of chips.
In some cases, previous test patterns may be used.

For example, it is realized by connecting all external signals of a circuit which has been designed to be divided into a plurality of chips to an external terminal via a selector, and switching the selector by an output of a mode setting circuit. .

[0004]

However, in the above configuration, when a bus circuit is connected to each other to include a master circuit serving as a bus master and a slave circuit serving as a slave,
Since a selector must be provided for each bus-coupling portion of the bus-coupling circuit, there is a problem that the test circuit becomes large.

SUMMARY OF THE INVENTION In view of the above problems, the present invention provides an integrated circuit including circuits which are bus-coupled to each other, and which can allocate external signals including bus signals of each circuit to external terminals with a small number of elements. Is what you do.

[0006]

According to a first aspect of the present invention, there is provided an integrated circuit, comprising: a control circuit for setting a mode for testing each of the built-in circuits; A selector that assigns an external signal of a circuit to be tested to an external terminal of the integrated circuit by an output of the circuit to be tested.If the circuit to be tested is a slave circuit that is coupled to a master circuit to be a bus master by an internal bus, The control circuit requests the master circuit to release the bus, and assigns the bus released by the master circuit to an external terminal by a selector.

In the second invention, when the circuit to be tested is a slave circuit connected to a master circuit serving as a bus master by an internal bus, the control circuit requests the master circuit to release the bus and sets the master circuit to the master circuit. The configuration in which the reset of the slave circuit to be tested is released by using the bus release response from the circuit is added to the first invention.

[0008]

According to the present invention, in the first aspect of the present invention, a bus release is requested from a master circuit serving as a bus master of a bus connected to a circuit to be tested, and the bus released by the master circuit is provided to an external terminal. The assignment allows bus signals of the circuit under test to be assigned to external terminals without inserting selectors on both sides of the input and output of the bus of the circuit under test. it can.

Further, in the second invention, the reset of the circuit to be tested is released using the bus release response of the master circuit serving as the bus master, so that the master circuit is released after the reset of the master circuit is released. By preventing the output signal of the master circuit from affecting the slave circuit to be tested before the bus is released, the test pattern of the single slave circuit to be tested can be used with only minor modifications. .

[0010]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
This will be described with reference to the drawings.

FIG. 1 is a block diagram showing an integrated circuit according to an embodiment of the present invention. In FIG. 1, 1 is an internal bus, 2 is a mode setting signal, 3 is a bus release request, 5 is a selector control signal, 6 is an external terminal, 100 is a control circuit,
00 is a master circuit, 300, 400, and 500 are slave circuits, and 600 is a selector.

A master circuit 200 and a slave circuit 300;
400 and 500 are connected by the internal bus 1.
Although not shown, a bus control signal is supplied from the master circuit 200 to each slave circuit. However, this bus control signal is not directly connected but is connected via the selector 600.

First, when the normal mode is indicated by the mode setting signal 2, the control circuit 100 outputs the normal mode to the selector control signal 5 and deasserts the bus release request 3.

At this time, the selector 600 connects the signal to be assigned to the external terminal in the normal mode to the external terminal 6 from the internal signal, and connects the signal to be connected between the internal signals in the normal mode. This internal signal includes the bus control signal described above. That is, the master circuit 20
The bus control signal output by 0 is connected to each slave circuit. Therefore, in the normal mode, all circuits are normally connected and operate as a system.

Next, a mode for testing the slave circuit 300 will be described. When the mode for testing the slave circuit 300 is indicated by the mode setting signal 2, the control circuit 100 outputs to the selector control signal 5 the mode for testing the slave circuit 300, and asserts the bus release request 3. .

The master circuit 200 releases the internal bus 1 when the bus release request 3 is asserted. Then, the selector 600 outputs the external signal of the slave circuit 300 to the external terminal 6.
Connect to At this time, the external signals of the slave circuit 300 include the internal bus 1 and the bus control signal.

FIG. 2 shows an example of the selector 600, and its operation will be described. In FIG. 2, 601, 602, 6
03 is an external terminal, 610, 611, 612, 613 are selector control signals, 620, 621, 622, 623, 6
Reference numerals 24, 625, and 626 indicate internal signals, respectively. The internal signal 626 is an internal bus.

Here, in the normal mode, selector control signal 610 is set to the H level, and internal signal 620 is set.
Is output to the external terminal 601, the internal signal 621 is connected to the internal signal 622, and the internal signal 623 is output to the external terminal 602.
Is entered from Also, the selector control signals 611 and 61
3 is set to H level, the selector control signal 612 is set to L level, and the internal signal 625 is output to the external terminal 603.

Next, in the test mode, the selector control signal 610 is set to L level, the internal signal 621 is output to the external terminal 601, and the internal signal 622 is input from the external terminal 602.

Since the selector control signal 611 is set at the L level and the selector control signals 612 and 613 are appropriately set using the bus control signal, the internal bus signal 626 can be input / output using the external terminal 603. Here, the slave circuit 300 outputs the internal signal 621 and the slave circuit 4
00 is a signal input as the internal signal 622. Then, in the normal mode, the selector control signal 610
Is set to the H level, the internal signal 621 can be connected to the internal signal 622.

Further, in the test mode of the slave circuit 300, the internal signal 621 can be output to the external terminal 601 by setting the selector control signal 610 to the L level, so that observation becomes possible. Then, also in the test mode of the slave circuit 400, by setting the selector control signal 610 to L level, the internal signal 622 can be input from the external terminal 602, so that control is possible.

An internal bus 6 common to each slave circuit
26 is a selector control signal 61 in the normal mode.
By setting 1 to H level, it cannot be observed from the outside.

However, in the test mode of each slave circuit, the selector control circuit 611 is set to the L level, and the selector control signal 612 is controlled to the H level when data is supplied to the slave circuit using the internal bus.
If the selector control signal 613 is an inverted signal of the selector control signal 612, the internal bus 626 can be controlled / observed from the external terminal 603 if the internal bus 626 is open.

If the bus connection portion of each slave circuit is assigned to an external terminal without releasing the bus to the master circuit 200, a selector circuit is required for each bus connection portion of each slave circuit. It is apparent that the number of test circuits can be reduced by this embodiment.

As described above, according to this embodiment, in the test of the slave circuit of the integrated circuit including the master circuit and the slave circuit, the external signal of the slave circuit to be tested is
By assigning a control circuit that outputs a bus release request to the master circuit when assigning to an external terminal, and releasing the bus to the master circuit and providing a selector circuit that directly assigns the internal bus to the external terminal, the bus connection can be reduced with a small number of circuits Portions can be assigned to external terminals.

Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a block diagram showing an integrated circuit according to a second embodiment of the present invention. 3, the same components as those in FIG. 1 are denoted by the same reference numerals. In FIG. 3, 4 is a bus release response, and 7 and 8 are reset signals. Here, the reset signal 7 is connected to the master circuit 200 and the control circuit 100.

When the normal mode is indicated by the mode setting signal 2, the control circuit 100 outputs the reset signal 7 as it is to the reset signal 8. However, when the mode setting signal 2 indicates the test mode, the reset signal 8 is negated after the bus release response 4 is asserted. For example, an inverted signal of the bus release response 4 is output as the reset signal 8.

Therefore, the operation in the test mode is as follows. First, the mode setting signal 2 is set to the test mode, and the reset signal 7 is asserted. At this time, the control circuit 100 asserts the bus release request 3. In the master circuit 200, the bus release request 3 is asserted because the reset signal 7 is asserted, but the bus release response 4 is deasserted. Therefore, the control circuit 100 asserts the reset signal 8. Further, the selector control signal 5 is set so that the external signal of the test target circuit indicated by the mode setting signal 2 is assigned to the external terminal 6. Therefore, selector 600
Assigns the external signal of the circuit under test and the internal bus 1 to the external terminal 6. However, data may collide on the internal bus 1 until the master circuit 200 releases the internal bus 1.

Next, the reset signal 7 is deasserted. Normally, after the reset is released, the master circuit 200 accepts the bus release request 3, asserts the bus release response 4, and releases the internal bus 1. When the internal bus 1 is released, collision of signals on the internal bus 1 is avoided, and the internal bus 1 can be controlled / observed from the external terminal 6 to which the internal bus 1 is assigned.

When the bus release response 4 is asserted, the control circuit 100 deasserts the reset signal 8. Therefore, from this point, a test can be performed by applying a test pattern from the external terminal 6 to the slave circuit to be tested and observing the state of the external terminal 6.

As described above, according to the present embodiment, in addition to the first embodiment, in the test mode, the reset signal to the slave circuit is released by the bus release response from the master circuit, so that the master circuit is released. The undefined state of the internal bus between the time when the reset is released and the time when the bus is released can be prevented from affecting the operation of the slave circuit. Therefore, a portion from mode setting to the release of the bus by the master circuit is added to the test pattern for the test target circuit alone, and the timing can be reused simply by adjusting the original reset release and the timing at which the master circuit releases the bus. . Therefore, it is possible to improve test pattern development efficiency.

In the second embodiment, the reset signal to the slave circuit in the test mode is generated from the bus release response from the master circuit. However, this does not limit the generation means. The reset signal may be released based on the assertion of the response.

In this embodiment, the case of a single bus master has been described. However, even when there are a plurality of bus masters, the control circuit sends a bus release request to all master circuits, and It is only necessary to replace the logical product of the bus release responses with the bus release response from the master circuit in this embodiment.

[0034]

As described above, according to the first aspect of the present invention, the master circuit serving as a bus master of the bus connected to the circuit to be tested is requested to release the bus, and the bus released by the master circuit is externally connected. By providing the selectors to be assigned to the terminals, the test can be performed with a smaller number of circuits as compared with a method of inserting selectors on both sides of the input and output of the bus of the slave circuit to be tested.

In the second invention, at the time of the test, a reset circuit of the circuit to be tested is released by using a bus release response from the master circuit. By the time the master circuit releases the bus, it is possible to prevent the output of the master circuit to the bus from affecting the circuit under test, and only minimally modify the test pattern of the slave circuit under test alone The development efficiency can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a selector for explaining operation in the embodiment.

FIG. 3 is a block diagram of a second embodiment of the present invention.

[Explanation of symbols]

 1 Bus 3 Bus release request 4 Bus release response 7, 8 Reset signal

Claims (2)

(57) [Claims] A master circuit serving as a bus master; a slave circuit bus-coupled to the master circuit; a control circuit for setting a test mode; and a bus signal connecting the master circuit and the slave circuit to an output of the control circuit. A selector that allocates a bus signal to an external terminal according to a signal, wherein the control circuit outputs a bus release request to the master circuit when the control circuit allocates the bus signal to the external terminal. . 2. The integrated circuit according to claim 1, wherein when the output signal of the control circuit assigns the bus signal to an external terminal, a reset signal for the slave circuit is generated from a bus release response signal from the master circuit. circuit.