JP3278594B2 - Test method for semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit such as a microcomputer, and more particularly to a semiconductor integrated circuit having a built-in test circuit for setting a test mode for product evaluation.

[0002]

2. Description of the Related Art Conventionally, a semiconductor integrated circuit such as a microcomputer is provided with a test mode for a designer to evaluate a product in addition to an operation mode for a user. Is called a test circuit.

[0003]

However, since this test circuit does not have a function for preventing access from a user, an unexpected operation mode other than the user mode is set by an erroneous operation of the user. However, there is a problem that it causes a malfunction. SUMMARY An advantage of some aspects of the invention is to provide a method for testing a semiconductor integrated circuit and a semiconductor integrated circuit that can prevent an erroneous operation of a test circuit.

[0004]

SUMMARY OF THE INVENTION The present invention provides a method for testing an adjacent second chip from external terminals of a first chip before separating the semiconductor wafer into individual chips. A predetermined signal is supplied to the circuit to set the second chip to the test mode. After the test , the first chip is set.
From the external terminal of the chip to the test circuit of the second chip.
And the test mode of the second chip is
After releasing and setting the user mode, the semiconductor wafer
By separating C into individual chips, the wiring connecting the external terminals of the first chip and the test circuit of the second chip is cut off. in this way,
In a state of the semiconductor wafer before being separated into individual chips, a predetermined signal is supplied from an external terminal of the first chip to a test circuit of an adjacent second chip to set the second chip to a test mode. After the test, a signal is supplied from an external terminal of the first chip to a test circuit of the second chip,
Set the second chip to the user mode. Thereafter, the semiconductor wafer is separated into individual chips, thereby forming a first chip.
Since the wiring connecting the external terminal of the chip and the test circuit of the second chip is disconnected, the test circuit cannot be accessed, and the test circuit keeps the state of the user mode .

[0005]

Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram of a semiconductor integrated circuit showing an embodiment of the present invention. FIG.
Then, a plurality of semiconductor integrated circuit chips 1a, 1b, 1c,
1d shows a state when it is formed on a semiconductor wafer.

A test circuit 2 for setting the chip to a test mode for product evaluation is provided in each chip having the same configuration.
An evaluation test ROM (read only memory) 3, an arithmetic circuit for performing four arithmetic operations or logical operations, and internal circuits (not shown) such as registers for holding addresses or data are provided.

Further, each chip is provided with a plurality of external terminals (pads). These terminals include an external terminal RST for reset, external terminals A, B, and C for supplying a test mode setting signal to the test circuit 2 of the adjacent chip, a power supply terminal (not shown), and a GND terminal (not shown). ).

The test circuit 2 includes a nonvolatile memory cell (E
EPROM cells) 11a, 11b, cells 11a, 11b
, And a buffer 13 connected to the output of the gate 12. The gates of the EEPROM cells 11a and 11b in a certain chip are connected to the external terminals A and B of the adjacent chip, respectively, and the sources of the EEPROM cells 11a and 11b are connected to the external terminal C of the adjacent chip. I have. Therefore, the test mode setting signal to the test circuit 2 of a certain chip is supplied from the external terminals A, B, and C of the adjacent chip via the wiring.

Next, a procedure for performing an evaluation test on such a semiconductor integrated circuit will be described. Here, a test of the chip 1c will be described as an example. First, chip 1
After the reset signal is input to the terminal RST of the chip c and the ROM 3 is reset, 0 is applied to the terminals A and B of the adjacent chip 1b.
V is applied, and a high voltage (for example, 1
0V). Thereby, the EEPR of the chip 1c
"0" is written in the OM cells 11a and 11b, and the cell 1
Erasure of 1a and 11b is performed.

Subsequently, a high voltage is applied to terminal A of chip 1b, and 0V is applied to terminals B and C of chip 1b. As a result, "1" is stored in the EEPROM cell 11a of the chip 1c.
Is written. Since the value written to the cell 11a becomes "1" and the value written to the cell 11b becomes "0", the output of the logic circuit 12 becomes "H" level, and the output of the buffer 13, that is, the test circuit 2 Becomes the "H" level.

In the ROM 3 of the chip 1c, the signal T is "H".
When it is recognized that the test mode has been set as the level, a test code (instruction) is output. The internal circuit of the chip 1c receiving the test code executes a process according to the test code. This execution result is output to a test device from an external terminal (not shown) of the chip 1c. The test device evaluates the chip 1c based on the received execution result. Thus, a product evaluation test is performed. In addition,
For information on how to test after setting to test mode,
It goes without saying that a method other than this embodiment may be used.

After the test, 0V is applied to terminals A and B of chip 1b, a high voltage is applied to terminal C of chip 1b, and "0" is written to EEPROM cells 11a and 11b of chip 1c. Subsequently, a high voltage is applied to the terminal B of the chip 1b, and 0V is applied to the terminals A and C of the chip 1b. Thereby, the EEPROM cell 11b of the chip 1c
"1" is written to.

Since the value written to the cell 11a becomes "0" and the value written to the cell 11b becomes "1", the output of the logic circuit 12 becomes "L" level and the signal T
Becomes the “L” level. Thus, the test mode is released, and the chip 1c is set to the user mode.

After performing the above-described processing for each chip, a dicing step, ie, a step of separating a semiconductor wafer into individual chips, is performed. When the test circuit 2 of each chip and the terminals A, The wiring connecting B and C is cut as shown in FIG. Since the test circuit 2 cannot be accessed due to the disconnection of the wiring, each chip maintains the state set in the user mode, so that an erroneous operation mode other than the user mode is not set.

After the chip is separated, the EEPROM cells 11a and 11b hold the user mode set value. Therefore, the state of the pad D is checked to determine whether the chip is in the user mode. be able to.
In this embodiment, the EEPROM cells are 11a,
Although the configuration is made up of two bits of 11b, a configuration other than two bits may be used. In the present embodiment, the test is performed one chip at a time, but it goes without saying that a plurality of chips may be tested simultaneously.

[0016]

According to the present invention, the separation between the external terminals of the first chip and the test circuit of the second chip is cut off by the separation of the chip after the completion of the test. The test circuit cannot be accessed, and the test circuit is fixed in the user mode. Therefore, an unexpected operation mode other than the user mode is not set by an erroneous operation of the user,
Malfunction due to erroneous operation of the test circuit can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram of a semiconductor integrated circuit showing an embodiment of the present invention.

FIG. 2 is a diagram showing a state of each chip after separation.

[Explanation of symbols]

1a, 1b, 1c, 1d ... semiconductor integrated circuit chip, 2 ...
Test circuit, 3 ROM, 11a, 11b nonvolatile memory cell, 12 logic circuit, 13 buffer, A, B,
C, D: external terminal, T: test signal, RST: external terminal (reset terminal).

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/822 H01L 27/04

Claims (1)

(57) [Claims] 1. A test method for a semiconductor integrated circuit, comprising: a test circuit for setting an evaluation test mode; and for each chip on a semiconductor wafer, a test mode is set using the test circuit and an evaluation test is performed. In the method, before a semiconductor wafer is separated into individual chips, a predetermined signal is supplied from an external terminal of the first chip to a test circuit of an adjacent second chip to set the second chip to a test mode. After the test is completed , the external terminal of the first chip is connected to the second terminal.
A predetermined signal is supplied to the test circuit of the second chip,
Cancel the test mode of the second chip and enter the user mode
After setting, the semiconductor wafer is separated into individual chips
A method of testing a semiconductor integrated circuit, characterized in that the wiring connecting the external terminal of the first chip and the test circuit of the second chip is cut .