JPH0566763A - Image data transmitting device - Google Patents

Abstract

PURPOSE:To improve the processing efficiency of a CPU by switching and transmitting the image data of different image planes without interrupting the CPU. CONSTITUTION:Plural head starting addresses corresponding to the respective display starting points of the different image planes are held in registers 12 and 14, and the display starting addresses are alternately switched, for example, in every vertical fly-back period by a switching device 16. By setting the display starting address selected by the switching device 16 as a head address from an address counter 18, the address for reading out the image data of one image plane is generated from image memories (32 and 34). The image data read out of the image memories (32 and 34) according to the respective addresses is transmitted to a picture display device in an ordinary way.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image data sending device for reading image data to be displayed one screen at a time from an image memory and sending it to an image display device.

[0002]

2. Description of the Related Art Generally, in a device or system that displays an image under the control of the CPU, the CPU should display 1
When the image data for the screen is written in the image memory, the hardware-like image data sending device next reads the image data for one screen to be displayed from the image memory at a predetermined timing and sends it to the image display device side. This allows the CPU to devote time other than the writing of image data to other processing. The head address (display start address) of the image data for one screen to be read from the image memory is set by the CPU in the image data sending device.

A conventional image data transmission device holds only one display start address at a time, and every time transmission of image data for one screen is completed (normally during a vertical blanking period during which the screen is switched). ) An interrupt request was issued to the CPU side. In response to this interrupt request, the CPU writes, as an interrupt processing routine, one screen of image data to be displayed next in the image memory, and further responds to the one screen of image data as necessary. The display start address was set in the image data sending device.

[0004]

As described above, according to the conventional image data transmitting apparatus, when the screen is switched, the CPU writes the image data to the image memory by the interrupt processing routine during the vertical blanking period, Further, since it is necessary to set the display start address for the image data transmission device as necessary and other processing is interrupted by the interrupt processing, there is a problem that the processing efficiency of the CPU is reduced.

The present invention has been made in view of the above problems, and it is possible to send image data of different screens without interrupting the CPU, thereby improving the processing efficiency of the CPU. An object is to provide a data transmission device.

[0006]

In order to achieve the above object, an image data transmitting apparatus of the present invention is provided with a plurality of image data storage positions in an image memory corresponding to respective display start points of different screens. Display start address holding means for holding the display start address, display start address switching means for selecting the plurality of display start addresses held by the display start address holding means for each screen display cycle, and the display start address. The display start address selected by the switching means is used as a head address, and an address generating means for generating an address for reading one screen of image data from the image memory is provided.

[0007]

The image data for one screen to be displayed on the image display device is written in the image memory by the CPU or the like prior to display. In the image data transmission device of the present invention, the display start address of the image data for one screen and the display start address of the image data for one screen to be displayed next to the image data are both stored in the display start address holding means. Retained. Then, the display start address switching means alternately switches the display start addresses, for example, every vertical blanking period, and the image generation is performed by the address generating means with the display start address selected by the display start address switching means as the head address. An address for reading the image data for one screen is generated. The image data read from the image memory at each address is sent to the image display device in a usual manner.

As described above, in the image data transmission device of the present invention, different display start addresses are automatically switched and the image data of different screens are read out from the image memory and transmitted to the image display device. It is not necessary to interrupt the CPU during the screen switching period to force the CPU to write the image data to be displayed next within a short time. It is possible to write image data of another screen by spending an arbitrary time.

[0009]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a diagram showing a configuration of an image data transmitting apparatus according to an embodiment of the present invention, and FIG. 2 conceptually shows a screen configuration of a right-eye video screen and a left-eye video screen when a stereoscopic video display system is performed. FIG. 3 and FIG. 3 are diagrams showing an example of a storage arrangement distribution of image data stored in the image memory of FIG. 1 when the stereoscopic image display system is performed.

Referring to FIG. 1, an image data transmitting apparatus 10 according to this embodiment includes an address bus AB0 and a data bus D.
It is connected to the CPU 30 via B0, and is also connected to the VRAM 32 and the font memory 34 via address buses AB1 and AB2 and data buses DB1 and DB2.
The CPU 30 and VRAM 32 are connected to each other via an address bus AB3 and a data bus DB3. Although not shown for the sake of simplicity, a control bus is also provided between the respective parts.

The VRAM 32 and the font memory 34 constitute an image memory, the VRAM 32 stores character data constituting an image for one screen or several screens, and the font memory 34 stores all displayable character data. The font data corresponding to is stored. Here, the character data is not necessarily limited to one independent character or figure, but can also be a fragmentary line or dot, and any preset pattern is represented as a code (number). The data. Also font data,
The data is not limited to one independent character or figure, and represents any pattern as a bit pattern.

Prior to displaying an image for one screen on the image display device, the CPU 30 writes a predetermined number (for example, 25 × 32) of character data constituting the image for one screen in the VRAM 32. According to the present embodiment, as will be described later, the CPU 30 writes the character data in the VRAM 32 by utilizing an arbitrary time within the vertical cycle instead of the conventional interrupt processing.

The image data transmitting apparatus 10 of this embodiment comprises registers 12, 14, a switch 16, and an address counter 1.
8, timing generator 20, address generator 22, buffers 24 and 26, and register 28.

The registers 12 and 14 have head start addresses VAa, which correspond to respective display start points of different screens.
It is for holding each VAb. These head start addresses VAa and VAb are set by the CPU 30 simultaneously or individually.

Under the control of the switching control signal SW from the timing generator 20, the switch 16 alternately selects the display start addresses VAa and VAb from the registers 12 and 14 each time the screen to be displayed is switched. Then, the selected display start address is set in the address counter 18.

The address counter 18 responds to the character clock CK from the timing generator 20 and sets the display start address VAi from the switch 16 to 1 as an initial value.
An address for sequentially reading the screen character data from the VRAM 32 is generated at a constant cycle. Each character data read from the VRAM 32 by each address from the address counter 18 is taken into the buffer 24.

The address generator 22 selects the font memory 3 for the font data corresponding to the character data from the character data stored in the buffer 24.
Data indicating the storage position in No. 4 is extracted, and an address for reading the font data is generated. Each font data read from the font memory 34 by each address from the address generator 22 is fetched in the buffer 26 and then sent to an image display device (not shown).

The timing generator 20 sends the switching control signal SW to the switch 16 and the address counter 18 as described above.
To the address generator 22 and the buffers 24 and 26 in addition to the character clock CK. Various set values defining the operation of the timing generator 20 are set in the register 28 by the CPU 30.

Next, the operation of the image data transmitting apparatus 10 of this embodiment for displaying a stereoscopic image will be described with reference to FIGS. 2 and 3. The stereoscopic image display means that the image screen for the right eye and the image screen for the left eye are alternately switched and displayed at every vertical period, and at the same time, the right lens of the special glasses for stereoscopic image viewing attached by the viewer in synchronization with the image It is a technique that allows you to view stereoscopic images on a flat display by turning on and off the left lens alternately.

In this stereoscopic image display method, as shown in FIG. 2, a right-eye image screen (A) and a left-eye image screen (B) are separately prepared. In both screens, for example, 25 × 32 characters (1a, 2a, ..., Ma, ... Na),
(1b, 2b, ..., Mb, ... Nb) are arranged in a matrix to form one screen.

Prior to displaying the image screen (A) for each right eye and the image screen (B) for each left eye on the image display device, the CPU 30 displays the character data (character number) constituting these screens. As shown in FIG. 3, each is written in a predetermined area of the VRAM 32. As described above, the video screen for the right eye (A) and the video screen for the left eye (B) can be switched alternately every vertical cycle.
The character data of both video screens (A) and (B) stored in 2 may be rewritten every two vertical periods.

Now, both video screens in the VRAM 32
The start addresses of the character data of (A) and (B), that is, the display start addresses VAa and VAb are the image data transmitting device 1
It is held in both registers 0 and 0 of 0. And
The display start addresses VAa and VAb are alternately switched by the timing generator 20 and the switcher 16 for each vertical blanking period and set as an initial value in the address counter 18, and the address counter 18 displays a right-eye video screen. (A) Character data and video screen for right eye
An address for alternately reading the character data of (A) is generated every vertical cycle.

Therefore, the CPU 30 should receive an interrupt request from the image data transmitting apparatus 10 and then display the right-eye video screen (A) for an arbitrary time within the vertical cycle during which the image is displayed next. The character data of the left-eye video screen (B) is written to the VRAM 32, and the left-eye video screen is displayed.
Character data of the right-eye video screen (A) to be displayed next can be written in the VRAM 32 by spending an arbitrary time within the vertical cycle in which (B) is displayed.

As described above, the CPU 30 does not need to forcibly interrupt other processing for writing the image data by interruption or the like, so that the throughput is improved. Of course, the burden on the software is also lightened.

Although the stereoscopic image display system has been described above as an example, the same operation as described above can be achieved when the screen is switched in the normal moving image display. Further, although the image data transmission device 10 of the above-described embodiment is provided with two registers 12 and 14 for holding the display start address VA, it is of course possible to provide three or more registers, or instead of the registers, a memory such as a RAM. May be used. Further, in the above embodiment, the image memory is composed of the separate VRAM 32 and font memory 34, but the image memory may have any form.

[0026]

The present invention has the following effects by having the above-mentioned structure. By holding a plurality of display start addresses corresponding to the display start points of different screens and switching the display start addresses, the CPU can read from the image memory and send to the image display device without interrupting the CPU. Since the image data to be output is switched, the load on the CPU can be reduced and the processing efficiency of the CPU can be improved.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an image data transmission device according to an embodiment of the present invention.

FIG. 2 is a diagram conceptually showing a screen configuration of a right-eye video screen and a left-eye video screen when a stereoscopic video display method is performed.

FIG. 3 is a diagram showing an example of a storage arrangement distribution of image data stored in the image memory of FIG. 1 when a stereoscopic video display method is performed.

[Explanation of symbols]

 10 image data sending device 12 register 14 register 16 switcher 18 address counter 20 timing generator 22 address generator 24 buffer 26 buffer 30 CPU 32 VRAM 34 font memory

Continuation of the front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location G09G 5/22 9061-5G

Claims (1)

[Claims] 1. From an image memory storing image data
In an image data transmission device for reading out image data for each screen and transmitting the read image data to an image display device, a plurality of image data storage positions in the image memory corresponding to respective display start points of different screens are specified. Display start address holding means for holding the display start address of the display start address, and display start address switching means for selecting the plurality of display start addresses held by the display start address holding means for each one screen display cycle; 1 from the image memory with the display start address selected by the switching means as the start address.
An image data transmitting apparatus comprising: an address generating unit that generates an address for reading image data for an image.