JP2003241727A - Method and circuit for image output for obtaining image outputs of a plurality of systems from image input of one system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method and circuit for image output generation which can obtain image outputs of a plurality of arbitrary systems from an image input of one system. <P>SOLUTION: The method and the circuit are provided with (n) pieces of line memories (1, 2) to which an image signal of one system is inputted with its dot clock respectively and a timing signal generating circuit (3) which generates a read clock signal 1/n times as fast as the dot clock of the image signal of the one system, a write enable signal making writable the line memories (1 or 2) made to correspond to each of periods obtained by dividing one horizontal effective scanning period of the image signal into (n) periods in the period, and a read enable signal making all the line memories readable in the periods corresponding to the one horizontal effective scanning period and supplies the generated signals to the (n) pieces of line memories. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image output method and circuit for obtaining a plurality of systems of image output from one system of image input.

[0002]

2. Description of the Related Art For obtaining a plurality of systems of image output from one system of image input, for example, Japanese Patent Publication No. 5-71098, JP-A-60-134336, JP-A-55-55.
There is an invention disclosed in Japanese Patent No. 110295. Japanese Patent Publication No. 5-71098 discloses an invention relating to an image display device for displaying different or the same image on two CRT screens such as a stereoscopic image display device.
The video display device of the present invention includes two display devices, a pair of video memories for storing video data to be supplied to the display devices, and an image data memory for storing image data of a character to be supplied to these video memories. And a body memory that stores data for selecting the image data stored in the image data memory, a position on the screen, and the like, and a video memory that has one pair in the first half of one horizontal scanning period. On the other hand, the data transmission control which gives the data of the image data memory and the data of the standard memory separately to the corresponding display unit by alternately reading the video data from the paired video memories for each horizontal scanning Equipped with means. With this configuration, the present invention can display different or the same image on the two displays using one image data memory.

Further, Japanese Patent Application Laid-Open No. 60-134336 discloses an invention relating to a display control device which converts parallel dot data of a display pattern into serial data and supplies the serial data to a plurality of display units. The present invention comprises a pattern generating means, a dot selecting means, and a plurality of dot buffers capable of respectively storing one-dot data in a one-to-one correspondence with a plurality of display units. Raster dot parallel dot data for the display unit are sequentially generated in a time division manner within one dot time, and one dot data to be displayed is selected by the dot selecting means from each of the parallel dot data, and the selected data is associated. The data stored in each dot buffer is sent to the corresponding display unit. Thus, the invention is
The display pattern is displayed on a plurality of display units, but by adopting the above configuration, the circuit configuration for realizing this can be simplified as compared with the conventional one.

Further, Japanese Patent Laid-Open No. 55-110295 discloses an invention relating to a character display device in which the output of a character generator is time-divisionally given to two display devices and alternately displayed for each screen. It is disclosed. The present invention ANDs the signal obtained by dividing the vertical synchronizing signal with the output signal of the character generator.
The above-mentioned signal is distributed to the two display devices, and two different characters can be simultaneously displayed on the two display devices by adding a simple circuit.

[0005]

However, in the invention disclosed in the above Japanese Patent Publication No. 5-71098, the data to be given to the two displays are stored in advance in the image data memory or the standard memory, It is not possible to distribute a general video output given by the above to a plurality of display devices. Further, in the invention disclosed in Japanese Patent Application Laid-Open No. 60-134336, parallel dot data such as a character pattern is serially sent to each display unit dot by dot. Only the same image as the original image (display pattern) is displayed.

Further, the invention disclosed in Japanese Patent Application Laid-Open No. 55-110295 is not capable of distributing the video output to an arbitrary number of displays due to its configuration, and each display is capable of displaying one frame. Hide 1 frame (display black)
Since it repeats alternately, a large screen flicker occurs and it becomes very unsightly.

The present invention has been made in view of the above points, and only by adding a circuit having a simple structure, an image input of one system can be performed and an image output of an arbitrary plurality of systems can be performed without causing the above problems. An image output method and a circuit that can be obtained are provided.

[0008]

An image output method for obtaining an image output of a plurality of systems from an image input of one system of the invention described in claim 1 is n (where n is an integer of 2 or more) pieces. Using a line memory, the image data included in each period is made to correspond to each period when one horizontal effective scanning period of image data having a predetermined dot clock is divided into n consecutive periods. In addition to writing in the line memory, the image data written in from all the line memories is read at a speed of 1 / n times the predetermined dot clock, and an n-system image output composed of the read image data is obtained.

The invention according to claim 2 is an image output method for obtaining an image output of a plurality of systems from an image input of one system, which is an image of an image obtained by arranging and synthesizing different images in order in the horizontal scanning direction. By writing data to the n line memories according to the method of claim 1, n
The feature is that image outputs of different systems are obtained.

Further, the image output circuit for obtaining the image output of a plurality of systems from the image input of one system of the invention described in claim 3 is such that n (where n is an integer of 2 or more) from the image input of one system. Circuit for obtaining the image output of
An image signal of a system is input to each of the dot clocks by n line memories, a read clock signal that is 1 / n times faster than the dot clock of the image signal of one system, and one horizontal line of the image signal. When the effective scanning period is divided into n consecutive periods, a write enable signal for writing the line memory corresponding to each period in each period, all lines in a period corresponding to the one horizontal effective scanning period And a timing signal generating circuit for generating a read enable signal for making the memory readable and supplying each of the generated signals to the n line memories.

In the above invention, the image data in the horizontal effective scanning period is divided into n, and the respective divided image data are sequentially written in the corresponding line memories. Then, the image data written in each line memory is read at a speed of 1 / n times the original dot clock (dot clock obtained by dividing the original dot clock by n) and output to the corresponding display device. Accordingly, it is possible to obtain image outputs of arbitrary plural systems from one system of image input.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a circuit configuration of an embodiment of the present invention. In the present embodiment, for simplification, a case where an image input of one system is received and an image output of two systems is performed will be described as an example.

The circuit of this embodiment comprises a line memory 1, a line memory 2 and a timing signal generating circuit 3. As the line memories 1 and 2 used here, a FIFO (Fast In Fast Out) memory is used, but a 2-bank memory is used.
Use each bank as line memories 1 and 2,
This can also be realized by writing and reading on a first-in first-out basis. Further, the line memories 1 and 2 are respectively R (Re
d), G (Green), and B (Blue) are composed of a FIFO memory to / from which digital image data of three colors are respectively written / read, but omitted in FIG. 1 for simplicity. Similarly, the image input, image output, and image output signal lines shown in FIG. 1 are composed of digital RGB signals, respectively.

A dot clock for image input and a horizontal / vertical synchronizing signal are input to the timing signal generating circuit 3. The timing signal generating circuit 3 generates the following WRITE (write) clock enable signals C and D, and READ (read) clock signals E and READ (read) clock enable signals F from these input signals. , To the line memories 1 and 2.

On the other hand, an image input signal (image input) from an image output device such as a graphics LSI and a dot clock for this image input as a WRITE clock signal B are input to both the line memories 1 and 2. A READ clock signal E and a READ clock enable signal F are input from the timing signal generation circuit 3. Further, the line memory 1 receives the WRITE clock enable signal C from the timing signal generating circuit 3, and the line memory 2 receives the WRITE clock enable signal D from the timing signal generating circuit 3. Then, the image output is output from the line memory 1 and the image output is output from the line memory 2.

The details of each of the above signals will now be described. The WRITE clock signal B is a dot clock for image input, and is a signal that determines the timing of writing the data (image data) of each pixel included in the image input to the line memory 1 and the line memory 2. Also, W
The WRITE clock enable signal C is a signal that determines the timing for permitting the writing of image data to the line memory 1, and the WRITE clock enable signal D is a signal that determines the timing at which the writing of image data is permitted. Specifically, the WRITE clock enable signal C becomes high level in the first half portion of the horizontal effective scanning period divided into two, which enables the line memory 1 to be written, and
The WRITE clock enable signal D becomes high level in the latter half of the horizontal effective scanning period divided into two,
The line memory 2 is made writable.

The READ clock signal E is a signal that determines the timing of reading image data from the line memory 1 and the line memory 2, and in the present embodiment,
The dot clock for image input is divided by 2, that is, 1
It is a clock signal with a double speed. The READ clock enable signal F is a signal that determines the timing for permitting the reading of image data from the line memories 1 and 2. Specifically, the READ clock enable signal F becomes high level during the period corresponding to the horizontal effective scanning period, and the line memory 1 and the line memory 2 can be read during this period, and the line memory 1 and the line memory 2 are read. All the written pixel data of the image input can be read at the timing determined by the READ clock signal E in this period.

In the timing signal generating circuit 3, the WRITE clock enable signals C, WRI
Each of the TE clock enable signal D and the READ clock enable signal F is generated by a circuit configured by using a well-known counter circuit or the like, and the timing required for each signal from the horizontal / vertical synchronization signal and the dot clock of the image input. Is generated and a pulse is generated / extinguished at that timing to generate the pulse. Further, the READ clock signal E can be generated by dividing the dot clock of the image input by 2 by a well-known divide-by-2 circuit.

Next, the operation of the circuit of this embodiment will be described with reference to FIG. FIG. 2 is a timing chart of each of the signals input / output in the line memories 1 and 2 and the timing signal generation circuit 3. In the timing chart shown in the figure, the image input has 640 horizontal pixels.
(PIXEL1 to PIXEL640). In the figure, reference characters A to H respectively indicate A: image input, B: WRITE clock signal to line memories 1 and 2 (dot clock of image input), C: WRITE clock enable signal to line memory 1. , D: WRITE clock enable signal to the line memory 2,
E: READ clock signal to the line memories 1 and 2,
F: READ clock enable signal to the line memories 1 and 2, G: image output, H: image output.

The image input A is input to the line memories 1 and 2, respectively. As described above, the line memory 1 becomes writable only when the WRITE clock enable signal C is at a high level, and the WRITE clock is input. The line memory 2 becomes writable only when the enable signal D is at high level. Then, the input image data of the image input / A is sequentially written in each line memory (1, 2) at the timing of each rising edge of the WRITE clock signal B.

In the example shown in FIG. 2, PIXEL1 to PIXEL1.
W during the period of receiving image input / A consisting of XEL320
The RITE clock enable signal C becomes high level, and during this period, the pixel data (image data) of PIXEL1 to PIXEL320 are written in the line memory 1. Subsequently, the WRITE clock enable signal D is at a high level during the period of receiving the image input / A composed of the PIXEL 321 to PIXEL 640, and during this period,
The pixel data of PIXEL 321 to PIXEL 640 are written in the line memory 2.

On the other hand, regarding the reading of image data from the line memories 1 and 2, when the READ clock enable signal F is at a high level, the reading from the line memories 1 and 2 is permitted. The READ clock enable signal F becomes high level during the period of receiving the image input / A of PIXEL1 to PIXEL640, and during this period, the image data is read from both the line memories 1 and 2 at the timing of each rising edge of the READ clock signal E. Is read.

At this time, from the line memory 1, the PIX
The pixel data of EL1 to PIXEL320 are read out, and PIXEL321 'to PI are read from the line memory 2.
XEL640 '(Note that PIXEL321'-PIXE
L640 'is the currently input image input / A 1
The data of the pixel of the data group of the pixel before the line) is read. As described above, this reading is performed by the REA that has a speed half that of the image input / A dot clock.
It is performed at the timing of each rising edge of the D clock signal E. In the example shown in FIG. 2, image output / G
And the image output H is 1 of the READ clock signal E.
The output is delayed by the clock.

As described above, from one system image input (pixel number 640 × 200) to two system image output,
(Number of pixels 320 × 200) is obtained. Here, FIG.
Fig. 4 shows a screen image for image input, and Fig. 4 shows a screen image for image output. As shown in these figures, for the image input having the screen image shown in FIG.
An image output having the image image (image) shown in FIG. 4A and an image output having the screen image (image) shown in FIG. 4B are obtained. Therefore, the horizontal effective scanning period is divided into two periods, and these periods are combined so as to include different images and images, that is,
An image input signal (image input) composed of image data of images obtained by arranging and synthesizing different images in order in the horizontal scanning direction is applied to the circuit of the present embodiment to output images and images having two different screen images. Will be able to get.

Although the embodiment of the present invention has been described in detail above with reference to the drawings, the specific configuration is not limited to this embodiment, and a configuration and the like within the scope not departing from the gist of the present invention are also possible. included. For example, in the above embodiment, for simplicity, a case has been described in which one system of image input is used to obtain two systems of image output, but the present invention uses n (n is 2 or more) line memories. In each period when one horizontal effective scanning period is divided into n consecutive periods, the image data included in each period is written in the line memory corresponding to each period, and 1
By reading the image data written from the whole line memory at the speed of / n times, it is possible to obtain the image output of n systems.

[0026]

As described above in detail, according to the present invention, when the horizontal effective scanning period is divided into n consecutive periods, the image data included in each period is divided into each period. The image data written in the line memory corresponding to the period is read out from all the line memories at a speed of 1 / n times of the dot clock of the image input, and n lines of the read image data are read. Image output is obtained. Therefore, by adding the image output circuit of the present invention that receives this image output signal as an image input to a general image output signal, it is possible to obtain image outputs of arbitrary plural systems from one system of image input. become. Also, as the image data included in the image input,
By using image data of images obtained by arranging and synthesizing different images in order in the horizontal direction, it is possible to obtain image outputs of different n systems.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an image output circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart of the same embodiment.

FIG. 3 is a diagram showing an example of a screen image for image input according to the same embodiment.

FIG. 4A is a diagram showing an example of an image output screen image in the same embodiment, and FIG. 4B is a diagram showing an example of an image output screen image in the same embodiment.

[Explanation of symbols]

1, 2 ... Line memory, 3 ... Timing signal generating circuit

Claims (3)

[Claims] 1. Each of n (where n is an integer of 2 or more) line memories is used, and each horizontal effective scanning period of image data having a predetermined dot clock is divided into n consecutive periods. In each period, the image data included in each period is written in the line memory corresponding to each period, and the image data written in from all the line memories is read and read at a speed of 1 / n times the predetermined dot clock. An image output method for obtaining image outputs of a plurality of systems from an image input of one system, characterized in that an image output of n systems composed of the image data is obtained. 2. The image data of an image obtained by arranging and synthesizing different images in order in the horizontal scanning direction is written in the n line memories by the method according to claim 1,
An image output method for obtaining image outputs of a plurality of systems from an image input of one system, characterized in that image outputs of different systems are obtained. 3. From one system of image input, n (however, n
Is an integer of 2 or more), and is a circuit for obtaining an image output of one system, and n line memories in which the image signal of one system is input at each of the dot clocks, and dots of the image signal of the one system Write a read clock signal at a speed 1 / n times as high as the clock, and write the line memory associated with each period into one period when one horizontal effective scanning period of the image signal is divided into n consecutive periods. A timing signal generation circuit that generates a write enable signal that enables the read enable signal that enables all line memories to be read in a period corresponding to the one horizontal effective scanning period, and applies each generated signal to the n line memories. And an image output circuit for obtaining image outputs of a plurality of systems from an image input of one system.