JP2903346B2 - Video display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION This invention, and about <br/> to the video display device, and more particularly, to have a function that displays the information about the character and pattern of the border, superimpose a character in the video
The present invention relates to a video display device for displaying images .

[0002]

2. Description of the Related Art FIG. 3 is a block diagram mainly showing a character video signal generating circuit portion of a conventional video display device of this kind . This character video signal generation circuit 13
A display data RAM 5 is provided which can store all character codes displayed on the screen at one time.

In order to write the character code "W" sent from the microcomputer 1 into the display data RAM 5, this circuit includes a write address register 2, a write data register 3, a write synchronization circuit 4, and an address selection circuit 6. Have. Write address register 2 receives control and data signal B from microcomputer 1 and holds address signal A. The write data register 3 holds the character code "W" and outputs it on the character signal W. The write synchronization circuit 4 outputs a write synchronization signal S
In response to the write signal S, the address selection circuit 6 generates an address signal U to the display data RAM 5.
Generate

In order to read out the character code "G" to be displayed from the display data RAM 5, the character video signal generation circuit 13 includes a vertical address counter 12, an oscillation circuit 11, and a horizontal address counter 10. The vertical address counter 12 receives a vertical synchronizing signal V and a horizontal synchronizing signal H for synchronizing with a scanning line, generates a row selecting signal R, and determines a vertical position on the display screen in a row selecting signal R. R is sent to the address selection circuit 6. Oscillation circuit 1
1 receives a horizontal synchronizing signal H and generates a dot clock D whose oscillation start phase is synchronized with the horizontal synchronizing signal H in order to take timing during horizontal scanning. The horizontal address counter 10 receives the horizontal synchronization signal H and the dot clock D, generates a digit selection signal C for determining a horizontal position on the display screen, and sends the digit selection signal C to the address selection circuit 6 and the write synchronization circuit 4. Send.

Further, the selected character code "
In order to display the pattern of G ″, the character video signal generation circuit 13 includes a character generator 7 and a serial conversion circuit 8.
Receives the address signal L generated by the address selection circuit 6 and the character code "G" on the character signal G, and generates a character pattern "P" for one line in a pattern for one character. The serial conversion circuit 8
Outputs a character pattern consisting of a plurality of bits for one row one by one dot by dot clock D.

[0006] The serial conversion circuit 8 further includes a circuit for generating a framing pattern.
The character pattern "P" with "Y" can be combined with another video signal E and displayed on the CRT 9.

The operation of writing the character code "W" sent from the microcomputer 1 into the display data RAM 5 in the character video signal generation circuit 13 having such a configuration will be described.

The microcomputer 1 controls the character code "W" to be written in the display data RAM 5 and writes data in accordance with the data signal B.
In response to this, the write data register 3 holds the character code "W" and outputs it on the character signal W. When the microcomputer 1 sends an address "A" of the display data RAM 5 to which the character code "W" is to be written to the write address register 2 according to the control and data signal B, the write address register 2 receives the address "A". And outputs it on the address signal A. The microcomputer 1 sends a control signal to the write synchronizing circuit 4 in accordance with the control and data signal B to write that the write address register 2 holds the address "A" and the write data register 3 holds the character code "W". Is ready, the write synchronization circuit 4 receives the notification and attempts to output a write synchronization signal S for performing writing.

However, at this time, the character code "G" for display selected by the address signal U generated by the address selection circuit 6 receiving the row selection signal R and the digit selection signal C is read from the display data RAM 5. Are performed in synchronization with the horizontal synchronizing signal H and the vertical synchronizing signal V, the write synchronizing circuit 4 avoids the timing at which the character code "G" is being read out, and avoids the unnecessary screen of the character signal G. During the scanning period, the write synchronization signal S is output. Address selection circuit 6 receiving write synchronization signal S
Selects the address signal A and uses the address "A" on the address signal A as the address signal U to display data RAM.
Output to 5 Receiving the address signal U and the character signal W, the character code "W" is written into the address "A" in the display data RAM in accordance therewith.

The operation of the circuit when selecting and reading out the character code "G" to be displayed from the display data RAM 5 will be described. The vertical address counter 12 receives the vertical synchronization signal V, initializes the count value, receives the horizontal synchronization signal H, advances the count value, and outputs a row selection signal R for determining the vertical position of the scanning line. . The oscillation circuit 11
Receiving the horizontal synchronizing signal H, the oscillation phase is initialized, and a dot clock D having a frequency corresponding to the horizontal scanning speed of the scanning line is generated and output. Horizontal address counter 10
Receives the horizontal synchronization signal H, the count value is initialized,
The count value is advanced in response to the dot clock D, and a digit selection signal C for determining the horizontal position of the scanning line is output. The address selection circuit 6 receives the row selection signal R and the digit selection signal C generated as described above, and stores the address signal U to the display data RAM 5 and the address signal L to the character generator 7 respectively. It calculates and generates it according to the form and outputs it.

The display data RAM 5 receives the address signal U, reads out the character code "G" stored in advance at the address designated by the address signal U, and outputs it as a character signal G to the character generator 7. The character generator 7 may be a ROM storing a character pattern. The character generator 7 receives a character code "G", selects a pattern (matrix configuration) for one character corresponding to the code, and further receives an address signal L. The character pattern "P" for one line in the pattern for one character is output.

In order to generate a border pattern, patterns of upper and lower rows are also required, and a total of three rows of patterns are required. For example, a character pattern to be displayed when the value of the address signal L is "N" Assuming that "P", the value of the address signal L is "(N-1)", "N", "(N + 1)" within the time for scanning the width of one character.
The character patterns for three lines in the pattern for one character are sequentially read out on the pattern signal P (see (a) of FIG. 2).

In order to perform such a process, a period in which the address selection circuit 6 which has received the digit selection signal C scans the width of one character pattern is defined as T0, and the time of T0 is defined as T0.
1, T2, T3 and T4 (FIG. 2 (b)
See). In the period of T1, the address selection circuit 6 uses the read address “Q” generated from the row selection signal R and the digit selection signal C as the address signal U as the display data RA.
Send to M5. As a result, the character code “G” stored at the address “Q” of the display data RAM 5
Is read out on the character signal G.

During the period T2, the character pattern in the row next to the row "N" to be scanned is read out to generate the border pattern "Y". Therefore, during this period, the address selection circuit 6 applies "(N-
In response to this and the character code "G", the character generator 7 reads the pattern of the "(N-1)"-th line from the matrix pattern of the character code "G" as the character signal P. During this time, the character generator 7 outputs the character code "
G ”, the character code“ read out from the display data RAM 5 onto the character signal G ”
G "must be stable. For this purpose, the address signal U which is an input to the display data RAM 5 needs to be stable. Further, for this purpose, the address signal U
Is generated by the address selection circuit 6 which generates the address signal U.
It is necessary to output the read address “Q” on the top.

In the period of T3, a character pattern "N" of a line "N" to be scanned is generated for generating a frame pattern "Y" and displaying an original character pattern "P".
Then, during this period, the address selection circuit 6 outputs "N" to the address signal L at this timing, and the character generator 7 receives this and the character code "G" as the character signal P. The pattern in the "N" th row, that is, the character pattern "P" is read from the matrix pattern of the character code "G" .During this time, the display data RAM 5 is used because the character generator 7 uses the character code "G".
It is necessary that the character code "G" read from the character signal G onto the character signal G is stable. For this purpose, the address signal U input to the display data RAM 5 needs to be stable. Further, for this purpose, it is necessary that the address selection circuit 6 generating the address signal U outputs the read address “Q” on the address signal U.

In the period T4, the character pattern on the row next to the row "N" to be scanned is read out to generate the border pattern "Y". Therefore, during this period, the address selection circuit 6 sets the address signal L to "(N +
In response to this and the character code "G", the character generator 7 reads out the pattern of the "(N + 1)" line from the matrix pattern of the character code "G" as the character signal P. Also, the character generator 7 uses the character code
G ”, the character code“ read out from the display data RAM 5 onto the character signal G ”
G "must be stable. For this purpose, the address signal U which is an input to the display data RAM 5 needs to be stable. Further, for this purpose, the address signal U
Is generated by the address selection circuit 6 which generates the address signal U.
It is necessary to output the read address “Q” on the top.

The serial conversion circuit 8 has a shift register for converting parallel data into serial data. Usually, three sets of shift registers are used to process three lines of character patterns required for generating a border pattern. , A character pattern “P” consisting of a plurality of bits and a character pattern in both adjacent rows are latched in parallel, and after receiving a dot clock D, the character pattern “P” and the generated border are The pattern “Y” is serially output dot by dot. The video signal generated by the character video signal generation circuit 13 and sequentially output one dot at a time is combined with another video signal E depending on the device and displayed on the CRT 9.

As described above, the conventional superimposition of a character on an image
Although the character video signal generation circuit 13 has been described as a specific example of the video display device that displays images by imposing , the write synchronization circuit 4 is particularly described. A conventional write synchronization circuit 4 is disclosed in Japanese Patent Laid-Open Publication No. 63-12408.
4, as disclosed in Japanese Patent Laid-Open Publication No. 1-124891, etc., it is provided to prevent flicker on the screen.
That is, the display data RAM 5 stores the character code “G”.
Is output, an address signal A for writing is selected and output as the address signal U, and the character signal G is output.
The upper character code becomes undefined. The character pattern on the pattern signal P output by the character generator 7 is also specified by the specified character code. As a result, an undesired flicker appears on the screen because a part of the pattern is not to be originally displayed. In order to eliminate such inconveniences, the conventional write synchronization circuit 4 uses a period of the horizontal retrace time and the vertical retrace time of the scanning line (so-called invalid screen period) in which the reading from the display data RAM is not performed. ), The write synchronization signal S is output.

[0019]

However, the conventional configuration has
In the video display device , the writing to the display data RAM is performed only by using the period of the invalid screen, so the data transfer speed and timing are limited .
In such a case, there is a problem that the update of the display screen is delayed, and the processing of the microcomputer is delayed .

An object of the present invention is to solve such a problem of the prior art. A simple circuit is used to write data into a display data RAM even during scanning of an effective screen. Superimposed characters that can be performed and that do not show flickering on the screen
It is intended to provide a video display device suitable for use .

[0021]

In order to achieve this object, a video display apparatus according to the present invention has a configuration in which a code data latch is provided in a circuit having a conventional configuration, and the code data latch reads from a display data RAM. The received character code is temporarily received and held, and the held character code is output to the character generator. And the character generator
Receiving character code from latch for framing
Send multiple character patterns to serial conversion circuit
And, in response to a control signal from the microcomputer, calligraphy
Write synchronizing circuit, in which the code data latch outputs a write included synchronization signal <br/> when not receiving a character code from the display data RAM.

[0022]

According to the above arrangement, the conventional video display device is used.
The difference is that there is a timing at which writing to the display data RAM is possible even within the display time of each of a plurality of character patterns that may exist in one scan of the effective screen. That is, during the period of scanning the width of one character pattern, reading of the character pattern is performed a plurality of times in order to generate a border pattern, but it is noted that the character code given to the character generator is the same during this period. Then, if the code data latches the character code read from the display data RAM, the display data R
The reading from the AM may be performed only once. When the character generator receives the character code from the code data latch and reads the character pattern, the output of the display data RAM may be anything. Therefore, at this timing, even when writing to the display data RAM, undesired flicker does not appear on the screen.

The operation of the circuit at this time will be described in detail.
At the beginning of the period (T0) for scanning the width of the character pattern (T1), reading from the display data RAM is performed once. Specifically, the address selection circuit sends an address signal generated from the row selection signal R and the digit selection signal C to the display data RAM, and in response to the address signal, the display data RAM outputs a designated character code. . This character code is held by the code data latch.

In the period (T0) for scanning the width of one character pattern, a period (T1) for reading from the display data RAM is followed by a period for continuing reading from the character generator (for a period of (T2, T3, T4). ) Done. Reading from the character generator is performed a plurality of times (usually three times) to perform framing. At this time, the character code received by the character generator needs to be stable.

In the circuit of the present invention, the character code received by the character generator is not directly output from the display data RAM, but is held and output by the code data latch. Even if the output of the data RAM is undefined, the character code received by the character generator is stable, so that the character pattern is not disturbed and undesired flicker does not appear on the screen.

Therefore, the write synchronizing circuit performs the scan period of the invalid screen (the horizontal retrace time and the vertical retrace time of the scan line).
In addition, during the reading period from the character generator, a write synchronization signal is output when a control signal is received from the microcomputer, and writing to the display data RAM can be performed, so that the microcomputer waits a long time for data transfer. There is no need for efficient data transfer and quick screen updates.

The character code includes JIS and A
The information is not limited to the code defined by the SCII code or the like, and may include color information, blinking information, and the like.

[0028]

An embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram mainly showing a character video signal generation circuit portion of a video display device according to an embodiment of the present invention, and corresponds to FIG. 3 showing a conventional example. FIG. 2A is an example of a character pattern and a border pattern surrounding dots of up, down, left, and right. FIG. 2B is a time table for explaining the relationship between signals around the code data latch.

The configuration of the video display device in this embodiment is different from that of the prior art shown in FIG. 3 in that a code data latch 25 is newly provided and a write synchronization circuit 4 is provided.
Has been improved to become the write synchronization circuit 24. The code data latch 25 stores the character code "G" on the character signal G read from the display data RAM 25.
The character code "G" is output to the character generator 7 as a character signal F. When the code data latch 25 does not receive the character signal G when receiving the control signal from the microcomputer 1 and the control signal in accordance with the data signal B when the code data latch 25 does not receive the character signal G, the write synchronization signal S is output.

With reference to the timing table shown in FIG. 2, a detailed description will be given of the fact that writing to the display data RAM 5 can be performed even during the display time of each character pattern according to the above configuration. As in the conventional example, the period for scanning the width of one character pattern is set to T0.
The time of T0 is divided into four times T1, T2, T3, and T4.

During the period T1, the address selection circuit 6
The read address “Q” generated from the row selection signal R and the digit selection signal C is used as an address signal U as the display data R
Send to AM5. Thereby, the character code "" stored at the address "Q" of the display data RAM 5 is displayed.
G "is read out as the character signal G.
In order to substitute the output of the display data RAM 5, the code data latch 25 receives one bit of the digit selection signal C as a clock signal, and receives and holds the character code "G".

During the period T2, the character code "G" held by the code data latch 25 is output as the character signal F instead of the display data RAM5. To generate the framing pattern "Y", the line to be scanned "
It is necessary to read the character pattern in the row next to N ". Therefore, during this period, the address selection circuit 6 generates and outputs" (N-1) "to the address signal L at this timing. The character generator 7 reads the character pattern in the "(N-1)" line from the matrix pattern for one character of the character code "G" as the pattern signal P. During this time, the display data R
Since AM5 is not restrained, the write synchronization circuit 24
Outputs a write synchronization signal S when receiving a control signal from the microcomputer 1 in accordance with the control and data signal B. Therefore, during this timing T2, upon receiving this signal S, the address selection circuit 6
The address "A2" on the address signal A is added to the address signal U.
Select and output. Thereby, the display data RAM 5
Is written with the character code "W2" on the character signal W.

At time T3, the character code "G" held by the code data latch 25 is output as the character signal F instead of the display data RAM5. During this period, the address selection circuit 6 outputs "N" to the address signal L. In response to this, the character generator 7 reads, as the pattern signal P, the character pattern "P" on the "N" th line from the matrix pattern for one character of the character code "G". During this time, since the display data RAM 5 is not restrained, the write synchronization circuit 24 outputs the write synchronization signal S when receiving the control signal from the microcomputer 1 in accordance with the control and data signal B. Therefore, this timing T3
During the period, the address selection circuit 6 receives the signal S.
Means that the address "A" on the address signal A is applied to the address signal U.
3 "and outputs the selected data.
The character code “W3” on the character signal W is input to M5.
Is written.

During the period T4, the character code "G" held by the code data latch 25 is output as the character signal F instead of the display data RAM5. To generate the framing pattern "Y", the line to be scanned "
It is necessary to read the character pattern in the row next to "N". Therefore, during this period, the address selection circuit 6 generates and outputs "(N + 1)" to the address signal L at this timing. The generator 7 reads the character pattern of the "(N + 1)" line from the matrix pattern for one character of the character code "G" as the pattern signal P. During this time, the display data RAM 5 is not restricted, so the writing is performed. Synchronous circuit 2
4 receives the control signal from the microcomputer 1 in accordance with the control and data signal B,
Is output. In response to the signal S during the timing T4, the address selection circuit 6 selects and outputs the address "A4" on the address signal A as the address signal U. Thus, the character code "W4" on the character signal W is written into the display data RAM5.

Thus, in the circuit of the present invention,
Character code received by character generator 7 "
G "is not directly output from the display data RAM 5, but is instead held and output by the code data latch 25. Therefore, during this time, the display data RAM 5
Even if the output of 5 is undefined, the character generator 7
Character code "G" on character signal F received by
Is stable and no flickering appears on the screen.

Therefore, in addition to the invalid screen scanning period,
Even during the scanning period of the effective screen, the microcomputer 1 can write to the display data RAM 5 in the reading periods T2, T3, and T4 from the character generator 7, that is, in about ／ of the time.

The writing of the effective screen during the scanning period, which is a feature of the present invention, has been described above. Other operations are the same as those of the conventional example.

[0038] because it is possible to use the reading of the time required to generate the features framing pattern of the present invention, the configuration of the present invention, television to superimpose a character or a title or the like with a border Ya The present invention is also applicable to a character video signal generation circuit of a video display device such as a VTR, a video camera, and a laser disk.

[0039]

As described above, according to the video table of the present invention,
In the display device , by adding a simple circuit, data from the microcomputer is written to the display data RAM without flickering even during the scanning of the effective screen in addition to the scanning period of the invalid screen. Can be framed display
When superimposing a character with
In addition, there is an effect that the data can be efficiently transferred without waiting for the microcomputer and the screen can be updated quickly.

[Brief description of the drawings]

FIG . 1 is a block diagram mainly showing a character video signal generation circuit portion of a video display device according to an embodiment of the present invention.

FIG . 2 is an example (a) of a character pattern in a video display device , a framing pattern generated from the character pattern and enclosing upper, lower, left and right dots, and a signal around a code data latch which is a feature of the character display device of the present invention; 5B is a time table (b) for explaining the relationship of FIG.

FIG . 3 is a diagram showing a configuration of a conventional video display device , and particularly is a block diagram of a character video signal generation circuit portion.

Claims (1)

(57) [Claims] 1. A write address register for holding and outputting a first address signal received from a microcomputer; a write data register for holding and outputting a first character code received from the microcomputer; An address selection circuit that receives a row selection signal that determines a vertical position, a digit selection signal that determines a horizontal position, and a first address signal, and generates a second address signal and a third address signal; Display data R for storing a code and reading out and outputting a second character code stored therein at an address indicated by a second address signal.
AM, a write synchronization circuit for receiving a control signal from the microcomputer and the digit selection signal, and transmitting a write synchronization signal to the address selection circuit at a timing at which writing to the display data RAM is possible; Receiving the code, selecting a corresponding one-character matrix pattern, receiving a third address signal, and selecting the corresponding one from the matrix pattern.
A character generator for outputting a character pattern of rows, the character generator a plurality of the character pattern needed to generate the framing pattern for one character
And a serial conversion circuit for receiving and holding the write synchronization signal and sequentially outputting one bit at a time for each dot clock, and receiving the write synchronization signal, the address selection circuit selects a first address signal and outputs it as a second address signal. In response to this, the display data RAM stores a first character code at an address designated by a second address signal , and the serial conversion circuit
Generates a framing pattern and generates a character
A video data latch for receiving and holding a second character code and outputting the character code, wherein the character generator receives the character code from the code data latch and forms the border. For more than one of the above
It sends the character patterns in the serial converter circuit
Is intended, the write synchronizing circuit receives a control signal from the microcomputer, when the code data latch does not receive a second character code from the data RAM, and outputs the write synchronizing signal, the display Video writing to data RAM
Display device.