JPH0565184U - LCD television receiver - Google Patents

Abstract

(57) [Abstract] [Purpose] To prevent beat interference due to harmonics that accompany the driving of liquid crystal displays. [Structure] When a channel demodulation output of a television broadcast wave is displayed on a liquid crystal display 5 by two-dimensional scanning according to a system clock, a horizontal synchronization signal obtained from a channel demodulation circuit 3 is multiplied by 2N by a phase locked loop 12. To generate the system clock and switch the multiplication ratio 2N of the phase locked loop 12 so that the frequency band of the harmonic component of the system clock is out of the broadcast wave band of the channel selected by the channel selection demodulation circuit 3. Due to
The beat interference caused by the harmonic component of the system clock jumping into the channel selection demodulation circuit 3 is suppressed.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a liquid crystal television receiver for suppressing beat interference due to harmonics associated with a system clock of a liquid crystal display.

[0002]

[Prior Art]

 Liquid crystal displays have an active matrix method in which a thin film transistor for driving the liquid crystal is arranged for each pixel and each pixel is driven in sequence, and a simple method in which a voltage is applied to transparent electrodes arranged vertically and horizontally to directly drive the liquid crystal between the electrodes. Although roughly divided into matrix systems, the active matrix system is superior to the simple matrix system in terms of contrast, color purity, and visual dependence, and is suitable for screen display with a screen size of 2-3 inches or more than the pocket type. Is used exclusively for the active matrix method.

A liquid crystal television receiver 1 shown in FIG. 7 includes a channel demodulation circuit 3 and a clock generation circuit 4 on a liquid crystal display unit 2 for a laptop personal computer so that a television broadcast wave can be projected. It is added. The liquid crystal display unit 2 includes a liquid crystal display 5 of 680 × 480 pixels, a DA converter 6 for converting an RGB signal given as digital data into an analog signal, a horizontal start pulse, a vertical start pulse and a shift clock, and a liquid crystal display. A liquid crystal drive circuit 7 for two-dimensionally scanning the display 5 is integrated. The tuning demodulation circuit 3 demodulates the television broadcast wave captured by the reception antenna 8 in accordance with a tuning command given to the tuning microcomputer 9 via a touch key or a remote controller. The same one as that used for the CRT television receiver is used, and the composite video signal is divided into RGB signals and horizontal and vertical synchronizing signals Hd and Vd and output.

Driving the liquid crystal display 5 requires a circuit that is not found in a general CRT television receiver, and one screen is composed of two 1-field screens each including 262.5 scanning lines. A scan conversion circuit 10 for converting from interlaced scanning to sequential scanning that forms one screen with 525 scanning lines, and various types for specifying drive timing for each pixel that forms a dot matrix. The clock generation circuit 4 for supplying a pulse and a clock is a circuit peculiar to the liquid crystal television receiver 1. The scanning conversion circuit 10 scans by sending the output of the AD converter 11 which converts the RGB signal output from the channel selection demodulation circuit 3 into digital data to the built-in line memory and reading it at twice the writing speed. The linear density is converted to double density, and the interlaced signal is converted to a non-interlaced signal. The RGB signal converted into the non-interlaced signal is sent to the DA converter 6 in the liquid crystal display unit 2 and converted into an analog signal, and then supplied to the pixels dot-sequentially designated by the liquid crystal drive circuit 7. .. The clock generation circuit 4 multiplies the horizontal synchronization signal Hd (frequency fh) sent from the channel selection demodulation circuit 3 by 2N by the phase locked loop 12 to generate a system clock of frequency 2fs (= 2Nf h). Generates a horizontal start pulse, vertical start pulse, or shift clock according to the system clock. As is well known, the phase-locked loop 12 comprises a phase comparator 13, a low-pass filter 14, a voltage-controlled oscillator 15 and a 1 / 2N frequency divider 16 to form a loop loop. Gives a system clock having a frequency of 2fs before being divided by 1/2 by the frequency divider 16 and a clock having a frequency fs of 1/2 thereof. The clock of frequency fs is used as the operation clock of the AD converter 11 and the write clock of the scan conversion circuit 10, while the system clock of frequency 2fs is the read clock of the scan conversion circuit 10 and the operation of the DA converter 6. It is used as a clock and a shift clock for the liquid crystal drive circuit 7.

The shift clock for the liquid crystal drive circuit 7 is actually a system clock that passes through the frequency divider 16 in the phase-locked loop 12 and a decoder 17 connected outside the loop. .. In addition, the horizontal start pulse that determines from which shift clock the horizontal row of pixels of the liquid crystal display 5 is counted from the horizontal synchronizing signal is the counter of the counter built in the frequency divider 16 in the phase locked loop 12. The decoder 17 decodes the count output, and the decoder 17 logically determines that the count value of the counter has reached a predetermined constant value. Furthermore, the vertical start pulse for determining from which shift clock the vertical pixel row of the liquid crystal display 5 is counted from the vertical synchronizing signal Vd is the vertical start pulse of the frequency divider 16 in the phase-locked loop 12. The output is counted by a counter in the frequency divider 18 which is reset by the vertical synchronizing signal Vd, and the decoder 17 logically judges that the count value of this counter reaches a predetermined constant value.

[0006]

[Problems to be solved by the device]

 The above-mentioned conventional liquid crystal television receiver 1 uses a clock having a frequency fs that is four times the color sub-carrier frequency as the operation clock of the AD converter 11 and the write clock to the line memory in the scan conversion circuit 10. In addition, since the system clock with a frequency of 2 fs is used as the read clock of the line memory in the scan conversion circuit 10 and the operation clock of the DA converter 6, the harmonics generated as a frequency that is an integral multiple of the system clock. When the component has a high risk of invading the broadcast wave band and, for example, the multiplication ratio of the phase-locked loop 12, that is, the division ratio 2N of the frequency divider 18 is set to 900 × 2, as shown in FIG. Channel selection for channels 4, 9, 15, 19, 24, 29, 34, 38, 43, 48, 53, 57, 62 of John's broadcast wave. Harmonics jumped to the circuit 3 has had the problem that would cause beat interference.

[0007]

[Means for Solving the Problems]

 This invention solves the above-mentioned problems, and displays a channel demodulation circuit for receiving and demodulating television broadcast waves and an output video signal of this channel demodulation circuit on a liquid crystal display by two-dimensional scanning. Liquid crystal display unit, a clock generation circuit that multiplies the horizontal synchronization signal obtained from the channel selection demodulation circuit by a phase locked loop, and generates a system clock required for the two-dimensional scanning, and a high harmonic component of the system clock. A beat interference suppressing means for switching the multiplication ratio of the phase locked loop and suppressing beat interference so that the frequency band of is out of the broadcast wave band of the channel selected by the tuning and demodulating circuit. It is a feature.

[0008]

[Action]

 In this invention, when the demodulation output of the television broadcast wave is displayed on the liquid crystal display by two-dimensional scanning according to the system clock, the horizontal synchronizing signal obtained from the demodulation demodulation circuit is multiplied by the phase locked loop. By generating the system clock and switching the multiplication factor of the phase-locked loop so that the frequency band of the harmonic component of the system clock is out of the broadcast wave band of the channel selected by the tuning / demodulation circuit. It suppresses beat interference caused by the harmonic components of the clock jumping into the channel demodulation circuit.

[0009]

【Example】

 An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a circuit configuration diagram showing an embodiment of the liquid crystal television receiver of the present invention, FIG. 2 is a signal waveform diagram of each part of the circuit shown in FIG. 1, and FIG. 3 shows a relationship between a multiplication ratio and an image. FIG. 4 is a diagram showing the relationship between the multiplication ratio and the overscan distortion rate, and FIG. 5 is a diagram showing the relationship between the multiplication ratio and the harmonics.

The liquid crystal television receiver 21 shown in FIG. 1 switches the multiplication ratio 2N of the phase locked loop in the clock generation circuit in conjunction with the selected channel so that the harmonic components of the system clock do not cause beat interference. In addition to the configuration, the image is always displayed in the central portion of the liquid crystal display 5 even if the system clock is changed. As the beat interference suppressing means for suppressing beat interference, here, a multiplication ratio memory 22 storing a multiplication ratio 2N selected for each channel of a television broadcast wave, and a multiplication ratio memory 22 in response to designation of a selected channel The CPU 23 is used to read out the multiplication ratio 2N corresponding to the channel and set it in the frequency divider 16 in the phase locked loop 12.

By the way, when selecting the system clock, a condition is imposed here that the overscan distortion ratio is suppressed to 5% or less. That is, with respect to the horizontal synchronizing frequency 2fh (= 31.46 kHz) which has been subjected to the double density conversion, the image display period corresponding to 680 pixels in the horizontal direction of the liquid crystal display 5 is 26.4 μs as shown in FIG. Becomes Of these, when the horizontal effective display period is 640 pixels, the overscan rate E, which is represented by the ratio of the effective display period in the video display period, is represented by 640 / 26.4 · 2fs, and the overscan distortion occurs. The rate is represented by (1-E) / 2. Therefore, the relationship between the multiplication ratio 2N and the overscan distortion ratio is as shown in Fig. 4. As can be seen from this, in order to suppress the overscan distortion ratio to 5% or less, the multiplication ratio must be divided. The frequency division ratio 2N of the device 16 must be 856 × 2 or less.

Further, when the multiplication ratio (frequency division ratio) 2N is set to 856 × 2 or less, when the relation between the multiplication ratio 2N and the harmonics is considered, the relation as shown in FIG. 5 becomes clear. As is clear from this, the 4th to 30th harmonics of the system clock have entered the broadcast wave band, and in order to prevent beat interference, multiple harmonics that do not invade the broadcast wave band can be prevented. It turns out that the system clock has to be selected. Therefore, if the overscan distortion is 5% or less and two harmonics of either channel are out of the broadcast wave band for any channel, for example, if a multiplication ratio of 808 × 2 and 832 × 2 is selected, When the multiplication ratio is 808 × 2, the frequency 2fs of the system clock is 25.42 MHz, so that the second, fifth, ninth, 15,19,23,27,32,36,40,44,49,53,57,61 Harmonics enter each channel. When the multiplication ratio is 832 × 2, the system clock frequency 2fs is 26. Since the frequency is 17 MHz, the harmonic wave invades each of the channels 3, 6, 10, 13, 17, 21, 21, 30, 30, 35, 39, 43, 48, 52, 56, 61. Therefore, beat interference can be avoided by switching the system clock to at least two types except for the 61st channel which receives the intrusion of the harmonic at any multiplication ratio. For the 61st channel, beat interference can be eliminated by using a multiplication ratio of 800 × 2, for example.

In the embodiment, the multiplication ratio memory 22 stores three kinds of multiplication ratios 2N that do not cause beat interference with the selected channel as an address, and the tuning microcomputer 9 receives the tuning instruction. At this time, the CPU 23, which controls the liquid crystal television receiver 21 as a whole, reads out the multiplication ratio 2N corresponding to the channel designated to be tuned from the multiplication ratio memory 22, and outputs it to the frequency divider 16 in the phase locked loop. Set to. That is, for example, when the third channel is selected, the multiplication ratio 808 × 2 is selected, and when the second channel is selected, the multiplication ratio 832 × 2 is selected, and the 61st channel is further selected. When is selected, the multiplication ratio 800 × 2 is selected.

When the multiplication ratio 2N is switched, the change in screen size due to the change in system clock becomes a problem. That is, if the system clock is switched from low speed (multiplication ratio N1) to high speed (multiplication ratio N2), one scan line of the received television signal is sampled at a higher speed within the defined effective display period. As shown in FIGS. 3 (A) and 3 (B), even if the same video signal is used, the image is horizontally expanded and displayed even if the same video signal is displayed. It will be. Further, as the image expands in the horizontal direction, the center point of the image also moves to the right of the display screen of the liquid crystal display 5. Therefore, the horizontal width of the image is subject to expansion or compression depending on the multiplication ratio of 2N, while the center point of the image is always in the display screen of the liquid crystal display 5 even if the multiplication ratio of 2N changes. The horizontal start pulse generation timing is changed according to the multiplication ratio of 2N so that it is located at the center. That is, the time interval Tc from the horizontal synchronizing signal to the midpoint of the effective display period is invariable, and its value is also defined by the television signal standard. Therefore, when a system clock corresponding to a multiplication ratio of 2N is given, the number of pixels existing in the above time interval Tc is calculated as Tc / (1 / 2fs) = 2Tcfs. By subtracting 1/2 the number of pixels of the image period, that is, 340, it is possible to determine the number j (= 2Tcfs-340) of shift clocks from the horizontal synchronizing signal until the horizontal start pulse is generated. In the embodiment, the multiplication ratio memory 22 stores the multiplication ratio 2N and the number j of shift clocks until the horizontal start pulse as a pair in the address of the selected channel. When the station channel is designated, in parallel with switching the multiplication ratio 2N, the CPU 23 works on the decoder 17 to switch the generation timing of the horizontal start pulse so that the midpoint of the video display period coincides with the center of the screen. be able to.

As described above, according to the liquid crystal television receiver 21, the several harmonics generated accompanying the system clock generated by the phase locked loop 12 are obtained by preliminary trial calculation, and Since the system clock is selected so as to avoid the 6 MHz occupied band of the television broadcast wave and the selected harmonic is selected according to the selected broadcast channel, a safe multiplication ratio that has been confirmed in advance 2 It is possible to generate a system clock using N, and it is possible to reliably prevent beat interference caused by a harmonic component of the system clock used for two-dimensional scanning of the liquid crystal display 5 jumping into the tuning / demodulating circuit 3. .. Also, when a channel is selected, the corresponding multiplication ratio 2N can be read from the multiplication ratio memory 22 together with the designation of the selected channel, and a safe multiplication ratio 2N can be set automatically, so that the liquid crystal television reception image can be received. The beat interference can be suppressed without imposing any burden on the user of the machine 21. Furthermore, when a multiplication ratio of 2N is set for the phase locked loop 12, the drive timing of the liquid crystal display 5 is changed according to the multiplication ratio of 2N, and the midpoint of the horizontal image display period is set on the liquid crystal display 5. Since the configuration is such that it is displayed in the center, when changing the frequency of the system clock to suppress beat interference, the change in the system clock causes the adverse effect of expanding and contracting the image size in the horizontal direction. The image is always displayed in the center of the liquid crystal display 5 regardless of the change of the image size, and the visual discomfort can be eliminated.

In the above embodiment, when the channel selection command is received, the CPU 23 sets the multiplication ratio 2N read from the multiplication ratio memory 22 in accordance with the channel selection channel. Like the liquid crystal television receiver 31 shown, there are provided multiplication ratio latch circuits 32, 33 and 34 for holding three types of multiplication ratios 2N, for example 800 × 2,808 × 2,832 × 2, and these latch circuits. It is also possible that the user connects the units 32, 33, and 34 to the CPU 23 via the changeover switch 35 that is manually switched by the user. In this embodiment, when the user who actually sees the screen determines that the beat disturbance has occurred, the beat disturbance can be avoided by switching the changeover switch 35 by his / her own will. This imposes a burden on the user to some extent, but it is possible to configure the beat interference suppression means with the minimum necessary circuit.

[0017]

[Effect of the device]

 As described above, the present invention, when displaying the demodulation output of the television broadcast wave on the liquid crystal display by two-dimensional scanning in accordance with the system clock, changes the phase of the horizontal synchronizing signal obtained from the channel demodulation circuit. A system clock is multiplied by a locked loop to generate a system clock, and the phase-locked loop multiplication ratio is set so that the frequency band of the harmonic component of the system clock is out of the broadcast wave band of the channel selected by the channel demodulator. Because of the switching configuration, several harmonics generated with the system clock generated by the phase-locked loop are calculated in advance by trial calculation, and these harmonics are tuned to 6 MHz, which is the occupied band of the television broadcast wave. Select the system clock that you want to avoid and select it according to the selected broadcast channel. With consideration, it is possible to generate a system clock using a safe multiplication ratio that has been confirmed in advance, so that the harmonic components of the system clock used for the two-dimensional scanning of the liquid crystal display can jump into the channel selection demodulation circuit. This has the excellent effect of being able to reliably suppress the beat interference that occurs in.

In addition, the present invention provides the beat interference suppressing means from the multiplication ratio memory that stores the multiplication ratio selected for each channel of the television broadcast wave and the multiplication ratio memory that receives the designation of the selected channel. By configuring the setting unit that reads the multiplication ratio corresponding to the channel and sets it to the phase locked loop, when the channel is selected, the selected channel is specified and the corresponding multiplication ratio is read from the multiplication ratio memory. It is possible to automatically set the required multiplication ratio, and this makes it possible to suppress beat interference without imposing any burden on the user of the liquid crystal television receiver.

Further, according to the present invention, the beat disturbance suppressing means is switched to a multiplying ratio holding means for holding at least two kinds of multiplying ratios so that they can be arbitrarily selected, and the beat ratio holding means is switched by an external operation. The multiplication ratio is held as analog data or digital data by selecting the multiplication ratio from the multiple multiplication ratios held by the means in accordance with the switching mode and comprising a changeover switch for setting the phase locked loop. In addition to the multiplication ratio holding means, it is only necessary to prepare a multi-input / single-output type changeover switch that selects and outputs only one of the same number of inputs as the number of multiplication ratios held in the multiplication ratio holding means. The beat disturbance can be easily suppressed, and the operation of the changeover switch is switched by the user's own will when the beat disturbance actually occurs when the user looks at the screen. This imposes a certain amount of burden on the user side, but there is an effect that the beat interference suppression means can be configured with the minimum necessary circuit.

Further, according to the present invention, when the multiplication ratio is set for the phase locked loop, the drive timing of the liquid crystal display is changed according to the multiplication ratio, and the middle point of the horizontal image display period is the liquid crystal display. By controlling so that it is displayed in the center of the display, when the frequency of the system clock is switched to prevent beat interference, the problem that the change in the system clock causes horizontal enlargement and reduction of the image size By preventing the image from moving to the left or right of the liquid crystal display even if the size is changed, the visual discomfort can be sufficiently eliminated, and the horizontal start pulse is switched in circuit in conjunction with the change of the system clock. The system clock and horizontal start pulse should be paired in accordance with the selected channel. By doing so, there is an effect that it can be dealt with reliably.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of a liquid crystal television receiver of the present invention.

FIG. 2 is a signal waveform diagram of each part of the circuit shown in FIG.

FIG. 3 is a diagram showing a relationship between a multiplication ratio and an image.

FIG. 4 is a diagram showing a relationship between a multiplication ratio and an overscan distortion rate.

FIG. 5 is a diagram showing a relationship between a multiplication ratio and harmonics.

FIG. 6 is a circuit diagram showing another embodiment of the liquid crystal television receiver of the present invention.

FIG. 7 is a circuit configuration diagram showing an example of a conventional liquid crystal television receiver.

FIG. 8 is a diagram showing a relationship between a multiplication ratio and harmonics.

[Explanation of symbols]

2 liquid crystal display unit 3 channel selection demodulation circuit 4 clock generation circuit 5 liquid crystal display 12 phase locked loop 21, 31 liquid crystal television receiver 22 beat interference suppression means (multiplication ratio memory) 23 beat interference suppression means, setting means, display control means (CPU) 32 to 34 beat interference suppressing means, multiplication ratio holding means (multiplication ratio latch circuit) 35 beat interference suppressing means (changeover switch)

Claims (4)

[Scope of utility model registration request] 1. A tuning demodulation circuit for receiving a television broadcast wave and tuning for demodulation, a liquid crystal display unit for displaying an output video signal of the tuning demodulation circuit on a liquid crystal display by two-dimensional scanning, and the tuning. A clock generation circuit that multiplies a horizontal synchronization signal obtained from a demodulation circuit by a phase locked loop to generate a system clock required for the two-dimensional scanning, and a frequency band of a harmonic component of the system clock is provided to the channel selection demodulation circuit. A liquid crystal television receiver, comprising: beat interference suppressing means for switching the multiplication ratio of the phase locked loop so as to deviate from the broadcast wave band of the selected channel. 2. The beat interference suppressing means corresponds to a multiplication ratio memory storing a multiplication ratio selected for each channel of a television broadcast wave, and a channel selected from the multiplication ratio memory when the channel is designated. 2. The liquid crystal television receiver according to claim 1, further comprising setting means for reading out a multiplication ratio to be set and setting it in the phase locked loop. 3. The beat disturbance suppression means is a multiplication ratio holding means for holding at least two types of multiplication ratios so that they can be arbitrarily selected, and a plurality of switching means which are switched in response to an external operation and held by the multiplication ratio holding means. 2. The liquid crystal television receiver according to claim 1, further comprising a changeover switch for selecting one of the multiplication ratios according to a switching mode and setting the phase locked loop. 4. When a multiplication ratio is set for the phase locked loop, the drive timing of the liquid crystal display is varied according to the multiplication ratio, and the midpoint of the horizontal image display period is the liquid crystal display. 2. The liquid crystal television receiver according to claim 1, further comprising display control means for controlling display on the center of the display screen.