JP3813097B2 - Video signal processor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a television receiver equipped with a display device such as a liquid crystal display, and relates to a display device and a video signal for improving display video image quality by suppressing beat disturbance due to harmonics associated with a system clock for video signal processing. The present invention relates to a processing apparatus.
[0002]
[Prior art]
Conventionally, there is a liquid crystal television receiver as a television receiver using a liquid crystal display as a display device. This conventional liquid crystal television receiver will be described below with reference to FIG.
[0003]
A liquid crystal television receiver 31 shown in FIG. 5 is obtained by adding a channel selection demodulation circuit 33 and a clock generation circuit 34 to a liquid crystal display unit 32 so that a television broadcast can be projected. The liquid crystal display unit 32 receives, as an example, a 680 × 480 pixel liquid crystal display 35, a DA converter 36 that converts RGB signals given as digital data into analog signals, a horizontal start pulse, a vertical start pulse, and a shift clock. A liquid crystal driving circuit 37 that two-dimensionally scans the liquid crystal display 35 is integrated. The channel selection demodulating circuit 33 selects and demodulates the television broadcast captured by the receiving antenna 38 in accordance with a channel selection command given to the channel selection microcomputer 39 via a touch key or a remote controller. The same one used for a television receiver is used, and the composite video signal is divided into RGB signals and horizontal and vertical synchronization signals HSY and VSY and outputted.
[0004]
Driving the liquid crystal display 35 requires a circuit that is not available in a general CRT television receiver, and 525 lines from interlaced scanning that form one screen with two screens of one field composed of 262.5 scanning lines. A scanning conversion circuit 40 for converting to sequential scanning that constitutes one screen with a plurality of scanning lines, and a clock for supplying various pulses and clocks for designating drive timing to each pixel constituting the dot matrix The generation circuit 34 and the like are circuits specific to the liquid crystal television receiver 31.
[0005]
The scan conversion circuit 40 sends the output of the AD converter 41 that converts the RGB signal output from the channel selection demodulation circuit 33 into digital data into the built-in line memory, and reads it out at a speed twice the writing speed. The density is double-density converted, and the interlace signal is converted to a non-interlace signal. The RGB signal converted into the non-interlace signal is sent to the DA converter 36 in the liquid crystal display unit 32 and converted into an analog signal, and then supplied to the pixels designated in a dot-sequential manner by the liquid crystal drive circuit 37.
[0006]
The clock generation circuit 34 multiplies the horizontal synchronization signal HSY (frequency fh) sent from the channel selection demodulation circuit 33 by 2N by a phase locked loop (hereinafter PLL) 42 to generate a system clock of frequency 2fs (= 2Nfh), A horizontal start pulse, a vertical start pulse, or a shift clock is generated according to this system clock. As widely known, the PLL 42 constitutes a loop with a phase comparator 43, a low-pass filtering circuit 44, a voltage-controlled oscillator 45, and a 1 / 2N frequency divider 46. From the voltage-controlled oscillator 45, A system clock having a frequency 2fs before being divided by 1 / 2N by the frequency divider 46 and a clock having a frequency fs ½ of the system clock are obtained. The clock of frequency fs is used as the operation clock of the AD converter 41 and the write clock of the scan conversion circuit 40, while the system clock of frequency 2fs is the read clock of the scan conversion circuit 40, the operation clock of the DA converter 36, and Used as a shift clock for the liquid crystal drive circuit 37.
[0007]
The shift clock for the liquid crystal drive circuit 37 is actually a system clock that passes through a frequency divider 46 in the PLL 42 and a decoder 47 connected to the outside of the loop. Further, the horizontal start pulse that determines the number of shift clocks to be driven from the horizontal synchronizing signal HSY when counting the horizontal pixel columns of the liquid crystal display 35 is the count output of the counter built in the frequency divider 46 in the PLL 42. Is decoded by the decoder 47, and the decoder 47 logically determines that the count value of the counter has reached a predetermined value. Furthermore, the vertical start pulse that determines the number of shift clocks to be driven from the vertical synchronization signal VSY when counting the vertical pixel columns of the liquid crystal display 35 is the output of the frequency divider 46 in the PLL 42 as the vertical synchronization signal. Counting is performed by a counter in the frequency divider 48 that is reset by VSY, and this is given by logically determining in the decoder 47 that the count value of this counter has reached a predetermined constant value.
[0008]
The conventional liquid crystal television receiver 31 uses a clock having a frequency fs four times the color subcarrier frequency as an operation clock of the AD converter 41 and a write clock to the line memory in the scan conversion circuit 40. In addition, since a system clock having a frequency of 2 fs is used as the read clock of the line memory in the scan conversion circuit 40 and the operation clock of the DA converter 36, the harmonic component generated as an integer multiple of the system clock is selected. There was a problem of jumping into the station demodulation circuit 33 and causing beat interference. As a method for suppressing the beat interference, for example, a liquid crystal television receiver described in Japanese Utility Model Laid-Open No. 5-65184 has been proposed. The liquid crystal television receiver described in Japanese Utility Model Laid-Open No. 5-65184 will be described as another conventional liquid crystal television receiver with reference to FIG.
[0009]
The liquid crystal television receiver 51 shown in FIG. 6 has the same reference numerals in common with the liquid crystal television 31 shown in FIG. The liquid crystal television receiver 51 shown in FIG. 6 is configured so that the PLL multiplication ratio 2N in the clock generation circuit is switched in conjunction with the selected channel so that the harmonic components of the system clock do not cause beat interference. Even if the clock is changed, the image is always displayed in the central portion of the liquid crystal display 35. Here, as beat disturbance suppression means for suppressing beat disturbance, a multiplication ratio memory 52 storing a multiplication ratio 2N selected for each channel of a television broadcast wave, and a multiplication ratio memory 52 in response to designation of a selected channel. The CPU 53 is used to read the multiplication ratio 2N corresponding to the channel from the CPU and set it in the frequency divider 46 in the PLL 42.
[0010]
By the way, when the system clock is selected, here, the condition that the overscan distortion rate is suppressed to 5% or less is imposed. That is, for the horizontal synchronization frequency 2fh (= 31.46 kHz) subjected to the double density conversion, the video display period corresponding to 680 pixels in the horizontal direction of the liquid crystal display 35 is 26.4 μsec. Of these, when the effective display period in the horizontal direction is 640 pixels, the overscan rate E represented by the ratio of the effective display period to the video display period is expressed by 640 / 26.4 · 2fs, and the overscan distortion The rate is represented by (1-E) / 2. Therefore, in order to suppress the overscan distortion rate to 5% or less, the multiplication ratio, that is, the frequency division ratio 2N of the frequency divider 16 must be 856 × 2 or less.
[0011]
In addition, when the multiplication ratio (frequency division ratio) 2N is 856 × 2 or less, the 4th to 30th harmonics of the system clock have entered the broadcast wave band, and in order to prevent beat interference, It should be understood that a plurality of system clocks that do not invade the broadcast wave band must be selected. Therefore, when the overscan distortion factor is 5% or less and, for each channel, two system clocks in which either harmonic component deviates from the broadcast wave band, for example, multiplication ratios 808 × 2 and 832 × 2 are selected, At a multiplication ratio of 808 × 2, the system clock frequency 2fs is 25.42 MHz, so that Harmonics enter each channel. In addition, since the frequency 2fs of the system clock is 26.17 MHz at a multiplication ratio of 832 × 2, the third, sixth, tenth, thirteenth, seventeenth, twenty-first, thirty-fifth, thirty-five, thirty-five, thirty-five, thirty-nine, thirty-four, fifty-second, fifty-second, Harmonics invade 61 channels. Accordingly, beat disturbance can be avoided by switching the system clock in at least two ways except for the 61st channel that receives the invasion of harmonics at any multiplication ratio.
For the 61st channel, beat interference can be eliminated by using, for example, a multiplication ratio of 800 × 2.
[0012]
The multiplication ratio memory 52 stores three types of multiplication ratios 2N that do not cause beat interference with the channel selection channel as an address. When the channel selection microcomputer 39 receives a channel selection command, the liquid crystal television receiver 51 is provided. The CPU 53 that performs overall control reads the multiplication ratio 2N corresponding to the channel designated for channel selection from the multiplication ratio memory 52, and sets this to the frequency divider 46 in the PLL. That is, for example, when the third channel is selected, the multiplication ratio 808 × 2 is selected, and when the second channel is selected, the multiplication ratio 832 × 2 is selected, and the 61st channel is selected. When stationed, a multiplication ratio of 800 × 2 is selected.
[0013]
Note that when the multiplication ratio 2N is switched, a change in the screen size accompanying a change in the system clock becomes a problem. That is, if the system clock is switched from the low speed (multiplication ratio N1) to the high speed (multiplication ratio N2), a sample of one scanning line of the received television signal is sampled at a higher speed within a predetermined effective display period. Therefore, even if the video signal is the same, the image is expanded and displayed in the horizontal direction as the system clock increases. As the image is expanded in the horizontal direction, the center point of the image also moves to the right of the display screen of the liquid crystal display 35.
[0014]
Therefore, the horizontal width of the image is accepted to be expanded or compressed in accordance with the multiplication ratio 2N, while the center point of the image is always the center of the display screen of the liquid crystal display 35 even if the multiplication ratio 2N changes. The generation timing of the horizontal start pulse is changed in accordance with the multiplication ratio 2N so as to be positioned in FIG. That is, the time interval Tc from the horizontal synchronization signal to the midpoint of the effective display period is unchanged, and the value is also defined by the television signal standard.
[0015]
Therefore, when the system clock corresponding to the multiplication ratio 2N is given, the number of pixels existing in the time interval Tc is obtained as Tc / (1 / 2fs) = 2Tcfs, and therefore the video display image period is calculated from the number of pixels 2Tcfs. By subtracting ½ of the number of pixels, that is, 340, it is possible to determine the number j (= 2Tcfs-340) of shift clocks from the horizontal synchronization signal until the horizontal start pulse is generated. The multiplication ratio memory 52 stores the channel selection channel as an address and stores the multiplication ratio 2N and the number of shift clocks j until the horizontal start pulse is issued as a pair. Therefore, the channel selection command is designated together with the channel selection command. At the same time as switching the multiplication ratio 2N, the CPU 53 works on the decoder 47 to switch the generation timing of the horizontal start pulse, so that the midpoint of the video display period can coincide with the center of the screen.
[0016]
[Problems to be solved by the invention]
The conventional liquid crystal television receiver shown in FIG. 5 has a clock having a frequency fs four times the color subcarrier frequency as an operation clock of the AD converter and a write clock to the line memory in the scan conversion circuit. In addition, since a system clock having a frequency of 2 fs is used as the read clock for the line memory in the scan conversion circuit and the operation clock for the DA converter, harmonic components generated as an integral multiple of the system clock are broadcast. When the frequency multiplication factor of the PLL, that is, the frequency division ratio 2N of the frequency divider is set to 900 × 2 in reality, the fourth, ninth, fifteenth, nineteenth, twenty-fourth, For channels 29, 34, 38, 43, 48, 53, 57, and 62, the harmonics jumping into the channel selection demodulation circuit cause beat interference. I had the challenge of Mau.
[0017]
Further, the other conventional liquid crystal television receiver shown in FIG. 6 obtains several harmonics generated in advance accompanying the system clock generated by the PLL by trial calculation, and these harmonics are obtained from the television. Since the system clock is selected so as to avoid the 6 MHz occupied band of the broadcast wave and selected according to the selected broadcast channel, the harmonic component of the system clock used for two-dimensional scanning of the liquid crystal display is selected. Beat disturbance caused by jumping into the demodulation circuit is suppressed. However, when the frequency of the system clock is switched to suppress beat interference, the change of the system clock causes a considerable increase or decrease in the horizontal direction of the image size, and the problem that the adverse effect cannot be eliminated. I had it.
[0018]
An object of the present invention is to provide a video signal processing apparatus capable of reliably suppressing beat interference caused by a harmonic component of a system clock and displaying with a constant image size.
[0019]
[Means for Solving the Problems]
The present invention solves the above-described problem, a channel selection demodulation circuit that receives and demodulates a television broadcast wave, a display device that displays an output video signal of the channel selection demodulation circuit, and a harmonic component A system clock generation circuit that generates a plurality of system clocks having different frequencies so that there is at least one clock that does not overlap with the broadcast wave band of the channel selected by the channel selection demodulation circuit, A system clock optimizing circuit for selecting one system clock out of the broadcast wave band of the channel selected by the channel selection demodulation circuit from among the system clocks generated by the system clock generation circuit; Depending on the system clock selected by the system clock optimization circuit, Change the setting of the number of samples outside the valid video period, And a scaling circuit for converting the video signal into a video signal having a number of samples suitable for the display device.
[0020]
The video signal processing apparatus of the present invention is characterized in that the system clock generation circuit generates an asynchronous clock to an output video signal of the channel selection demodulation circuit.
[0021]
Further, the video signal processing apparatus of the present invention stores selection data in which a system clock in which the frequency of the harmonic component does not overlap with the broadcast wave band of the channel is stored for each channel of the television broadcast wave. And an instruction means for reading the system clock data corresponding to the selected channel based on the selection data and instructing the system clock optimization circuit to select the system clock based on the selection data. It is characterized by that.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of a video processing apparatus according to the present invention will be described with reference to FIGS. 1 is a circuit configuration diagram showing an outline of an embodiment of a video signal processing apparatus of the present invention, FIG. 2 is a signal waveform diagram of each part of the circuit in FIG. 1, and FIG. 3 is a signal waveform of each part of the scaling and double speed conversion circuit in FIG. FIG. 4 and FIG. 4 are diagrams showing the relationship between the selected channel and harmonic interference.
[0023]
In FIG. 1, 1 is a receiving antenna, 2 is a channel selection demodulation circuit, 3 is a PLL composed of an LPF / synchronization separation circuit, a phase comparison / VCO circuit, and a counter, 7 is an AD converter, 8 is a YC separation circuit, 9 Is a color demodulation circuit, 10 is an RGB conversion circuit, 11 is a scaling circuit, 12 is a double speed conversion circuit, 13 and 14 are system clock generators, 15 is a system clock optimization circuit, 16 is a synchronization generation circuit, and 17 is a DA converter. Reference numeral 18 denotes a display device including a liquid crystal drive circuit 19 and a liquid crystal display 20, and a CPU 21.
[0024]
A channel selection demodulation circuit 2 that selects and demodulates a television broadcast captured by the reception antenna 1 in accordance with a channel selection instruction given to the CPU 21 through a touch key or a remote controller outputs a composite video signal. The AD converter 7, the YC separation circuit 8, the color demodulation circuit 9 and the RGB conversion circuit 10 convert the composite video signal output from the channel selection demodulation circuit 2, which is an NTSC or PAL analog video signal, to the ITU-R recommendation BT601. Decode into compliant RGB digital data as follows.
[0025]
Since the sampling clock for AD conversion conforms to ITU-R recommendation BT601, the subsequent system can be simplified as 13.5 MHz or its multiplied and low frequency. The higher one is desirable, and here it is 27 MHz. The PLL 3 generates a 27 MHz sampling clock for the operation of the AD converter 7 and a 13.5 MHz decode clock for the operations of the YC separation circuit 8, the color demodulation circuit 9, and the RGB conversion circuit.
[0026]
The PLL 3 has a widely known configuration. The LPF / synchronization separation circuit 4 separates the horizontal synchronization signal (frequency fh) from the composite video, and the phase comparison / VCO circuit 5 and the counter are based on the horizontal synchronization signal. The counter 6 generates a 27-MHz sampling clock and 1/2 of the 13.5-MHz decoding clock. The composite video signal sampled at 27 MHz by the AD converter 7 is downsampled to 13.5 MHz by the decimation filter in the YC separation circuit 8 and then separated into the Y signal and the C signal. The C signal is demodulated into a Cb signal and a Cr signal by the color demodulation circuit 9 and converted into an RGB signal together with the Y signal by the RGB conversion circuit 10.
[0027]
The RGB signal has the timing shown in FIG. 2A, and the data of the effective video period is upsampled by the interpolation filter in the scaling circuit 11 arranged at the subsequent stage, and further the line in the double speed conversion circuit 12 The scanning line is read at a speed twice as fast as the writing speed by the memory to convert the scanning line at a double speed, and the interlace signal is converted into a non-interlace signal. The synchronization generation circuit 16 is used for the operation of the liquid crystal drive circuit 19 according to the horizontal and vertical reference signals synchronized with the input composite synchronization signal supplied from the counter 6 and the system clock supplied from the system clock optimization circuit 15. A horizontal start pulse, a vertical start pulse, or a shift clock is generated. The RGB signal converted into the non-interlace signal is converted into an analog signal by the DA converter 18 in the display device 17, and then supplied to the pixels designated by the liquid crystal drive circuit 19 in a dot sequential manner.
[0028]
By the way, a system clock which is an operation clock of the display device 17 including the scaling circuit 11, the double speed conversion circuit 12, the DA converter 18 and the liquid crystal drive circuit 19 is supplied from the system clock optimization circuit 15. Need to be selected so as not to cause beat interference with respect to the receiving channel, which will be described below.
[0029]
The method of suppressing beat interference is to use two system clock generation circuits 13 and 14 that generate clocks of two frequencies fs1 and fs2 in which the frequency of the clock harmonic component does not overlap each other in the frequency band of all broadcast channels. The CPU 21 having prepared and storing the system clock selection data for each channel of the television broadcast wave in the built-in memory controls the system clock optimization circuit 15 in response to the designation of the channel selection channel, and outputs the system clock generation circuits 13 and 14. Is to switch. The output clock frequencies fs1 and fs2 of the system clock generation circuits 13 and 14 are selected so that the frequencies of the clock harmonic components do not overlap each other in the frequency band of all broadcast channels. On the other hand, the CPU 21 automatically instructs the system clock optimizing circuit 15 to select the clock that does not cause beat interference, thereby preventing beat interference.
[0030]
The selection of the system clock frequency is also related to the display size of the liquid crystal display 20 and the conversion ratio of the scaling circuit 11 corresponding to the display size. Here, a 16: 9 wide VGA panel (854 × 480) is used for the liquid crystal display 20 in consideration of a high-quality DVD image and the like.
[0031]
As shown in FIG. 2A, since the RGB video signal has 720 samples of effective video data, the interpolation filter in the scaling circuit 11 is used to upsample the number of horizontal samples 854 of the liquid crystal display 20. The horizontal conversion ratio in the scaling circuit 11 at this time is 32/27, and conversion data is obtained by weighting adjacent data as shown in FIG. Since the signal is still an interlace signal, the line memory in the double speed conversion circuit 12 reads the data at a speed twice as high as the write speed, and further weights adjacent data as shown in FIG. -By passing through the poration filter, the scanning lines are converted to a non-interlace signal by double speed conversion, so the number of effective scanning lines is also converted from 240 to 480. With this processing, data matched to a 16: 9 wide VGA panel (854 × 480) is obtained.
[0032]
Now, regarding the selection of the system clock frequency, 28.888 MHz was selected as the output clock frequency fs1 of the system clock generation circuit 13 as shown in FIG. Since the number of horizontal scanning lines of the output signal of the double speed conversion circuit 12 is twice the number of horizontal scanning lines of the input composite video signal, the horizontal scanning period Th1 is Th1 = Th / 2 = 31.778 μsec, and each field 262. The number of horizontal scanning lines, which was five, is 525. Here, the number of samples in the horizontal scanning period is 854 samples as described above. The setting of the number of samples other than the effective video period depends on the specification of the liquid crystal drive circuit 19, but here it is 64 samples. As a result, when the vertical frequency is 59.94 Hz, the output clock frequency fs1 of the system clock generation circuit 13 is selected as fs1 = (854 + 64) × 525 × 59.94 = 28.887 MHz.
[0033]
On the other hand, as the output clock frequency fs2 of the system clock generation circuit 14, 30.902 MHz was selected as shown in FIG. This is obtained by fs2 = (854 + 128) × 525 × 59.94 = 30.902 MHz as in the case of fs1, but here the number of samples other than the effective video period is set to 128 samples. As indicated by the crosses in the SCK1 column of FIG. 4, the harmonics of the clock frequency fs1 are the 4, 9, 16, 21, 26, 30, 35, 40, 45, 50, 55, 59 of the broadcast channel. It overlaps with the frequency band of the channel. On the other hand, the harmonics of the clock frequency fs2 set to 30.902 MHz are 1, 6, 12, 17, 22, 27, 32, 37, 42, 47 of the broadcast channel, as indicated by the X in the SCK2 column of FIG. It overlaps with the frequency bands of 53 and 58 channels. Comparing the “X” in the SCK1 column and the “X” in the SCK2 column in FIG. 4, it can be seen that there are no overlapping channels.
[0034]
Here, two frequencies of 28.887 MHz and 30.902 MHz are selected, but many other combinations are conceivable depending on the setting of the number of samples other than the effective video period and the display size of the liquid crystal display, as described above. Any combination that does not have channels with overlapping waves is acceptable.
[0035]
As described above, according to the signal processing apparatus of the present embodiment, several-order harmonics generated in association with the system clock are obtained in advance by trial calculation, and these harmonics are obtained for each channel 6 MHz of the television broadcast wave. Since a plurality of system clocks that do not overlap in the frequency band are selected and selected according to the selected broadcast channel, the scaling circuit 11, the double speed conversion circuit 12, the DA converter 18, and the liquid crystal drive circuit 19 are included. It is possible to reliably suppress beat disturbance caused by the harmonic component of the system clock that is the operation clock of the display device 17 jumping into the channel selection demodulation circuit 2.
[0036]
In addition, when the channel is selected, the CPU 21 that stores the selection data indicating the system clock to be selected for each channel in the built-in memory together with the designation of the channel to be selected automatically instructs the safe clock to optimize the system clock. Since the circuit is selected, beat disturbance can be suppressed without placing any burden on the actual user.
[0037]
【The invention's effect】
In the video processing apparatus according to the present invention, the frequency of the harmonic component of the system clock is selected when the channel demodulation signal of the television broadcast wave is displayed on a display device such as a liquid crystal panel from the above configuration and operation. The optimal system clock can be selected from multiple system clocks so that they deviate from the broadcast wave band of the channel, and scaling is performed to convert the video signal to the number of samples that matches the display size of the display device regardless of the system clock frequency. Since the system clock is selected, a system clock having a frequency at which the harmonics of the system clock do not overlap in the 6 MHz frequency band of each station of the television broadcast wave is selected to match the selected broadcast channel. The system clock can be operated without harmonic interference, and the system Beat interference caused by the harmonic component of the lock jumping into the channel selection demodulation circuit can be reliably suppressed. In addition, a natural image can be displayed because the display device can display a constant image size regardless of the system clock selection. Excellent effects such as being able to be displayed.
[0038]
In addition, the video processing apparatus according to the present invention is configured to operate the system clock of the display apparatus with an asynchronous clock having no correlation with the channel selection demodulation signal, so that the degree of freedom in system design is increased and the display of the display apparatus is displayed. Even when changes in size, specifications, etc. occur, it is possible to flexibly cope with it, and it is possible to simplify development and shorten the development schedule, which leads to excellent effects such as reducing the cost of the system.
[0039]
In addition, the video processing apparatus according to the present invention, when selecting a channel, designates the channel to be selected, and the instruction means that stores the system clock selection data for each channel in the built-in memory automatically generates a safe clock. Since the system clock optimizing circuit is instructed, beat disturbance can be suppressed without placing any burden on the user who actually uses it.
[Brief description of the drawings]
FIG. 1 is a circuit configuration diagram showing an outline of an embodiment of a video signal processing apparatus of the present invention.
FIG. 2 is a signal waveform diagram of each part of the circuit according to the present invention.
FIG. 3 is a signal waveform diagram of each part of the scaling and double speed conversion circuit in the present invention.
FIG. 4 is a diagram showing a relationship between a channel selection channel and harmonic interference in the present invention.
FIG. 5 is a circuit configuration diagram showing an example of a conventional liquid crystal television receiver.
FIG. 6 is a circuit configuration diagram showing an example of another conventional liquid crystal television receiver.
[Explanation of symbols]
1 Receiving antenna
2 Tuning demodulation circuit
3 Phase locked loop (PLL)
4 LPF / sync separation circuit
5 Phase comparison / VCO circuit
6 counter
7 AD converter
8 YC separation circuit
9 color demodulator
10 RGB conversion circuit
11 Scaling circuit
12 double speed conversion circuit
13 System clock generator
14 System clock generator
15 System clock optimization circuit
16 Synchronization generator
17 Display device
18 DA converter
19 Liquid crystal drive circuit
20 Liquid crystal display
21 CPU
31 LCD television receiver
32 LCD unit
33 Channel selection demodulation circuit
34 Clock generation circuit
35 Liquid crystal display
36 DA converter
37 Liquid crystal drive circuit
38 Receiving antenna
39 Tuning microcomputer
40 Scan conversion circuit
41 AD converter
42 Phase Locked Loop (PLL)
43 Phase comparator
44 Low-pass filtering circuit
45 Voltage controlled oscillator
46 1 / 2N divider
47 Decoder
48 divider
51 LCD television receiver
52 Multiplier ratio memory
53 CPU

Claims (3)

A channel selection demodulation circuit for receiving and broadcasting a television broadcast wave, a display device for displaying an output video signal of the channel selection demodulation circuit, and a frequency of a harmonic component are selected by the channel selection demodulation circuit. A system clock generating circuit for generating a plurality of system clocks having different frequencies so that there is at least one clock that does not overlap with the broadcast wave band of the selected channel, and a system clock generated by the system clock generating circuit A system clock optimization circuit that selects one system clock whose harmonic component frequency is out of the broadcast wave band of the channel selected by the channel selection demodulation circuit, and a system clock selected by the system clock optimization circuit in response, changing the number of samples set outside of the effective video period, the video signal display apparatus A video signal processing apparatus characterized by comprising a scaling circuit for converting into a suitable number of samples of the video signal.   2. The video signal processing apparatus according to claim 1, wherein the system clock generation circuit generates an asynchronous clock to the output video signal of the channel selection demodulation circuit.   For each channel of a television broadcast wave, when the selection data in which the frequency of the harmonic component is associated with a system clock that does not overlap with the broadcast wave band of the channel is stored, and the selected channel is designated 3. The system according to claim 1, further comprising instruction means for reading system clock data corresponding to the channel based on the selection data and instructing the system clock optimization circuit to select a system clock to be selected. Video signal processing device.

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