JPH0690416A - Display device - Google Patents

Abstract

PURPOSE:To display television signals of various systems on many kinds of display parts different in synchronizing frequencies and aspect ratios without damaging their aspect ratios by discriminating the system of an input television signal and subjecting it to such signal processing that this signal corresponds to the synchronous frequency and the aspect ratio of a display device. CONSTITUTION:Various data of the horizontal frequency, vertical frequency, the aspect ratio, etc., of a connected display device are inputted to a CPU 30a through an I/O control circuit 30f and a data bus 31 by a keyboard 46. The CPU 30a calculates a thinning rate for the display of a decoded MUSE signal on the display device. For example, when the signal is displayed on the display device having 4:3 aspect ratio without damaging its aspect ratio, the thinning rate is set to 7/20 in the vertical direction, and the CPU 30a outputs this thinning rate to a thinning, time conversion, and interpolation processing part 41 through the data bus 31 and an I/O control circuit 43.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device for outputting and displaying a television signal on a display such as a CRT (cathode ray tube) or a liquid crystal projector, and particularly to an NTSC signal or a high quality display. The present invention relates to a device capable of displaying a plurality of types of signals having different frequencies and aspect ratios such as a television signal.

[0002]

2. Description of the Related Art As is well known, in recent television broadcasting, a plurality of television signals such as EDTV signals and MUSE signals are mixed and broadcast in addition to ordinary NTSC signals. Nowadays, as a television receiver capable of receiving all such a plurality of television signals, for example, "National Technical Report V
ol.37 No.5 Oct.1991 ”," 36 type HDTV receiver TH-36HD1 "has appeared. This television receiver is based on the current NTSC BS / UHF.
In addition to receiving / VHF / CATV broadcasting, it is possible to receive MUSE high definition broadcasting.

FIG. 24 shows the structure of a conventional television receiver of this type. First, UHF / VHF / CA
Each television signal of TV broadcasting is received by the antenna 11, selected by the tuner 13 controlled by the system controller 12, converted into a baseband signal, and then supplied to one input end of the switch circuit 14. It The tuner 13 has a function of receiving and processing normal NTSC signals and EDTV signals.

A television signal of BS broadcasting is received by an antenna 15, is tuned by a tuner 16 controlled by a system controller 12 and converted into a baseband signal, and then is input to the other input of a switch circuit 14. Supplied on the edge. This tuner 16 is used for high definition broadcasting MUSE in addition to normal NTSC signals and EDTV signals.
It also has the function of receiving and processing signals.

The switch circuit 14 is controlled by the system controller 12, and the tuners 13 and 16 are controlled.
The baseband signals output from the NTSC decoder 17 and the MUSE decoder 18 are distributed and supplied. Of these, the NTSC decoder 17
The input baseband signal is R (red), G (green), B
It is converted into each color signal of (blue) and output to the scanning line conversion circuit 19.

This scanning line conversion circuit 19 converts 525 horizontal interlaced NTSC signals into 525 horizontal scanning lines.
The data is converted into a non-interlaced book (double speed conversion) and output to the time compression circuit 20. This time compression circuit 20
Compress each color signal R, G, B horizontally to 3/4 and
When displayed on a 6: 9 wide screen, C with the correct aspect ratio
Processing for displaying on RT is performed. The time-compressed color signals R, G, B are supplied to one input terminal of the switch circuit 21.

Also, the MUSE decoder 18 is
The MUSE signal band-compressed to 1 MHz is decoded and converted into R, G, B color signals, and the switch circuit 21
Is output to the other input terminal of. Furthermore, the above NTSC
The decoder 17 and the MUSE decoder 18 take out the horizontal synchronizing signal H and the vertical synchronizing signal V, respectively, from the input baseband signal and output them to one and the other input ends of the switch circuit 22, respectively.

Under the control of the system controller 12, the switch circuit 21 selectively selects the color signals R, G, B obtained by decoding the NTSC signal and the color signals R, G, B obtained by decoding the MUSE signal. To the CRT 23. In addition, the switch circuit 22
Also, under the control of the system controller 12, the switching operation is performed in synchronization with the switch circuit 21.
The horizontal synchronizing signal H and the vertical synchronizing signal V corresponding to the color signals R, G, B derived in 3 are switched to the deflecting circuit 24.

The deflection circuit 24 is controlled by the system controller 12 and operates at a horizontal frequency of 31.5 kHz and a vertical frequency of 59.94 Hz when displaying an NTSC signal on the CRT 23. The horizontal frequency of NTSC is 15.75 kHz, but since the scanning line conversion circuit 19 performs double speed conversion, the frequency of the horizontal synchronizing signal H is also doubled to 31.5 kHz accordingly. The deflection circuit 24, when displaying the MUSE signal on the CRT 23, has a horizontal frequency of 33.75 kHz and a vertical frequency of 60 Hz.
Works with.

The system controller 12 is
Based on the operation command from the remote control operating unit 26 received by the remote control receiving unit 25, the remote control receiving unit 25 is operated to control, for example, a series of tuning operations.

However, in the conventional television receiver as described above, a screen display is performed from the tuners 13 and 16 to which the received television signal is first inputted.
The deflection circuit 24 has an integrated structure up to RT23.
Are configured to operate with two types of synchronization signals.
That is, the signal processing unit that processes the received television signal and the display unit that displays the signal processed by the signal processing unit on the screen completely correspond to each other, that is, the signal processing unit is The configuration is designed so as to correspond only to a display unit having a certain fixed sync frequency and aspect ratio.

Generally, the horizontal synchronizing frequency for operating the display is not limited to the above-mentioned two types of frequencies, including those for personal computers and work stations. For example, 100 kHz is used for a graphic display. There are also things to overcome. Further, in the past, the received television signal is set to a fixed C
It suffices to design it only by displaying it on the RT, but recently, the image of the television signal is personalized.
It has been used as so-called multimedia processing for displaying on a display of a computer or the like.

Further, in recent years, liquid crystal projectors using liquid crystals have been commercialized, and the aspect ratio thereof is not only 4: 3 or 16: 9 at present, but is similar to that of movie screens due to the increase in high definition of large screens. It is expected that those with an aspect ratio will be put to practical use. On the other hand, as the types of television signals, signals such as NTSC and MUSE signals, which have different synchronization frequencies and different aspect ratios, are expected to increase more and more in the future with the progress of multimedia.

Under these circumstances, a television receiver in the future will have a signal processing section and a display section separated from each other, and the signal processing section will be compatible with various kinds of display sections having different synchronization frequencies and different aspect ratios. What is gained tends to be desired.

[0015]

As described above, in the conventional television receiver, the signal processing unit for processing the received television signal is compatible only with the display unit having the defined synchronizing frequency and aspect ratio. Therefore, there is a problem in that it cannot be applied to various kinds of display units having different synchronization frequencies and aspect ratios.

Therefore, the present invention has been made in consideration of the above circumstances, and it is possible to process television signals of various systems, respectively, and make it possible to display on various types of display units having different synchronization frequencies and aspect ratios. An object is to provide a good display device.

[0017]

A display device according to the present invention comprises a discriminating means for discriminating a synchronizing frequency and an aspect ratio of an inputted television signal, a synchronizing frequency of a display for displaying an image of the television signal, and An input means for taking in the aspect ratio, and a horizontal and vertical direction of the television signal based on the discrimination result of the discriminating means and the data captured by the input means in order to display the image of the television signal on the display without impairing the aspect ratio. Calculating means for calculating the decimating rate and interpolation rate in the direction, decimating means for decimating the television signal based on the decimating rate calculated by the computing means, and television based on the interpolating rate calculated by the computing means. Interpolation means to interpolate the television signal and the television signal to the display sync frequency. And a time conversion means for converting the time axis so as to respond, which is constituted of the front and decimation means and the interpolation means to the subsequent time conversion means to place each.

[0018]

According to the above construction, the system of the inputted television signal is discriminated and the signal processing is performed in a form corresponding to the synchronizing frequency and the aspect ratio of the display. It is possible to display the signal on various types of display units having different synchronization frequencies and aspect ratios without impairing the aspect ratio.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings. In FIG. 1, UHF / VHF
Each television signal of the / CATV broadcast is transmitted to the antenna 27.
Is received, is tuned by the tuner 28, converted into a baseband signal, and then supplied to one input end of the switch circuit 29. In this tuner 28, a control signal output from a CPU (central processing unit) 30a in the system controller 30 is transmitted to the data bus 31 and I / O.
It is controlled by being supplied through the (input / output) control circuit 32. The tuner 28 is a standard NTS
It has a function of receiving and processing the C signal and the EDTV signal.

The television signal of the BS broadcast is received by the antenna 33, selected by the tuner 34 and converted into a baseband signal, and then the switch circuit 29.
Is supplied to the other input terminal of the. Also in this tuner 34, the control signal output from the CPU 30a in the system controller 30 is the data bus 31 and the I / O control circuit 32.
It is controlled by being supplied via. The tuner 34 has a function of receiving and processing MUSE signals of high-definition broadcasting in addition to ordinary NTSC signals and EDTV signals.

The switch circuit 29 outputs the baseband signals output from the tuners 28 and 34 to N
It is operated so as to be distributed to the TSC decoder 35 and the MUSE decoder 36 and supplied. This switch circuit 29
Is performed by the CPU 30a in the system controller 30.
The control signal output from the data bus 31 and the I / O
It is controlled by being supplied through the control circuit 37. Of these, the NTSC decoder 35 converts the input baseband signal into each color signal of R, G, B and supplies it to one input end of the switch circuit 38.

The MUSE decoder 36 is 8.
The MUSE signal band-compressed to 1 MHz is decoded and converted into R, G, B color signals, and the switch circuit 38
Is output to the other input terminal of. Furthermore, the above NTSC
The decoder 35 and the MUSE decoder 36 take out the horizontal synchronizing signal H, the vertical synchronizing signal V, and the pixel-based clock signal CK from the input baseband signal, respectively.
It outputs to one and the other input ends of the switch circuit 39.

The switch circuit 38 is supplied with the control signal output from the CPU 30a in the system controller 30 via the data bus 31 and the I / O control circuit 37 to decode the NTSC signal. The signals R, G, B and the color signals R, G, B obtained by decoding the MUSE signal are selectively switched and switched to the decimation / time conversion / interpolation processing unit 41 in the display control unit 40. Be operated.

Also, the switch circuit 39 is synchronized with the switch circuit 38 by the control signal output from the CPU 30a in the system controller 30 being supplied via the data bus 31 and the I / O control circuit 37. The switching operation is performed, and the horizontal synchronization signal H, the vertical synchronization signal V, and the clock signal CK corresponding to the color signals R, G, and B derived to the display control unit 40 are thinned out / time-converted in the display control unit 40. The switching operation is performed so as to lead to the interpolation processing unit 41.

Here, the thinning / time conversion / interpolation processing unit 4
The main operation 1 is to perform thinning or interpolation processing on the input color signals R, G, B according to a connected display (not shown) so that the color signals R, G, B are displayed on the display. Therefore, the color signals R, G, and B after the thinning-out and the interpolation processing are supplied to the display together with the respective synchronization signals SYNC generated by the display synchronization generating unit 42 in correspondence with the horizontal synchronization frequency and the vertical synchronization frequency of the display. To be done.

That is, the display synchronization generating section 42 can freely generate a frequency that matches the horizontal synchronization frequency and the vertical synchronization frequency of the connected display.
Horizontal and vertical dividing value b _H for obtaining a horizontal and vertical synchronizing frequencies to be generated in the display synchronizing generator 42, c _V
Is given from the CPU 30a through the data bus 31 and the I / O control circuit 43. In addition, the display synchronization generator 42 is connected to the data bus 31 and the I / O from the CPU 30a.
The clock frequency division value a _ck and the V area and the H area are set via the control circuit 43. The clock division value a _ck is
The frequency division value for generating the basic clock frequency of the synchronization signal for driving the display is shown, and the V area and the H area are information designating the display position of the display.

The display synchronization generation section 42 outputs various synchronization signals SYNC for driving the display, and the thinning / time conversion / interpolation processing section 41.
A clock CK ', a horizontal pulse H', and a vertical pulse V'for controlling the pulse are output. In addition, the above thinning
The time conversion / interpolation processing unit 41 is given a thinning rate and an interpolation rate from the CPU 30a via the data bus 31 and the I / O control circuit 43.

Further, the baseband signals output from the tuners 28 and 34 are supplied to the system discriminating circuit 44 to discriminate the type of signal, that is, NTSC or MUSE. The result determined by the system determination circuit 44 is written to the system memory 30b in the system controller 30 via the I / O control circuit 45 and the data bus 31. Further, in the system controller 30, the CPU 30
Program ROM storing the program to be given to a.
A (read only memory) 30c, a calculation RAM (random access memory) 30d used in the calculation of the CPU 30a, and a memory 30e for recording the horizontal frequency f _H , vertical frequency f _V, aspect ratio, etc. of the display.
And an I / O control circuit 30f for allowing the CPU 30a to take in data such as the horizontal frequency f _{H of the} display, the vertical frequency f _V, and the aspect ratio set by operating the keyboard 46.

Here, the operation of the display control section 40 can be roughly divided into two functions of thinning out signals and interpolating signals according to the display. First, the case of thinning processing will be described. This case corresponds to a case where a MUSE signal is displayed on the monitor of a normal television receiver, for example, as shown in FIG. That is, the horizontal frequency of the connected display (15.75 kHz
z), vertical frequency (59.94 Hz), aspect ratio (4: 3), and other various data are displayed on the keyboard 46.
CP via I / O control circuit 30f and data bus 31
It is input to U30a.

Then, the CPU 30a calculates the thinning rate when the decoded MUSE signal is displayed on the display. In order to display on a display with an aspect ratio of 4: 3 without impairing the aspect ratio, the thinning rate of 7/20 in the vertical direction is sufficient.
Outputs the thinning rate to the thinning / time conversion / interpolation processing unit 41 via the data bus 31 and the I / O control circuit 43.

FIG. 3 shows a detailed configuration of the thinning / time conversion / interpolation processing unit 41. That is, terminal 4
Color signals R, G, B derived from the switch circuits 38, 39, a horizontal synchronizing signal H, a vertical synchronizing signal V, and a clock signal CK are supplied to 7, 48, respectively. Also,
The thinning rate and the interpolation rate output from the I / O control circuit 43 are supplied to the terminals 49 and 50, respectively. further,
A clock CK ′, a horizontal pulse H ′, and a vertical pulse V ′ output from the display synchronization generator 42 are supplied to the terminals 51, 52, and 53, respectively.

The vertical decimation ratio of 7/20 output from the I / O control circuit 43 is equal to the terminal 49 and the I / O.
It is read by the CPU 55 via the control circuit 54, and as shown in FIG. 4, the tap coefficient of each line in the vertical direction is calculated. The method of thinning out 20 lines in the vertical direction into 7 lines is executed by a combination of a method of thinning out 10 lines into 3 lines and a method of thinning out 10 lines into 4 lines.

That is, the CPU 55 calculates the tap coefficient of each line, and then executes the thinning-out calculation process at the timing shown in FIG. That is, in FIG. 5, the CPU 55
Performs an operation of l ₁ × 1 in the period 1, writes the operation result l ₁ ′ into _one of the field memories 56 and 57 for time axis conversion, and in the period 2, (l ₄ × 0.7) +
The calculation of (l ₅ × 0.3) is performed, and the calculation result l ₂
′ Is written in either one of the field memories 56 and 57. Thereafter, the same calculation process is repeated in the periods 3, 4, 5, ...
It is written in either one of 6 and 57.

FIG. 6 shows the calculation timing of the CPU 55 in pixel units. Since the received signal is a MUSE signal,
The pixel rate is 20 nsec, and the calculation is performed during the period T of the control signal a shown in FIG. The control signal a is generated by the control signal generation circuit 59 based on the address signal generated by the fetch address generation circuit 58, and controls the buffers 60 and 61 so that the data bus and the address bus of the CPU 55 are separated from each other. I try not to hit them. That is, data is written in the thinning memory 62 during the L level period of the control signal a, and the CPU 55 can access the thinning memory 62 during the other periods.

Next, the field memory 5 for time axis conversion
Writing and reading of data with respect to 6 and 57 will be described with reference to FIG. That is, when writing data to the field memory 56, the data in the field memory 57 is read out, and when writing data in the field memory 57, the data in the field memory 56 is read out. This control is performed by the control signals b and c.
This is performed by controlling the buffers 63 to 70 connected to the address buses and data buses of the field memories 56 and 57. These control signals b and c are generated from the control signal generation circuit 71. Of the read addresses, the horizontal address is generated by the horizontal counter 72, and the vertical address is generated by the CPU 55.
Data via the I / O control circuit 73 and the horizontal counter 72
It is generated by adding the output and the output of the.

In this case, since the thinning processing is performed,
The data read from the field memories 56 and 57 is output without being interpolated. That is, the data read from the field memories 56 and 57 is
Line memory 75, switch circuit 76 and latch circuit 7
After passing through 7, the multiplier 78 multiplies the coefficient by 1. Then, the signal is converted into an analog color signal by the D / A (digital / analog) conversion circuit 80 through the addition circuit 79 and is output to a display (not shown) via the output terminal 81. It is displayed on the screen without sacrificing the aspect ratio of the base. The multipliers 82, 83, 8
No. 4 has a tap coefficient of 0 so that no output is produced.

FIGS. 8A and 8B show the line memory 75.
5 shows the timing of writing and reading data to and from. Further, FIG. 9 shows the number of lines per 1 V (1 field) at the time of reading. FIG. 2 shows the number of lines per frame, and the aspect ratio is 4: 3.
The display will have 393 lines. That is, in the field unit, the numbers of lines of 196 lines and 197 lines alternate.

Next, the interpolation process will be described. As for future displays, large screens and higher resolutions are becoming more and more advanced, and one of the cases is shown in FIG. The display has a horizontal frequency of 135 kHz,
The field frequency is 60 Hz and the aspect ratio is 8: 3. This specification is input by the keyboard 46 and I /
The interpolation rate is calculated by being taken into the CPU 30a via the O control circuit 30f. Then, the horizontal interpolation rate (4 times) and the vertical interpolation rate (2 times) calculated by the CPU 30a are taken into the CPU 55 via the terminal 50 and the I / O control circuit 54. The horizontal interpolation rate (4 times) is the horizontal frequency of the MUSE signal 33.75 kHz.
Horizontal frequency of display is 135kHz for z
Since it is four times as large as the MUSE signal, it is calculated on the assumption that the horizontal pixels also have four times the display capability.

FIG. 11 shows horizontal interpolation processing. m ₁ , m ₂ , m ₃ , m ₄ , ... Are pixel data of the received signal, respectively, m ₁₀ ′, m ₁₁ ′, m ₁₂ ′, m ₁₃
′, M ₂₀ ′, m ₂₁ ′, m ₂₂ ′, m ₂₃ ′, m ₃₀ ′, ……
Is the interpolated data to be displayed on the display. Further, FIG. 12 shows the interpolation processing in the vertical direction. l ₁ , l ₂ , l ₃ , l ₄ , l ₅ , l ₆ , l ₇ , ...
Are data in the line direction of the received signal, respectively, and l
₁₀ ', l ₁₁ ', l ₂₀ ', l ₂₁ ', l ₃₀ ', l ₃₁ ', l ₄₀
′, L ₄₁ ′, l ₅₀ ′, l ₅₁ ′, l ₆₀ ′, l ₆₁ ′, l
₇₀ ', ... are the data after interpolation for displaying on the display.

Since there is no thinning in this interpolation processing, the writing of signals into the field memories 56 and 57 is performed in the form shown in FIG. The timing of writing is as described in the thinning process. FIG. 14 shows the timing of the interpolation calculation. In FIG. 14, 1 is a non-display period, data l ₁ is set in the line memory 75 during this period, and data l ₁₀ ′ is calculated and output during the period 2. Further, the data l ₂ is set in the line memory 85 in the period 3 and the interpolation calculation is performed in the period 4 to obtain the data l ₁₁ ′.
Is output. CP of line memories 75 and 85
It is performed from U55 via the I / O control circuit 86.

FIG. 15 shows the timing of the interpolation calculation output, and FIG. 16 shows the coefficient contents of the coefficient registers 87, 88, 89, 90. This coefficient is specified by the CPU 55
Is performed via the I / O control circuit 91. This FIG.
Shows a case where data l ₁₁ ′ is generated using the data l ₁ and l ₂ shown in FIG. That is, the line memory 75 stores data l ₁ (l ₁ m in pixel units).
₁ , l ₁ m ₂ , l ₁ m ₃ ) are included. Further, the line memory 85 contains data l ₂ (expressed as l ₂ m ₁ , l ₂ m ₂ , l ₂ m _{3 in} pixel units).

Then, in the period of the calculation 1, the multiplier 82 performs the operation of l ₁ m ₁ × 0.5 and the multiplier 83
Performs the calculation of l ₂ m ₁ × 0.5. At this time, the multipliers 74 and 84 perform multiplication by a coefficient of 0, so that the output is 0. The outputs of the multipliers 78, 82 to 84 are added by the adder circuit 79, and the data l _{11 ′} m ₁₀ is added.
It is output as'. FIG. 17 shows how the multipliers 78, 82 to 84 perform the calculations during each period of the calculations 1 to 4.

The I / O control circuit 86 controls the switch circuit 76. In the case of this example, the switch circuit 76 is switched and controlled so that the output of the line memory 75 is supplied to the latch 77 and the output of the line memory 85 is supplied to the latch 92.

The specific examples of the thinning-out process and the interpolation process have been described above. Next, the generation of the synchronization signal SYNC corresponding to the display will be described. FIG. 18 shows a detailed configuration of the display synchronization generating section 42 in the display control section 40. That is, the terminals 93, 94 and 95 are supplied with the clock division value a _ck and the H area and V area, respectively, and the terminals 96 and 97 are supplied with the horizontal and vertical division values b _H and c _V , respectively. Each is supplied.

Here, in the case of thinning processing, 163 frequency division is specified as the clock frequency division value a _ck supplied to the terminal 93, and 2332.8 MH output from the oscillator 98.
A value obtained by counting the clock of z by the frequency dividing counter 99 is compared by the comparator 100, and when the count value of the frequency _dividing counter 99 matches the clock frequency _dividing value a _ck , the frequency _dividing counter 99 is reset. By
The clock C of 14.3 MHz from the frequency division counter 99
K'is obtained. This clock CK 'is supplied to the terminal 51
It is supplied to the control signal generating circuit 71 and the horizontal counter 72 via the, and is also supplied to the frequency dividing counter 101 for counting.

Further, the horizontal frequency division value b supplied to the terminal 96
_H is the count value of the frequency division counter 101 and the comparator 102.
Are compared, and the operation of resetting the frequency dividing counter 101 when the count value of the frequency dividing counter 101 matches the horizontal frequency dividing value b _H is repeated, so that the horizontal frequency dividing value b _H specifies 910 frequency division, for example. If it does, the frequency division counter 101 can obtain an H synchronization signal of 15.7 kHz. The H synchronization signal is supplied to the frequency dividing counter 103 and counted, and is also supplied to the adder 104.

[0047] Then, the vertical dividing value c _V supplied to the terminal 97, the comparator 10 and the count value of the dividing counter 103
5 and the operation of resetting the frequency dividing counter 103 when the count value of the frequency dividing counter 103 matches the vertical frequency dividing value c _V is repeated, so that, for example, the vertical frequency dividing value c _V is divided by 525. If specified, the frequency division counter 103 can obtain a 60 Hz V sync signal. The V sync signal is added to the H sync signal by the adder 104 to become a sync signal SYNC, which is sent to the display through the output terminal 106.

The count value of the frequency dividing counter 101 and the horizontal display area (H area) supplied to the terminal 94 are supplied to the horizontal display area generating circuit 107. The display area generation circuit 107 compares the set H area with a count value and outputs the horizontal pulse H.
′ Is generated, and the control signal generating circuit 7 is generated via the output terminal 52.
1 and the horizontal counter 72. Further, the count value of the frequency division counter 103 and the vertical display area (V area) supplied to the terminal 95 are supplied to the vertical display area generation circuit 108. The display area generation circuit 108 compares the set V area with a count value to generate the vertical pulse V ′, and outputs the output terminal 53.
It is output to the control signal generation circuit 71 and the CPU 55 via.

Here, in the case of the interpolation process, the clock frequency division value a _ck is set to 2 and the horizontal frequency division value b _H is set to 8640 and the vertical frequency division value c _V is set to 225.
When 0 division is designated, a clock CK 'of 1166.4 MHz, an H synchronization signal of 135 kHz, and a V synchronization signal of 60 Hz are obtained.

Next, FIG. 19 shows an operation flowchart of the CPU 55. This flow chart is mainly arranged by the CPU 55 of the above-described thinning-out processing and interpolation processing. First, when the power is turned on (step S1), the CPU 55 sends the vertical synchronization signal V via the I / O control circuit 109 in step S2.
To detect. After that, the CPU 55, in step S3,
The thinning rate and the interpolation rate are read via the I / O control circuit 54. In the above embodiment, in the case of thinning, 7
In the case of interpolation, data of / 20 is read, and in the case of interpolation, data of 4 times horizontal and 2 times vertical is read.

Next, the CPU 55 calculates the thinning coefficient and the interpolation coefficient in step S4.
This is performed in the vertical blanking period from the detection of the vertical synchronizing signal V to the start of the television signal. 4 and 11,
FIG. 12 shows the coefficient for each line. And CP
In step S5, the U55 detects the horizontal synchronizing signal H in the video period via the I / O control circuit 109. When the horizontal synchronizing signal H is detected, the CPU 55 proceeds to step S6.
By detecting the control signal a via the I / O control circuit 109, the pixels to be processed are detected for each line.

When the control signal a is detected, the CPU 55
In step S7, the thinning operation is executed at the timing shown in FIG. When the thinning operation is completed, C
The PU 55 transfers the calculation result to the field memories 56 and 57 in step S8. Thereafter, the CPU 55 determines in step S9 whether or not the data transfer for one line is completed, and if not completed (NO), the step S9.
Returned to the processing of 6. If the processing has been completed (YES), the CPU 55 determines in step S10 whether the processing for the number of lines for one field has been completed, and if not completed (NO), the processing returns to the processing in step S5. If completed (YES), the process returns to step S2.

The CPU 55 executes a thinning process in the main routine until the data is input to the field memories 56 and 57, and interrupts the data set for performing the interpolation process after reading the data from the field memories 56 and 57. The feature is that it is performed by processing. The CPU 55 designates the line memory for the interpolation calculation and sets the tap coefficient data in the coefficient register, and the timing detection thereof is realized by the V ′ synchronous interrupt processing and the H ′ synchronous interrupt processing.

FIG. 20 is a flow chart showing the V'synchronous interrupt processing, and interrupt start (step S11).
Then, the CPU 55 clears a line counter register (not shown) installed therein in step S12, and then returns to the original flowchart in step S13.

FIG. 21 is a flow chart showing the H'synchronous interrupt processing, and interrupt start (step S14).
Then, the CPU 55 sets the line address to be processed in the I / O control circuit 73 by referring to the value of the line counter register in step S15. This set address becomes the write address of the field memories 56 and 57.

Next, the CPU 55, in step S16,
The line memories 75, 85, 110 for writing the data read from the field memories 56, 57 are designated via the I / O control circuit 86. After that, the CPU 55
In step S17, coefficient data is set in the coefficient registers 87 to 90 via the I / O control circuit 91. Then, the CPU 55 increments the line counter register by 1 in step S18, and then returns to the original flowchart in step S19. The above interpolation operation is executed every time the H'synchronization interrupt arrives, and the interpolation processing for one field is finally performed.

Next, FIG. 22 shows the system controller 3
The operation | movement flowchart of CPU30a in 0 is shown. The main function of the CPU 30a is to determine the broadcasting system being selected, take in the specifications (horizontal frequency, vertical frequency, aspect ratio) of the connected display, and calculate the thinning rate and interpolation rate. Is. The operation flow chart shown in FIG. 22 shows a case where the keyboard 46 is used to specify a channel and a display is specified, and is based on interrupt processing.

First, the CPU 30a executes step S20.
Then, the tuners 28 and 34 are selected via the I / O control circuit 32. Next, the CPU 30a, in step S21,
The system discrimination result of the television signal output from the selected tuner 28, 34 is fetched via the I / O control circuit 45. After that, the CPU 30a proceeds to step S22.
Then, the fetched method discrimination result is set in the method memory 30b. Next, in step S23, the CPU 30a inputs / outputs the display specifications input by the keyboard 46 to the I / O.
Captured via the control circuit 30f. And the CPU 30
In step S24, a writes the specifications of the display taken in in the memory 30e.

Thereafter, the CPU 30a causes the step S25.
Then, the thinning rate and the interpolation rate are calculated based on the format data recorded in the format memory 30b and the display specifications recorded in the memory 30e and output to the display control unit 40, and in step S26, the clock frequency division value a _ck is calculated. , Horizontal frequency division value b _H , vertical frequency division value c _V , H area and V area are output to the display control unit 40.

FIG. 23 shows an example of thinning rate calculation. First, in step S27, the CPU 30a calculates the number of lines of the display from the horizontal frequency and the vertical frequency in the specifications of the display input from the keyboard 46. In this example, the horizontal frequency (15750H
z) × 2 / vertical frequency (59.94 Hz) = 525 lines are obtained. Next, the CPU 30a causes the step S28.
Then, the compression ratio of the received signal is obtained from the aspect ratio of the signal and the aspect ratio of the display. In this example, 9 /
(16 × 3/4) = 3/4, so 3/4 in the vertical direction.
It should be doubled.

After that, the CPU 30a carries out step S29.
Then, find the number of lines actually displayed. Where 16: 9
When the television signal of is displayed at 4: 3, the number of lines in the vertical direction is 3/4 of 525, that is, 393.
Then, the CPU 30a calculates the thinning rate of the number of lines in step S30. In this example, 393/1125
Is about 7/20, and the value is sent to the display control unit 40 as a thinning rate.

Therefore, according to the configuration of the above embodiment, a plurality of television signals such as NTSC signals and MUSE signals are matched with the specifications (horizontal frequency, vertical frequency, aspect ratio) of the connected display. Since the signal processing (decimation, time axis conversion, interpolation) is performed in, it is possible to display television signals of various systems on various types of display units having different synchronization frequencies and aspect ratios. Further, in the above embodiment, the tuner 2
Although it has been described that the baseband signals obtained from 8 and 34 are thinned out, time-axis converted, and interpolated, the baseband signal directly input from the outside can be processed. Further, the means for inputting the specifications of the display is not limited to the keyboard 46, but may be realized by using a remote control operation, for example. The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention.

[0063]

As described above in detail, according to the present invention,
It is possible to provide a very good display device that can process television signals of various systems and can display on various types of display units having different synchronization frequencies and aspect ratios.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing an embodiment of a display device according to the present invention.

FIG. 2 is a diagram for explaining the relationship between screens in the thinning process of the embodiment.

FIG. 3 is a block configuration diagram showing details of a decimation / time conversion / interpolation processing unit in the embodiment.

FIG. 4 is a diagram for explaining a thinning process of the embodiment.

FIG. 5 is a view showing a thinning-out calculation timing in the embodiment.

FIG. 6 is a diagram showing a calculation timing of a CPU in the same thinning-out calculation.

FIG. 7 is a diagram showing write and read timings of the time axis conversion memory of the embodiment.

FIG. 8 is a diagram showing write and read timings of the line memory of the embodiment.

FIG. 9 is a diagram for explaining the number of lines at the time of reading from the same line memory.

FIG. 10 is a diagram for explaining the relationship between screens in the interpolation processing of the embodiment.

FIG. 11 is a diagram for explaining horizontal interpolation processing of the same embodiment.

FIG. 12 is a diagram for explaining vertical interpolation processing according to the embodiment.

FIG. 13 is a diagram showing write and read timings of the time axis conversion memory of the embodiment.

FIG. 14 is a diagram for explaining an interpolation calculation processing period of the embodiment.

FIG. 15 is a diagram showing the interpolation calculation output timing of the embodiment.

FIG. 16 is a diagram showing the content of coefficients in the embodiment.

FIG. 17 is a diagram showing the contents of calculation in the interpolation processing of the embodiment.

FIG. 18 is a block configuration diagram showing details of a display synchronization generating unit of the embodiment.

FIG. 19 is a flowchart showing the operation of the CPU in the display control unit of the embodiment.

FIG. 20 is a flowchart showing V ′ synchronous interrupt processing of the same CPU.

FIG. 21 is a flowchart showing H ′ synchronous interrupt processing of the same CPU.

FIG. 22 is a CPU in the system controller of the embodiment.
6 is a flowchart showing the operation of the above.

FIG. 23 is a flowchart showing thinning processing of the CPU.

FIG. 24 is a block diagram showing a conventional television receiver.

[Explanation of symbols]

11 ... Antenna, 12 ... System controller, 13 ...
Tuner, 14 ... Switch circuit, 15 ... Antenna, 16
… Tuner, 17… NTSC decoder, 18… NUSE
Decoder, 19 ... Scan line conversion circuit, 20 ... Time compression circuit, 21, 22 ... Switch circuit, 23 ... CRT, 24 ...
Deflection circuit, 25 ... Remote control receiver, 26 ...
Remote control operation part, 27 ... Antenna, 28 ...
Tuner, 29 ... Switch circuit, 30 ... System controller, 31 ... Data bus, 32 ... I / O control circuit, 3
3 ... Antenna, 34 ... Tuner, 35 ... NTSC decoder, 36 ... MUSE decoder, 37 ... I / O control circuit,
38, 39 ... Switch circuit, 40 ... Display control unit, 41 ...
Thinning-out / time-changing / interpolation processing unit, 42 ... Display synchronization generating unit, 43 ... I / O control circuit, 44 ... Method determination circuit, 45
... I / O control circuit, 46 ... Keyboard, 47 to 53 ... Terminal, 54 ... I / O control circuit, 55 ... CPU, 56, 57
... field memory, 58 ... fetch address generating circuit, 59 ... control signal generating circuit, 60, 61 ... buffer,
62 ... Thinning memory, 63-70 ... Buffer, 71 ...
Control signal generation circuit, 72 ... Horizontal counter, 73 ... I / O
Control circuit, 74 ... Adder, 75 ... Line memory, 76 ...
Switch circuit, 77 ... Latch, 78 ... Multiplier, 79 ... Adder circuit, 80 ... D / A conversion circuit, 81 ... Output terminal, 82
-84 ... Multiplier, 85 ... Line memory, 86 ... I / O control circuit, 87-90 ... Coefficient register, 91 ... I / O control circuit, 92 ... Latch, 93-97 ... Terminal, 98 ... Oscillator, 99 ... Frequency division counter, 100 ... Comparator, 101 ...
Frequency division counter, 102 ... Comparator, 103 ... Frequency division counter, 104 ... Adder, 105 ... Comparator, 106 ... Output terminals, 107, 108 ... Display area generation circuit, 109 ... I
/ O control circuit, 110 ... Line memory.

Claims (1)

[Claims] 1. A discriminating means for discriminating a synchronizing frequency and an aspect ratio of an inputted television signal, an inputting means for fetching a synchronizing frequency and an aspect ratio of a display for displaying the television signal as an image, and the television. In order to display a signal on the display without impairing the aspect ratio of the signal, the horizontal and vertical thinning rate and interpolation of the television signal are performed based on the determination result of the determination means and the data captured by the input means. A calculating means for calculating the ratio, a thinning means for thinning the television signal based on the thinning ratio calculated by the calculating means, and a television signal for the television signal based on the interpolation ratio calculated by the calculating means. An interpolating means for performing an interpolating process, and a synchronization frequency of the display for the television signal. And a time converting means for converting the time axis so as to correspond to the above, and the thinning means and the interpolating means are arranged before and after the time converting means, respectively.