JP2004040731A - Video signal processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reproduce a recording medium without interrupting television video and to display high-definition video without beat interference caused by the higher harmonic wave components of a system clock coming into a tuning demodulation circuit. <P>SOLUTION: The video signal processing apparatus is provided with: a timing generating circuit 22 for detecting a synchronizing signal in the output video signal of a tuning demodulation circuit 2 to set a period except an effective video period corresponding to a blanking period; a reproducing circuit (video data reproducing circuit 26) for performing reproducing from the recording medium (IC card 23) only during the period except the effective video period set by the timing generating circuit 22; a memory circuit (image memory circuit 27) for coupling and temporarily storing information intermittently reproduced by the reproducing circuit; and a superimposing circuit (scaling circuit 11) for superimposing the information in the memory circuit on the output video signal of the tuning demodulation circuit 2. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a video signal processing device in a television receiver or the like equipped with a display device such as a liquid crystal display, and more particularly to a television device that suppresses beat interference caused by harmonics accompanying a display device and a system clock of video signal processing. The present invention relates to a video signal processing device capable of improving the video quality when displaying a John broadcast.
[0002]
[Prior art]
Conventionally, there has been a liquid crystal television receiver as a television receiver using a liquid crystal display as a display device. There is also a liquid crystal television receiver which has an IC card slot and is provided with a function of reproducing a still image for an IC card recorded using a standard such as JPEG.
[0003]
A conventional liquid crystal television receiver to which an IC card reproducing function is added will be described with reference to FIG.
As shown in FIG. 7, a conventional liquid crystal television receiver 31 includes a liquid crystal display unit 32. In order to display a television broadcast, a channel selection demodulation circuit 33 and a clock generation circuit 34 are added. A card slot 50 and a video data reproducing circuit 51 are added to display a reproduced video of the card.
[0004]
The liquid crystal display unit 32 includes, for example, a DA conversion circuit 36 for converting an RGB signal given as digital data into an analog signal for a liquid crystal display 35 of 680 × 480 pixels, a horizontal start pulse, a vertical start pulse, and a shift. A liquid crystal drive circuit 37 for two-dimensionally scanning the liquid crystal display 35 in response to a clock is integrated.
[0005]
The channel selection demodulation circuit 33 tunes and demodulates the television broadcast captured by the reception antenna 38 in response to a channel selection command given to the CPU 39 via a touch key or a remote controller, and is a general CRT television receiver. And outputs the composite video signal divided into an RGB signal and horizontal and vertical synchronization signals HSY and VSY.
[0006]
The video data reproducing circuit 51 reads out data from an IC card inserted into the card slot 50 in response to a card reproducing command given to the CPU 39 via a touch key or a remote controller, and performs a predetermined operation using data compression means such as JPEG. And reproduces the data from the H.264 format, and outputs horizontal and vertical synchronization signals HSY and VSY.
The output signal of the video data reproduction circuit 51 decoded into the Y, Cb, and Cr component signals is converted into an analog RGB signal by an RGB conversion circuit 52 and a DA conversion circuit 53.
[0007]
Driving the liquid crystal display 35 requires a circuit that does not exist in a general CRT television receiver. For example, as a circuit specific to the liquid crystal television receiver 31, from interlaced scanning in which one screen is composed of two screens of one field consisting of 262.5 scanning lines, one screen is composed of 525 scanning lines. There are a scan conversion circuit 40 for converting into a sequential scan to be constituted, a clock generation circuit 34 for supplying various pulses and clocks for designating a drive timing for each pixel constituting a dot matrix, and the like.
[0008]
The scan conversion circuit 40 scans by sending the output of the AD conversion circuit 41 for converting the RGB signals output from the switch circuit 55 into digital data to a built-in line memory and reading the output at twice the writing speed. The linear density is double-density-converted, and the interlaced signal is converted into a non-interlaced signal. The RGB signals converted to non-interlaced signals are sent to a DA conversion circuit 36 in the liquid crystal display unit 32 and converted to analog signals, and then supplied to pixels designated by the liquid crystal drive circuit 37 in a dot-sequential manner.
[0009]
The clock generation circuit 34 multiplies the horizontal synchronizing signal HSY (frequency fh) sent from the channel selection demodulation circuit 33 by 2N by a phase locked loop (hereinafter, referred to as PLL) 42 and converts the system clock of frequency 2fs (= 2Nfh). Then, a horizontal start pulse, a vertical start pulse, or a shift clock is generated according to the system clock.
[0010]
As is widely known, the PLL 42 constitutes a single loop with a phase comparator 43, a low-pass filtering circuit 44, a voltage-controlled oscillator 45, and a frequency dividing circuit 46 for performing 1 / 2N frequency dividing. The voltage-controlled oscillator 45 obtains a system clock having a frequency of 2 fs before being frequency-divided by ＮN by the frequency dividing circuit, and a clock having a frequency fs of そ の.
[0011]
The clock of the frequency fs is used as the operation clock of the AD conversion circuit 41 and the write clock of the scan conversion circuit 40, and the system clock of the frequency 2fs is the read clock of the scan conversion circuit 40, the operation clock of the DA conversion circuit 36, and the liquid crystal. Used as a shift clock for the drive circuit 37.
[0012]
As a shift clock for the liquid crystal driving circuit 37, a system clock that has passed through a frequency dividing circuit 46 in the PLL 42 and a decoder 47 connected outside the loop to this is actually used.
[0013]
A horizontal start pulse for determining the number of shift clocks to be driven from the horizontal synchronization signal HSY with respect to the horizontal pixel row of the liquid crystal display 35 is built in the frequency dividing circuit 46 in the PLL 42. The count output of the counter is decoded by the decoder 47, and given by the logic determination of the decoder 47 that the count value of the counter has reached a predetermined constant value.
[0014]
Furthermore, a vertical start pulse for determining the number of shift clocks to be driven from the vertical synchronizing signal VSY with respect to a vertical pixel row of the liquid crystal display 35 is an output of the frequency dividing circuit 46 in the PLL 42. Is counted by a counter in the frequency dividing circuit 48 which is reset by the vertical synchronizing signal VSY, and the decoder 47 logically determines that the count value of the counter has reached a predetermined constant value.
[0015]
By the way, the video data reproduction circuit 51 operates with the output clock of the system clock generation circuit 54 dedicated to card reproduction. Considering the decoding of Y, Cb, and Cr component signals based on ITU-R recommendation BT601 of the video data reproducing circuit 51, the frequency of the card system clock is set to a frequency of 13.5 MHz, which is M / N times. Since the system is simple and advantageous, the frequency is set to 135 MHz here. Therefore, the output signal of the video data reproduction circuit 51 and the operating frequencies of the RGB conversion circuit 52 and the DA conversion circuit 53 are 13.5 MHz.
[0016]
Therefore, in the above-mentioned conventional liquid crystal television receiver to which the IC card reproduction function is added, if the IC card reproduction is performed simultaneously during the reception of the television broadcast, the harmonic generated as an integral multiple of the frequency of the card reproduction system clock is generated. There is a problem that the component jumps into the channel selection demodulation circuit and causes a beat disturbance.
[0017]
As a countermeasure against such a problem, it is conceivable that the television reception and the IC card reproduction are not performed at the same time, and the television reception mode and the IC card reproduction mode are separated. That is, in the television reception mode, the CPU 39 stops the IC card reproducing operation and switches the switch circuit 55 to select the RGB signal output from the channel selection demodulation circuit 33 and the horizontal and vertical synchronization signals HSY and VSY. I do. On the other hand, in the IC card reproduction mode, the CPU 39 stops the channel selection demodulation operation and switches the switch circuit 55 so that the video data reproduction circuit 51 and the RGB signals output from the DA conversion circuit 53 are synchronized with the horizontal and vertical synchronization. Measures such as selecting the signals HSY and VSY have been taken.
[0018]
As another countermeasure, switching the system clock frequency for card reproduction in accordance with the selected channel may be considered. As a method of switching the system clock frequency according to the channel selected, for example, a liquid crystal television receiver described in Japanese Utility Model Laid-Open No. 5-65184 has been proposed. The technique described in Japanese Utility Model Laid-Open No. 5-65184 will be described with reference to FIG.
[0019]
As shown in FIG. 8, a liquid crystal television receiver 61 described in Japanese Utility Model Laid-Open No. 5-65184 switches a multiplication ratio 2N in a PLL in a clock generation circuit in conjunction with a channel to be selected, and controls a harmonic of a system clock. The configuration is such that wave components do not cause beat disturbance, and an image is always displayed in the center of the liquid crystal display 35 even when the system clock is changed.
[0020]
The beat interference suppressing means for suppressing the beat interference includes a multiplication ratio memory 62 storing a multiplication ratio 2N selected for each channel of the television broadcast wave, and a multiplication ratio memory 62 received from the multiplication ratio memory 62 in response to designation of a channel to be selected. Is read, and the CPU 63 is used to read the multiplication ratio 2N and set it in the frequency dividing circuit 46 in the PLL 42.
[0021]
By the way, when selecting the system clock, there is a condition that the overscan distortion rate is suppressed to 5% or less. That is, for the horizontal synchronization frequency 2fh (= 31.46 kHz) subjected to the double density conversion, the video display period corresponding to 680 pixels in the horizontal direction of the liquid crystal display 35 is 26.4 μs. When the effective display period in the horizontal direction is 640 pixels, the overscan rate E represented by the ratio of the effective display period to the video display period is represented by 640 / 26.4 · 2fs, and the overscan distortion The rate is represented by (1-E) / 2. Therefore, in order to suppress the overscan distortion rate to 5% or less, the multiplication ratio, that is, the frequency division ratio 2N of the frequency dividing circuit 46 must be 856 × 2 or less.
[0022]
When the multiplication ratio (division ratio) 2N is 856 × 2 or less, the fourth to thirtieth harmonics of the system clock enter the broadcast wave band. Must select a plurality of system clocks so as not to violate the broadcast wave band. Then, when the overscan distortion rate is 5% or less and any harmonic component of any channel is out of the broadcast wave band, for example, when the multiplication ratios 808 × 2 and 832 × 2 are selected, At a multiplication ratio of 808 × 2, the frequency 2fs of the system clock is 25.42 MHz, so that the second, fifth, 9, 15, 19, 23, 27, 32, 36, 40, 44, 49, 53, 57, 61 Harmonics enter each channel. Further, at the multiplication ratio of 832 × 2, since the frequency 2fs of the system clock is 26.17 MHz, the third, sixth, 10, 13, 17, 21, 26, 30, 35, 39, 43, 48, 52, 56 , 61 enter the harmonics.
[0023]
Therefore, it is possible to avoid beat disturbance by switching the system clock in at least two ways except for the 61st channel where harmonics intrude at any multiplication ratio. For the 61st channel, beat interference can be eliminated by using, for example, a multiplication ratio of 800 × 2.
[0024]
In the multiplication ratio memory 62, three types of multiplication ratios 2N that do not cause beat interference are stored using the selected channel as an address, and when the tuning microcomputer 64 receives a tuning command, the liquid crystal television receiver 61 The CPU 63, which controls the entire system, reads out the multiplication ratio 2N corresponding to the selected channel from the multiplication ratio memory 62, and sets this in the frequency dividing circuit 46 in the PLL. That is, for example, when the third channel is selected, the multiplication ratio of 808 × 2 is selected, and when the second channel is selected, the multiplication ratio of 832 × 2 is selected, and further, the 61st channel is selected. When localized, a multiplication ratio of 800 × 2 is selected.
As described above, by selecting a clock, a system clock in which harmonic components do not jump into the band of the selected channel can be obtained.
[0025]
[Problems to be solved by the invention]
In the above-described liquid crystal television receiver to which the conventional IC card reproduction function is added, a viewer inserts an IC card into the liquid crystal television receiver, and performs reproduction for the purpose of viewing the IC card while receiving a television broadcast. If this is attempted, there is a problem that a harmonic component generated as an integral multiple of the frequency of the system clock for card reproduction jumps into the channel selection demodulation circuit and causes beat interference. In order to avoid the beat interference, the TV reception mode and the IC card playback mode were separately displayed and displayed on the display. It doesn't correspond to watching TV at all.
[0026]
In addition, several harmonics generated accompanying the system clock generated by the PLL are obtained in advance by trial calculation, and a system clock in which these harmonics avoid the 6 MHz occupied band of the television broadcast wave is selected. In the method of suppressing the beat interference caused by the harmonic component of the system clock jumping into the channel selection demodulation circuit, when the viewer changes the channel selection, Also needs to be reselected according to the selected channel.
[0027]
Generally, when the clock frequency changes, it is necessary to change the processing settings of the internal operation of the video data reproduction circuit as well as the RGB conversion circuit and the DA conversion circuit. In other words, if the selected channel is changed during the reproduction of the IC card, the clock frequency of the video data reproduction circuit changes, so that not only the reproduction video of the IC card is disturbed but also the card reproduction operation itself may stop.
Therefore, the method of selecting a clock that does not cause a harmonic component to jump into the band of the selected channel has a problem in that it is not possible to view an IC card while receiving a television broadcast without being disturbed by a beat. I was holding it.
[0028]
The present invention has been proposed in view of the circumstances described above. When an IC card is played back for the purpose of viewing or confirming the recorded content of the IC card while watching a television broadcast, the television image is not interrupted. Provided is a video signal processing device capable of reproducing an IC card and displaying a high-quality video without a beat disturbance caused by a harmonic component of a system clock jumping into a channel selection demodulation circuit. With the goal.
[0029]
[Means for Solving the Problems]
The video signal processing device according to the present invention has the following features in order to achieve the above object.
[0030]
That is, the video signal processing apparatus according to the present invention includes a channel selection demodulation circuit for receiving and broadcasting and demodulating a television broadcast wave, a recording medium on which video information is recorded, and reproducing the video information from the recording medium. A reproduction circuit for, and a video signal processing device comprising a display device for displaying the output video signal of the channel selection demodulation circuit and the reproduction circuit,
A timing generation circuit for detecting a synchronization signal in an output video signal of the channel selection demodulation circuit and setting a period other than an effective video period corresponding to a retrace period,
The playback circuit is controlled to perform playback processing from the recording medium only during a period other than the effective video period set by the timing generation circuit, and combines information intermittently played back by the playback circuit and temporarily And a superimposing circuit for superimposing information of the memory circuit on an output video signal of the channel selection demodulation circuit.
[0031]
Here, the reproducing circuit reproduces additional information relating to video information from the recording medium, and the superimposing circuit converts the additional information as a character and superimposes it on the output video signal of the channel selection demodulation circuit. And
[0032]
Further, the reproduction circuit includes a clock generation circuit that generates a reproduction circuit operation clock only during a period other than the effective video period set by the timing generation circuit, and stops the reproduction operation during periods other than the effective video period. .
[0033]
A detection circuit that detects that the recording medium is mounted,
The reproduction circuit performs a reproduction process from the recording medium immediately after mounting the recording medium.
[0034]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of a video processing device according to the present invention will be described with reference to FIGS.
[0035]
FIG. 1 is a circuit diagram showing an outline of an embodiment of a video signal processing apparatus according to the present invention. FIG. 2 is a signal waveform diagram of each part of the circuit in FIG. 1. FIG. 3 is a signal of each part of a scaling and double-speed conversion circuit in FIG. FIG. 4 is an explanatory diagram showing the relationship between the selected channel and the harmonic interference. FIG. 5 is a signal waveform diagram of the timing generation circuit in FIG. 1 in the horizontal period. FIG. 6 is a signal waveform diagram of the timing generation circuit in FIG. It is a signal waveform diagram.
[0036]
In FIG. 1, 1 is a receiving antenna, 2 is a channel selection demodulation circuit, 3 is a phase locked loop (hereinafter, referred to as PLL) composed of an LPF / sync separation circuit 4, a phase comparison / VCO circuit 5, and a counter 6, 7 Is an AD conversion circuit, 8 is a YC separation circuit, 9 is a color demodulation circuit, 10 is an RGB conversion circuit, 11 is a scaling circuit, 12 is a double speed conversion circuit, 13 is an OSD circuit, 14 and 15 are liquid crystal system clock generation circuits, 16 is a synchronization generation circuit, 17 is a display device composed of a DA conversion circuit 18, a liquid crystal drive circuit 19 and a liquid crystal display 20, 21 is a CPU, 22 is a timing generation circuit, 23 is an IC card, 24 is a card slot, and 25 is a card slot. A card system clock (CCK) generation circuit, 26 is a video data reproduction circuit, 27 is an image memory circuit, and 28 is an RGB conversion circuit.
[0037]
In describing an embodiment of the video processing device according to the present invention, first, an operation of displaying a television broadcast on the display device 17 will be described.
The tuning demodulation circuit 2 tunes and demodulates a television broadcast captured by the receiving antenna 1 in response to a tuning instruction given to the CPU 21 through a touch key or a remote controller, and outputs a composite video signal.
[0038]
The AD conversion circuit 7, the YC separation circuit 8, the color demodulation circuit 9, and the RGB conversion circuit 10 convert the composite video signal output from the channel selection demodulation circuit 2 which is an analog video signal of the NTSC or PAL system into ITU-R recommendation BT601. Is decoded as follows with respect to RGB digital data conforming to.
[0039]
That is, the sampling clock for AD conversion is 13.5 MHz or a multiple thereof and a lower frequency can be used to simplify the system at the subsequent stage in order to comply with ITU-R Recommendation BT601. Is preferably higher, and is 27 MHz here.
[0040]
The PLL 3 generates a 27 MHz sampling clock for the operation of the AD conversion circuit 7 and a 13.5 MHz decode clock for the operations of the YC separation circuit 8, the color demodulation circuit 9 and the RGB conversion circuit. The PLL 3 has a configuration that is widely known, and separates a horizontal synchronizing signal (frequency fh) from a composite image by an LPF / sync separation circuit 4 and uses the horizontal synchronizing signal as a reference to output a phase comparison / VCO circuit 5 and a counter. 6, a 27 MHz sampling clock and 1/2 of the 13.5 MHz decode clock are generated from the counter 6.
[0041]
The composite video signal sampled at 27 MHz by the AD conversion circuit 7 is downsampled to 13.5 MHz by the decimation filter in the YC separation circuit 8, and then separated into a Y signal and a C signal. The C signal is demodulated by a color demodulation circuit 9 into a Cb signal and a Cr signal, and is converted into an RGB signal together with a Y signal by an RGB conversion circuit 10.
[0042]
The RGB signal has the timing shown in FIG. 2A, and data of the effective video period is up-sampled by an interpolation filter in the scaling circuit 11 arranged at the subsequent stage. Further, the line memory in the double speed conversion circuit 12 reads out the data at twice the writing speed, doubles the scanning lines, and converts the interlaced signal into a non-interlaced signal.
[0043]
In the synchronization generation circuit 16, a liquid crystal driving circuit is provided according to a horizontal and vertical reference signal synchronized with the input composite synchronization signal supplied from the counter 6 and a liquid crystal system clock supplied from the liquid crystal system clock generation circuit 14 or 15. A horizontal start pulse, a vertical start pulse, or a shift clock for the operation of step 19 is generated.
[0044]
The RGB signals converted to non-interlaced signals are converted to analog signals by a DA conversion circuit 18 in a display device 17, and then supplied to pixels specified in a dot-sequential manner by a liquid crystal drive circuit 19.
[0045]
By the way, the liquid crystal system clock, which is the operation clock of the display device 17 including the scaling circuit 11, the double-speed conversion circuit 12, and the D / A conversion circuit 18 and the liquid crystal drive circuit 19, has a harmonic component of the clock with respect to the reception channel selected. It is necessary to make a selection so as not to cause a beat disturbance.
[0046]
Hereinafter, a method of suppressing beat disturbance will be described. In order to suppress the beat interference, two liquid crystal system clock generating circuits 14, which generate clocks of two frequencies fs1 and fs2, in which the frequency of the clock harmonic component does not overlap each other in the frequency band of all broadcast channels, 15 is prepared and the CPU 21 storing the system clock selection data for each channel of the television broadcast wave in the built-in memory switches the output of the liquid crystal system clock generation circuits 14 and 15 in response to the designation of the selected channel. I do.
[0047]
The output clock frequencies fs1 and fs2 of the liquid crystal system clock generation circuits 14 and 15 are selected so that the frequencies of the clock harmonic components do not overlap each other in the frequency band of all broadcast channels. The CPU 21 automatically selects a clock that does not cause a beat disturbance to the selected channel, thereby suppressing the beat disturbance.
[0048]
The selection of the liquid crystal system clock frequency depends on the display size of the liquid crystal display 20 and the conversion ratio of the scaling circuit 11 according to the display size. Here, a case will be described in which a 16: 9 wide VGA panel (854 × 480) is used as the liquid crystal display 20 in consideration of high-quality DVD video and the like.
[0049]
As shown in FIG. 2A, the RGB signal has 720 samples of effective video data. Therefore, the number of horizontal samples of the liquid crystal display 20 is increased to 854 by the interpolation filter in the scaling circuit 11. At this time, the horizontal conversion ratio in the scaling circuit 11 is 32/27, and as shown in FIG. 3A, adjacent data is weighted to obtain converted data.
[0050]
In this state, since the signal is still an interlaced signal, it is read out at twice the writing speed by the line memory in the double speed conversion circuit 12, and further, as shown in FIG. By passing through an interpolation filter in the circuit 12, the scanning line is double-speed converted to a non-interlaced signal. Therefore, the number of effective scanning lines is also converted from 240 lines to 480 lines.
By performing such processing, data adapted to a 16: 9 wide VGA panel (854 × 480) is obtained.
[0051]
As for the selection of the liquid crystal system clock frequency, 28.888 MHz was selected as the output clock frequency fs1 of the system clock generation circuit 14, as shown in FIG. Since the number of horizontal scanning lines of the output signal of the double speed conversion circuit 12 is twice the number of horizontal scanning lines of the input composite video signal, the horizontal scanning period Th1 is Th1 = Th / 2 = 31.778 μsec. The number of horizontal scanning lines from 262.5 becomes 525.
[0052]
Here, as for the number of samples in the horizontal scanning period, the number of samples in the effective video period is 854 as described above. Although the setting of the number of samples other than the effective video period depends on the specification of the liquid crystal drive circuit 19, here, the number of samples is 64. As a result, assuming that the vertical frequency is 59.94 Hz, the output clock frequency fs1 of the system clock generation circuit 14 is selected as fs1 = (854 + 64) × 525 × 59.94 = 28.888 MHz.
[0053]
On the other hand, as shown in FIG. 2C, 30.902 MHz was selected as the output clock frequency fs2 of the liquid crystal system clock generation circuit 15. That is, similarly to fs1, fs2 = (854 + 128) × 525 × 59.94 = 30.902 MHz, but the number of samples other than the effective video period is set to 128 here. As shown by the crosses in the LCK1 column in FIG. 4, the harmonics of the clock frequency fs1 are the frequencies of the broadcast channels 4, 9, 16, 21, 26, 30, 35, 40, 45, 50, 55, and 59 channels. It overlaps with the band.
[0054]
On the other hand, the harmonics of the clock frequency fs2 of 30.902 MHz are shown in the LCK2 column in FIG. , 53 and 58 channels.
[0055]
In FIG. 4, a comparison between the crosses in the LCK1 column and the crosses in the LCK2 column indicates that there are no overlapping channels. Here, two frequencies of 28.888 MHz and 30.902 MHz are selected, but many other combinations are conceivable depending on the setting of the number of samples other than the effective video period and the display size of the liquid crystal display. That is, as described above, other combinations can be adopted as long as there are no channels where the harmonics overlap each other.
[0056]
As described above, several harmonics generated accompanying the liquid crystal system clock are obtained in advance by trial calculation, and a plurality of system clocks in which these harmonics do not overlap in the 6 MHz frequency band of each channel of the television broadcast wave. Is selected so as to be selected in accordance with the selected broadcasting channel. Therefore, the operation clock of the display device 17 including the scaling circuit 11, the double-speed conversion circuit 12, and the DA conversion circuit 18 and the liquid crystal drive circuit 19 is used. It is possible to suppress beat disturbance caused by a harmonic component of a certain liquid crystal system clock jumping into the channel selection demodulation circuit 2.
[0057]
Next, an operation for displaying the reproduction signal of the IC card on the display device 17 will be described.
[0058]
When the CPU 21 receives a card reproduction instruction (for example, an instruction to reproduce a certain still image) through the touch key or the remote controller, and recognizes that the IC card 23 is inserted into the card slot 24, the CPU 21 receives the instruction. , A reproduction command is issued to the video data reproduction circuit 26.
[0059]
Upon receiving the instruction, the video data reproducing circuit 26 reads the data at the designated position from the IC card 23 via the card slot 24 and extracts the video data from a predetermined recording format using a data compression means such as JPEG. Decode and output as Y, Cb, Cr component signals.
[0060]
By the way, the operating frequency of the video data reproducing circuit 26 is not specially defined, though there are restrictions due to the processing speed and the electrical characteristics of the LSI to be constituted. In a video signal processing system such as a television video signal or a DVD video signal, generally, Y, Cb, and Cr component signals conforming to ITU-R recommendation BT601 are often used, and therefore, the system clock is set to 13.5 MHz M / N times as high as 13.5 MHz. Since there are many frequencies, the output clock frequency of the system clock generation circuit 25 dedicated to card reproduction is set to 135 MHz.
[0061]
Therefore, the operating frequency of the video data reproducing circuit 26 and the writing frequency of the image memory circuit 27 are also set to 135 MHz. At this time, when examining the beat disturbance at the card system clock frequency of 135 MHz, as shown by the crosses in the CCK column in FIG. It can be seen that it overlaps with.
[0062]
Here, referring to the video signal of the television broadcast, as shown in FIGS. 5A and 6A, the effective video period in which the video signal actually exists and the blanking period in which the video signal does not exist, as shown in FIGS. Can be divided. Therefore, by performing control such that the video data reproduction circuit 26 operates only during a period other than the effective video period, the IC card 23 is reproduced without causing beat interference to the television broadcast displayed on the liquid crystal display 20. It becomes possible.
[0063]
Hereinafter, setting of periods other than the effective video period and the operation of the video data reproducing circuit 26 at that time will be described.
[0064]
First, in the horizontal scanning period, the LPF / sync separation circuit 4 separates and extracts the horizontal synchronization signal of the second stage in FIG. 5B during the horizontal blanking period of the first stage in FIG. The signal at the third stage in FIG. 5B is obtained from the effective video period based on the horizontal synchronizing signal. It is assumed that 32 + 128 + 116 = 276 samples. This period is shorter than the horizontal blanking period in the EIA studio standard RS-170A of FIG. 5A, but there is no problem if it is within the horizontal blanking period.
[0065]
Further, based on the signals of the second and third stages in FIG. 5B, the processing delay time α in the channel selection demodulation circuit 2, the AD conversion circuit 7, and the LPF / sync separation circuit 4, and the channel selection demodulation circuit 2 The period shown in the fourth row of FIG. 5 (B) obtained in consideration of the reception processing and the variation β is a period during which no beat interference is caused to the effective video signal of the channel selection demodulation circuit 2. Is hereinafter referred to as a horizontal non-video period.
[0066]
Subsequently, in the vertical scanning period, the vertical synchronization signal of the second stage in FIGS. 6A and 6B is separated and extracted. Since the period from the front end of the vertical synchronization signal to 3H and from the rear end to 14H is the vertical blanking period according to the EIA studio standard RS-170A of the first stage in FIGS. 6A and 6B, FIG. The period shown in the third row of (A) and (B) is a period in which no beat disturbance is applied to the effective video signal of the channel selection demodulation circuit 2, and this period is referred to as a vertical non-video period.
[0067]
As described above, the timing generation circuit 22 sets the horizontal non-video period and the vertical non-video period based on the horizontal synchronization signal and the vertical synchronization signal from the LPF / sync separation circuit 4, and sets the set horizontal non-video period and the vertical non-video period. The non-video period is output to the CPU 21.
[0068]
The CPU 21 receives the input and controls the card system clock generation circuit 25. That is, when displaying a television broadcast on the liquid crystal display 20, the CPU 21 does not cause a beat disturbance to the television broadcast on the liquid crystal display 20 when a card reproduction instruction is externally given. As described above, in order to stop the operation of the video data reproduction circuit 26 during the effective video period, the clock output of the card system clock generation circuit 25 is permitted only during the horizontal non-video period and the vertical non-video period, and the card system clock generation is performed. The circuit 25 complies with the command.
[0069]
The video data reproducing circuit 26 reads data at a designated position from the IC card 23 via the card slot 24 during clock input, and converts video data from a predetermined recording format using a data compression means such as JPEG. The signal is extracted and decoded, output as Y, Cb, and Cr component signals, and written to the image memory circuit 27.
[0070]
While the clock is stopped, the operation immediately before the stop is stored, and when the clock input is started again, the operation immediately before the stop is continuously performed. Then, such processing is repeated intermittently, and is stored in the image memory circuit 27.
[0071]
When the data reproduction for the card reproduction instruction given first (for example, an instruction to reproduce a certain still image) is completed and the decoded data is stored in the image memory circuit 27, the CPU 21 generates the card system clock. The operations of the circuit 25 and the video data reproducing circuit 26 are stopped.
[0072]
The clock for reading the video data from the image memory circuit 27 is the liquid crystal system clock, and no beat disturbance occurs in the liquid crystal system clock as described above. Reading is performed from the image memory circuit 27 at a timing synchronized with the television broadcast, converted into an RGB signal by the RGB conversion circuit 28, and then superimposed by the scaling circuit 11. The superposition method may be, for example, a picture-in-picture method or a method such as alpha blending.
[0073]
As described above, according to the video signal processing device according to the present embodiment, the IC card can be intermittently reproduced during the specific period of the television broadcast wave. Beat interference caused by the harmonic component jumping into the channel selection demodulation circuit 2 can be reliably suppressed.
[0074]
Further, in the above configuration, another card reproduction instruction (for example, a reproduction instruction of additional information relating to video information recorded on the IC card, or a recording date / time, a recording channel display instruction) is given through the touch key or the remote controller. In this case, when recognizing that the IC card 23 is inserted into the card slot 24, the CPU 21 issues a reproduction command to the video data reproduction circuit 26 in accordance with the given instruction. Upon receiving the instruction, the video data reproducing circuit 26 reads the data at the designated position from the IC card 23 via the card slot 24, and adds additional information relating to video information from a predetermined recording format, for example, data relating to recording date and time, recording channel. Is extracted and output to the CPU 21.
[0075]
The CPU 21 identifies additional information related to video information, for example, a recording date and a recording channel from the extracted data, and creates character data. The OSD circuit 13 is a circuit for converting characters from character data to video as RGB signals and outputting the signals, and performs output at a timing synchronized with television broadcasting in accordance with the character data from the CPU 21.
[0076]
The scaling circuit 11 superimposes additional information on the video information recorded on the IC card 23, for example, the recording date and time, the recording channel, and the like as characters on the video of the television broadcast. The recorded contents of the card 23 can be grasped.
[0077]
Still further, in the above configuration, a detection circuit for detecting that the IC card 23 is mounted in the card slot 24 may be provided, and the detection result may be notified to the CPU 21. Accordingly, in the above description, when the CPU 21 to which the card reproduction instruction is given through the touch key or the remote controller recognizes that the IC card 23 is inserted into the card slot 24, the CPU 21 reproduces the video data according to the given instruction. Although the reproduction command is issued to the circuit 26, the reproduction process can be performed from the IC card 23 immediately after the IC card 23 is inserted into the card slot 24.
[0078]
This means that the IC card 23 can be automatically reproduced without putting any burden on the user who has inserted the IC card 23 for the purpose of viewing or checking the recorded contents of the IC card 23.
[0079]
【The invention's effect】
Since the video signal processing device according to the present invention has the above-described configuration, while displaying the channel selection demodulation signal of the television broadcast wave on a display device such as a liquid crystal panel, when performing a recording medium reproduction process, The following effects can be obtained. Hereinafter, the effect when an IC card is used as a recording medium will be described.
[0080]
The video signal processing device according to the present invention, when inserting an IC card into the IC card slot and playing back the IC card, sets a period other than the effective video period from the video signal of the received television broadcast, Only during the period other than the effective video period, the playback process from the IC card and the memory write process for combining the intermittently played information are performed, and the clock is output from the memory with a clock that removes the harmonic component from the broadcast wave band of the selected channel. The read image is superimposed on the television broadcast image.
Therefore, at the time of the IC card reproduction processing, it is possible to reliably suppress the beat disturbance to the video caused by the harmonic of the clock jumping into the channel selection demodulation circuit. That is, when the IC card is reproduced for the purpose of viewing or confirming the recorded contents of the IC card while watching the television broadcast, the reproduction of the IC card can be performed without interruption of the television image. This is an extremely excellent effect that a high-quality image free from beat interference caused by a harmonic component of the system clock jumping into the channel selection demodulation circuit can be displayed.
[0081]
Further, the video processing device according to the present invention has a configuration in which additional information relating to video information recorded on the IC card, for example, recording date and time, recording channel, and the like are superimposed as characters on the television broadcast video.
Therefore, when the IC card is reproduced for the purpose of confirming the recorded contents of the IC card while watching the television broadcast, the recorded contents of the IC card can be grasped without interruption of the television image. Because of the superimposition, an excellent effect of minimizing the influence on the original television broadcast video is achieved.
[0082]
Further, the video processing device according to the present invention includes a clock generation circuit that generates a video data reproduction circuit operation clock only during a period other than the effective video period of the television broadcast.
Therefore, it is possible to efficiently reproduce the IC card without causing the harmonic component of the clock to cause a beat disturbance in the channel selection demodulation circuit.
[0083]
Further, the video processing device according to the present invention is provided with a detection circuit for detecting that an IC card is mounted, and performs a reproducing process from the IC card immediately after mounting the IC card.
Therefore, there is an excellent effect that the IC card can be automatically reproduced without putting any burden on the user who has mounted the IC card for the purpose of viewing or checking the recorded contents of the IC card.
[Brief description of the drawings]
FIG. 1 is a circuit diagram schematically illustrating a video signal processing device according to an embodiment of the present invention.
FIG. 2 is a signal waveform diagram of each section of a circuit according to the embodiment of the present invention.
FIG. 3 is a signal waveform diagram of each part of a scaling and double speed conversion circuit in the embodiment of the present invention.
FIG. 4 is an explanatory diagram showing a relationship between a selected channel and harmonic interference in the embodiment of the present invention.
FIG. 5 is a signal waveform diagram in a horizontal period of the timing generation circuit according to the embodiment of the present invention.
FIG. 6 is a signal waveform diagram in a vertical period of the timing generation circuit according to the embodiment of the present invention.
FIG. 7 is a circuit configuration diagram illustrating an example of a conventional liquid crystal television receiver.
FIG. 8 is a circuit configuration diagram showing another example of a conventional liquid crystal television receiver.
[Explanation of symbols]
1 receiving antenna
2 Tuning demodulation circuit
3 Phase locked loop (PLL)
4 LPF / sync separation circuit
5 Phase comparison / VCO circuit
6 counter
7 AD conversion circuit
8 YC separation circuit
9 color demodulation circuit
10 RGB conversion circuit
11 Scaling circuit
12 double speed conversion circuit
13 OSD circuit
14 LCD system clock generation circuit
15. System clock generation circuit for LCD
16 Synchronous generation circuit
17 Display device
18 DA conversion circuit
19 LCD drive circuit
20 LCD display
21 CPU
22 Timing generation circuit
23 IC card
24 card slots
25 Card system clock generator
26 Video data playback circuit
27 Image memory circuit
28 RGB conversion circuit
31 LCD television receiver
32 liquid crystal display unit
33 Tuning demodulation circuit
34 Clock Generation Circuit
35 LCD display
36 DA conversion circuit
37 LCD drive circuit
38 receiving antenna
39 CPU
40 scan conversion circuit
41 AD conversion circuit
42 Phase Locked Loop (PLL)
43 Phase comparator
44 Low-pass filtering circuit
45 Voltage controlled oscillator
46 1 / 2N frequency divider
47 decoder
48 divider circuit
49 IC card
50 card slots
51 Video data playback circuit
52 RGB conversion circuit
53 DA conversion circuit
54 Card System Clock Generator
55 switch circuit
61 LCD television receiver
62 multiplication ratio memory
63 CPU
64 channel selection microcomputer

Claims (4)

A tuning demodulation circuit for receiving and tuning a television broadcast wave, a recording medium on which video information is recorded, a reproduction circuit for reproducing video information from the recording medium, the tuning demodulation circuit, and A video signal processing device comprising a display device for displaying an output video signal of the reproduction circuit;
A timing generation circuit for detecting a synchronization signal in an output video signal of the channel selection demodulation circuit and setting a period other than an effective video period corresponding to a retrace period,
The reproduction circuit,
Along with being controlled so as to perform a reproduction process from the recording medium only during a period other than the effective video period set by the timing generation circuit, it is also possible to combine information temporarily reproduced by the reproduction circuit and temporarily store the information. A memory circuit,
A video signal processing device comprising: a superimposing circuit for superimposing information of the memory circuit on an output video signal of the channel selection demodulation circuit. The reproduction circuit reproduces additional information related to video information from the recording medium,
2. The video signal processing device according to claim 1, wherein the superimposing circuit converts the additional information as characters and superimposes the output information on the video signal output from the channel selection demodulation circuit. The reproduction circuit includes a clock generation circuit that generates a reproduction circuit operation clock only during a period other than the effective video period set by the timing generation circuit, and stops the reproduction operation during a period other than the effective video period. 2. The video signal processing device according to 1. 2. The video signal processing apparatus according to claim 1, further comprising a detection circuit for detecting that the recording medium is mounted, wherein the reproduction circuit performs a reproduction process from the recording medium immediately after mounting the recording medium. .

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