JP4606201B2 - Display control device, display device, and display control method - Google Patents

Description

  The present application relates to a display control technique for a matrix type display panel such as a plasma display panel (PDP) or a liquid crystal display panel.

In recent years, various so-called matrix type display panels such as PDPs and liquid crystal display panels have been provided in order to reduce the thickness of display devices. In this type of display device, since the display panel is driven using a digital drive signal, electromagnetic waves are emitted as unnecessary radiation from a circuit mounted in the device. Such electromagnetic waves become noise at the time of broadcast reception in the broadcast reception tuner mounted on the display device, and cause deterioration of video quality. Therefore, various proposals have been made for preventing the influence of electromagnetic waves generated when the display panel is driven (see, for example, Patent Document 1).
JP 2000-338932 A

By the way, in the above-described conventional method, by changing the application period of the drive signal applied to the display panel with time, the spectrum of the generated electromagnetic wave is dispersed, and the natural frequency of the electromagnetic wave is broadcast wave. The method of preventing concentration in the vicinity of the reception frequency was adopted. However, this method merely has a configuration in which the cycle of the drive signal is changed every predetermined period. Therefore, the frequency of the electromagnetic wave (and its harmonic component) generated as unnecessary radiation is equal to the reception frequency of the broadcast wave. This could cause degradation of video quality.

  The present application has been made in view of the circumstances described above. As an example of the problem, the influence on the image quality caused by the electromagnetic waves generated when driving the matrix type display panel is suppressed, and the leap of the image quality is achieved. It is an object of the present invention to provide a display control device and a display device that can improve the quality of the image.

In order to solve the above-described problem, in one aspect of the present application, the display control device according to claim 1 is a display control for displaying various images on a matrix type display panel in which a plurality of pixels are arranged on a matrix. A receiving means for receiving a broadcast video signal; a detecting means for detecting a frequency of the received video signal as a first frequency; and a reference clock signal serving as a reference for signal processing at a second frequency. A reference clock generating means for generating the signal, a processing means for performing signal processing on the video signal in accordance with the reference clock signal, and a drive signal for driving the display panel using the video signal after the signal processing. Display panel driving means for generating the three driving frequencies and supplying the driving signal to the display panel, and detection result of the first frequency in the detecting means In response, and control means for changing at least one of the second frequency and a third frequency, wherein the display panel driving means, of the drive signal supplied to the display panel based on said first frequency It is characterized by changing the waveform .

According to another aspect of the present invention, a display device according to claim 4 is a display of the display control device according to any one of claims 1 to 3 and a matrix type display in which a plurality of pixels are arranged on a matrix. And a panel.

Furthermore, in another aspect of the present application, the display control method according to claim 5 displays various videos corresponding to the broadcast video signal on a matrix type display panel in which a plurality of pixels are arranged on a matrix. A display control method in a display control device for detecting a frequency of a video signal received by a receiving unit mounted on the display control device as a first frequency, and a reference for the signal processing At least one of a second frequency for generating a reference clock signal and a third frequency for generating a drive signal for driving the display panel using the video signal is set to the detected first frequency. A second step of changing the reference clock signal, a third step of generating the reference clock signal at the changed second frequency, and the reference clock signal A fourth step of performing signal processing with respect to have the video signal, a driving signal for driving the display panel using the video signal after the signal processing generated in the third frequency which is the change, the second And changing the waveform of the driving signal based on one frequency and supplying the driving signal to the display panel.

  Hereinafter, embodiments of the present application will be described with reference to the drawings. In the following embodiments, the display control device of the present application is applied to a display device equipped with a PDP driven by a so-called subfield method. However, the embodiment is merely an example of the present application, and the display control apparatus of the present application can be applied to all display apparatuses equipped with a matrix type display panel such as a liquid crystal panel.

  The “subfield method” here divides one field of a video signal into N subfields and emits a PDP for each subfield to display a video corresponding to one field. Means the way.

[1] Embodiment [1.1] Configuration of the First Embodiment First, an outline of the present embodiment will be described with reference to FIG. 1 which is a block diagram showing the configuration of the display device DIS. As shown in the figure, the display device DIS according to the present embodiment broadly includes a tuner 1, a video processing circuit 2, a panel drive circuit 3, a PDP 4, and a frequency variable unit 5. The display device DIS receives a broadcast wave such as terrestrial analog broadcast in the tuner 1, digitally processes the video signal Stv included in the broadcast wave in the video processing circuit 2, and converts the PDP 4 based on the signal after the digital processing. It is for driving and displaying video corresponding to the broadcast program.

  Here, in a display device equipped with a matrix-type display panel (specifically, PDP 4) such as the display device DIS, electromagnetic waves and their harmonics (hereinafter simply referred to as “electromagnetic waves”) as unwanted radiation. As a result, the video quality is degraded. Examples of electromagnetic wave generation sources that can cause such deterioration include (generation source 1) system clock generation circuit 23 and drive clock generation circuit 32 that generate a clock for operation, and (generation source 2) PDP4. Therefore, if electromagnetic waves generated from both generation sources can be reduced, it is possible to suppress degradation of video quality.

Therefore, in the present embodiment, the following method is adopted.
(1) Measures against electromagnetic waves generated at the time of clock signal generation First, the frequencies of electromagnetic waves radiated from the system clock generation circuit 23 and the drive clock generation circuit 32 that generate the operation clock are output from both the circuits 23 and 32. Depending on the clock frequency of the clock signal, if the frequency of the clock signal output from each circuit 23 and 32 is f2 and f3, respectively, the center frequency of the electromagnetic wave spectrum corresponding to unwanted radiation is also f2 and f3, respectively. (The frequencies of the harmonic components are integer multiples of f2 and f3, respectively). When the center frequencies nf2 (n is an arbitrary integer) and mf3 (m is an arbitrary integer) of the electromagnetic wave are equal to the value of the reception frequency f1, or when the frequency becomes very close, the electromagnetic wave is received by the tuner 1 together with the broadcast wave. As a result, beat noise is generated, which causes degradation of video quality. Therefore, in the present embodiment, the frequency variable unit 5 sets the reception frequency f1 of the tuner 1 in order to prevent deterioration in video quality due to electromagnetic waves generated when signals are generated in the system clock generation circuit 23 and the drive clock generation circuit 32. Detection is performed, and the values of the frequencies f2 and f3 are varied based on the detection result so that the frequencies f1, nf2, and mf3 are not close to each other.
(2) Measures against electromagnetic waves caused by PDP On the other hand, similarly for electromagnetic waves generated from PDP4, the center frequency tf4 (t is an arbitrary integer) of the electromagnetic waves (including harmonic components) spectrum becomes equal to the reception frequency f1. Alternatively, when the frequencies are extremely close to each other, the electromagnetic wave becomes noise and causes deterioration of video quality. Therefore, from the viewpoint of improving the video quality, it is necessary to vary the frequency tf4 of the electromagnetic wave so that the frequency tf4 does not become equal to the reception frequency f1.

  In this regard, in the present embodiment, the following two methods are used in combination.

< Method 1 >
First, the center frequency tf4 of the electromagnetic wave (and its harmonics) generally generated in the PDP 4 is set to the frequency of the drive signal applied to the PDP 4 (for example, the application frequency of the pixel data pulse DPj and the sustain pulses IPy and IPx in FIG. 5). Depends on
It is known that the relationship of the frequency of the driving signal × t (t is an integer) ≈the center frequency of the electromagnetic wave spectrum (that is, the relationship of the frequency of the driving signal≈f4) is known. In the present embodiment, paying attention to such characteristics, the frequency variable unit 5 detects the reception frequency f1 of the tuner 1, changes the frequency f4 of the drive signal based on the detection result, and generates from the frequency f1 and the PDP4. The frequency tf4 of the electromagnetic wave was prevented from approaching (Method 1). Thereby, it is possible to significantly reduce the influence caused by the electromagnetic waves as unnecessary radiation generated in the PDP 4. A method for changing the frequency f4 of the drive signal will be described in detail later.

< Method 2 >
Further, in the experiment to the completion of the present application, by combining the method 2 described below with the method 1 described above, it is possible to suppress the generation amount of electromagnetic waves due to the PDP 4 and further improve the image quality. I came up with something. First, in an experiment leading to the completion of the present application, the relationship between the waveform of the drive signal and the electromagnetic wave generated from the PDP 4 was investigated, and it was found that the following relationship was established between the two.
<Relationship 1> The electromagnetic wave generated from the PDP 4 has a frequency component that depends on the rising and falling characteristics of the drive signal.
<Relationship 2> If the drive signal supplied to the PDP 4 has a steep rise and fall characteristic (that is, if a square wave drive signal containing a lot of high frequency components is supplied), the electromagnetic wave as unwanted radiation The amount of generation increases.

  Therefore, in the present embodiment, in combination with the above method 1, the waveform of the drive signal supplied to the PDP 4 is varied to reduce the radiation amount itself of the electromagnetic wave radiated from the PDP 4, and also depends on the waveform of the drive signal. The frequency component to be transmitted is prevented from approaching the reception frequency f1 (method 2).

  Hereinafter, a specific configuration of the display device DIS according to the present embodiment will be described.

  First, as in the conventional PDP, the PDP 4 is provided with column electrodes Dk (k = 1, 2,..., M) in the vertical direction of the display area, and row electrodes Yl (l) in the horizontal direction of the display area. = 1, 2,... N) and a row electrode Xl. The row electrode Yl and the row electrode Xl are formed in parallel with each other, and a cell CL as a light emitter is formed in a region where one column electrode Dk and one row electrode pair Yl, Xl intersect. Has been. Each cell CL repeats light emission and non-light emission by generating a predetermined wall charge in accordance with signals supplied to the column electrode Dk and the row electrodes Yl and Xl. The light emission state of each cell Cl Various images are displayed depending on the situation.

  Next, the tuner 1 is a tuner for analog broadcasting such as terrestrial analog broadcasting and BS analog broadcasting, and receives broadcast waves transmitted from each broadcasting station via the antenna AT. The tuner 1 demodulates the broadcast wave to be received into a TV video signal Stv and an audio signal, and outputs the audio signal to an audio output system (not shown), while the video signal Stv 2 to the synchronization detection circuit 21 and the display data generation unit 24.

  The video processing circuit 2 is an element for performing A / D (analog / digital) conversion and predetermined signal processing on the video signal Stv supplied from the tuner 1 and supplying the converted signal to the panel drive circuit 3. A synchronization detection circuit 21, a PLL circuit 22, a system clock generation circuit 23, and a display data generation unit 24 are included.

  The synchronization detection circuit 21 of the video processing circuit 2 detects a vertical synchronization signal and a horizontal synchronization signal included in the video signal Stv supplied from the tuner 1 and also performs horizontal synchronization in synchronization with the detection timing of each synchronization signal. A detection signal H and a vertical synchronization detection signal V are generated and supplied to the PLL circuit 22 and the drive control unit 33 of the panel drive circuit 3, respectively. The PLL circuit 22 generates a sampling clock signal Tck serving as a reference when sampling the video signal Stv in the display data generation unit 24 while synchronizing the phase with the horizontal synchronization detection signal H, and displays the generated sampling clock signal Tck. The data is supplied to the data generation unit 24.

The system clock generation circuit 23 has a crystal oscillation element 231. A clock signal is generated by applying a predetermined voltage to the crystal oscillation element 231, and display data is displayed as a system clock signal Sck (frequency f2). This is supplied to the generation unit 24 and the drive control unit 33 of the panel drive circuit 3. The “reference clock signal” in “Claims” corresponds to the system clock signal Sck, for example. As described above, when the value of the frequency f2 of the system clock signal Sck satisfies the relationship of f1≈nf2 with respect to the reception frequency f1 of the tuner 1, electromagnetic waves generated when the system clock signal Sck is transmitted are imaged. It becomes a factor of deterioration of quality. Therefore, in the present embodiment, the value of the frequency f2 of the system clock signal Sck is varied by supplying a control signal from the frequency variable unit 5.

Note that the method of changing the frequency in the system clock generation circuit 23 is arbitrary, and the frequency f2 may be sequentially changed over time at predetermined intervals (that is, the frequency f2 may be changed at every predetermined number of clocks). In this embodiment, for the sake of concrete description, the description will be made on the assumption that a method of uniformly changing the frequency f2 is adopted (that is, the frequency f2 is fixed to a frequency different from the reception frequency f1). This method will be described later. As a method for uniformly changing the frequency f2, for example, the oscillation frequency itself in the crystal oscillation element 231 may be varied, or a modulation circuit for performing frequency modulation on the output signal is provided, and this modulation is performed. A method of changing the frequency based on a control signal from the frequency variable unit 5 may be used.

  The display data generation unit 24 performs A / D conversion on the TV signal Stv supplied from the tuner 1 in accordance with the sampling clock signal Tck supplied from the PLL circuit 22. Then, the display data generation unit 24 performs predetermined signal processing (more specifically, error diffusion processing or dither processing) on the converted digital signal using the system clock signal Sck, and displays the display data. Sd is generated. At this time, the display data generation unit 24 generates display data Sd in units of subfields, and sequentially supplies the generated display data Sd to the frame memory of the panel drive circuit 3.

  Next, the panel drive circuit 3 is a circuit for driving the PDP 4 on the basis of the display data Sd supplied from the video processing circuit 2 and displaying video corresponding to the broadcast program. The circuit 32, the drive control unit 33, and the drive unit 34 are included.

  The frame memory 31 is composed of, for example, a VRAM, and temporarily records the display data Sd supplied from the display data generation unit 24 in accordance with the control signal Sc supplied from the drive control unit 33. The display data Sd recorded in the frame memory 31 is read for each line in accordance with the read timing signal included in the control signal Sc, and is sequentially supplied to the address driver 341 of the drive unit 34.

The drive clock generation circuit 32 includes a crystal oscillation element 321, and generates a clock signal having a frequency f3 by applying a predetermined voltage to the crystal oscillation element 321, and supplies the drive control signal 33 as the drive clock signal Gck. Supply. The “drive clock signal” in “Claims” corresponds to the drive clock signal Gck, for example. As described above, the electromagnetic wave generated in the drive clock generation circuit 32 is also a factor of deterioration in video quality. Therefore, in this embodiment, a voltage applied to the crystal oscillation element 321 by supplying a control signal from the frequency variable unit 5. The value is changed to vary the value of the frequency f3 of the drive clock signal Gck. Note that the method of changing the frequency f3 in the drive clock generation circuit 32 is arbitrary as in the system clock generation circuit 23.

Next, the drive control unit 33 is configured by a CPU, for example, and controls the frame memory 31 and the drive unit 34. For example, the drive control unit 33 generates a control signal Sc synchronized with the system clock signal Sck supplied from the system clock generation circuit 23 and supplies the control signal Sc to the frame memory 31. In addition, the drive control unit 33 generates a reset signal Tr in synchronization with the drive clock signal Gck supplied from the drive clock generation circuit 32 and supplies the reset signal Tr to the first and second sustain drivers 342 and 343 of the drive unit 34. Further, the drive control unit 33 generates a data timing signal Td based on the drive clock signal Gck, supplies the data timing signal Td to the address driver 341 and the second sustain driver 343 of the drive unit 34, and generates sustain light emission timing signals Ty and Tx. Then, they are supplied to the first sustain driver 342 and the second sustain driver 343, respectively.

  Here, since the values of the frequencies f2 and f3 of the system clock signal Sck and the drive clock signal Gck are changed according to the reception frequency f1 in the tuner 1 as described above, the changes in the frequencies f2 and f3 are caused. Accordingly, the frequencies of the control signal Sc, the reset signal Tr, the data timing signal Td, and the sustain light emission timing signals Ty and Tx are varied. This will be described in detail later.

Next, the drive unit 34 is an element for driving the PDP 4 based on the display data Sd supplied from the frame memory 31, and includes an address driver 341, a first sustain driver 342, and a second sustain driver 343. Composed. As shown in FIG. 5 (details will be described later), the drive unit 34 repeats the reset period, the address period, and the sustain period as one subfield N times, and finally applies an erase pulse to all the cells. By executing main erasure that resets the wall charges to the erased state, an image corresponding to display data Sd for one field is displayed on the PDP 4. Here, (a) the reset period is a signal application period in which the reset pulses RPx and RPy are applied to all the cells CL of the PDP 4, and (b) the address period is based on the display data Sd. This is a period for selectively discharging each cell CL and setting the light emission state or the non-light emission state of each cell CL in the subsequent sustain period. Further, (c) the sustain period is a period for maintaining the light emission state in each cell CL in the light emission state by applying the sustain pulses IPy and IPx (see FIG. 5) to each cell CL of the PDP 4. .

  Here, the drive unit 34 will be described in detail with reference to FIG.

First, among these elements, the address driver 341 is a driver circuit for driving the column electrode Dk provided in the PDP 4 and is a pixel data pulse DPj based on the display data Sd supplied from the frame memory 31 (see FIG. 5). And is sequentially applied to each column electrode Dk in synchronization with the data timing signal Td supplied from the drive control unit 33.

On the other hand, the first sustain driver 342 and the second sustain driver 343 are driver circuits for driving the row electrodes Yl and Xl of the PDP 4, respectively, and the reset signal Tr and data timing supplied from the drive control unit 33. Various drive signals are applied to the row electrodes Yl and Xl according to the signal Td and the sustain light emission timing signals Ty and Tx. This first sustain driver 342 second sustain driver 343, as shown in FIG. 2, in addition to having a sustain pulse generator and a reset pulse generator as a common element to both drivers, the first Sustain command driver 342 Further, a scan pulse generator is provided.

The reset pulse generator includes a power source B2 (B22 in the second sustain driver 343. Hereinafter, the parentheses indicate elements of the second sustain driver 343), and a transistor Q5 connected in series thereto. (Q55) and a buffering resistor R1 (R11). The gate of the transistor Q5 (Q55) is supplied with a signal GT5 (GT55) corresponding to the reset signal Tr. Then, the transistor Q5 (Q55) is turned on in response to the signal GT5 (GT55), at the same time the reset pulse Rpy and Rpx to all the row electrodes Xl and Yl from the reset pulse generator (see FIG. 5) is applied Is done. When the reset pulses Rpy and Rpx are applied, a reset discharge is generated in all the cells CL of the PDP 4 at the same time, and after the discharge is converged, a predetermined amount of wall charges are accumulated in all the cells CL and can emit light. It becomes a state.

  Next, as shown in FIG. 2, the scan pulse generator is composed of transistors Q6 to Q8, power supplies B3 and B4, diodes D4 and D5, and resistor R2, and performs scan pulse SP (see FIG. 5). It is a circuit portion for applying to the electrode Yl. In order to realize such a function, signals GT6 to GT8 corresponding to the data timing signal Td are applied to the transistors Q6 to Q8 of the scan pulse generator, and these transistors Q6 to Q8 are turned on / off. Thus, the scan pulse SP is sequentially applied to each row electrode Yl at a timing synchronized with the data timing signal Td (that is, synchronized with the output timing of the pixel data pulse DPj from the address driver 341). As a result, among the cells CL belonging to the row electrode Yl to which the scan pulse SP is applied, the wall charges disappear only in the cell CL to which the pixel data pulse DPj is simultaneously applied, and the cell CL transitions to a non-light emitting state.

On the other hand, the sustain pulse generator is a circuit part that generates sustain pulses IPy and IPx (see FIG. 5) for controlling the light emission sustain period in the cell CL of the PDP 4, and includes a power supply B1 (B11) and transistors Q1 to Q4. (Q11 to Q44), diodes D1 to D3 (D11 to D33), coils L1 and L2 (L11 and L22), and a capacitor C1 (C11). Among these elements, the transistor Q1 (Q11) and the power supply B1 (B11) are elements provided for controlling the application period of the sustain pulses IPy and IPx, and are signals GT1 corresponding to the sustain light emission timing signals Ty and Tx. When the transistor Q1 (Q11) is turned on by (GT11) , the voltage values of the sustain pulses IPy and IPx are maintained at the supply voltage value from the power supply B1 (B11).

  On the other hand, the transistor Q3 (Q33), the diode D2 (D22), the coil L2 (L22), and the capacitor C1 (C11) are elements provided for controlling the rise times of the sustain pulses IPy and IPx. In this circuit portion, the transistor Q3 (Q33) is turned on by a signal GT3 (GT33) corresponding to the sustain light emission timing signal Ty (Tx) supplied from the drive control unit 33, and this transistor is multiplied to turn on the capacitor C1 (C11). As a result, the sustain pulse IPy (IPx) gradually rises. Further, the transistor Q2 (Q22), the diode D1 (D11), the coil L1 (L11), and the capacitor C1 (C11) are elements provided for controlling the falling time of the sustain pulse IPy (IPx). In this circuit portion, the transistor Q2 (Q22) is turned on by a signal GT2 (GT22) corresponding to the sustain light emission timing signal Ty (Tx) supplied from the drive control unit 33, and this transistor is multiplied to turn on the capacitor C1 (C11). As a result, the sustain pulse IPy (IPx) gradually falls.

  Here, as described above, the electromagnetic wave that causes the deterioration of the image quality is generated due to the drive signal applied to the PDP 4, particularly the pixel data pulse DPj and the sustain pulses IPy and IPx that are frequently applied. The frequency tf4 of the electromagnetic wave depends on the frequency of these pulse signals. Therefore, in order to improve the video quality, it is necessary to vary the frequency of the pixel data pulse DPj and the sustain pulses IPy and IPx. In this regard, in the present embodiment, the frequency of each pulse signal DPj, IPy, IPx is varied by the following method.

< Regarding the pixel data pulse DPj >
First, the pixel data pulse DPj is output at a timing synchronized with the data timing signal Td supplied from the drive control unit 33, and the data timing signal Td is output at a timing synchronized with the drive clock signal Gck. It has become. Accordingly, the frequency of the pixel data pulse DPj varies in proportion to the clock frequency f3 of the drive clock signal Gck. By changing the frequency f3 of the drive clock signal Gck in the system clock generation circuit 23, the pixel data pulse DPj The frequency (obtained as the reciprocal of the period TD in FIG. 5) can be varied.

<About Sustain Pulse IPy and IPx >
Next, regarding the sustain pulses IPy and IPx, these pulses are generated based on the signals GT1 (GT11) to GT4 (GT44) included in the sustain light emission timing signal Ty (Tx) (see FIG. 2). Therefore, in order to vary the frequencies of the sustain pulses IPy and IPx (obtained as the reciprocal of the period TS in FIG. 5), it is necessary to control these signals GT1 (GT11) to GT4 (GT44). The specific contents of this control method will be described in detail with reference to FIG. 4A shows a relationship between the sustain pulse used in the display device DIS according to the present embodiment and the signals GT1 to GT4 (GT11 to GT44) necessary for generating the sustain pulse. It is a timing chart, and (b) is a timing chart showing a relationship between a sustain pulse used in a conventional display device and signals GT01 to GT04 used for generating the sustain pulse.

As shown in FIG. 6A, it can be seen that the period TS of the sustain pulse IPy (IPx) has a property depending on the periods T1 to T4 of GT1 (GT11) to GT4 (GT44). Further, since the frequency f4 of the sustain pulse IPy (IPx) is obtained as the reciprocal of the period TS, a signal included in the sustain light emission timing signal Ty (Tx) with the change of the frequency f3 of the drive clock signal Gck. By varying the periods T1 to T4 of GT1 to GT4, the frequencies f4 of the sustain pulses IPy and IPx can be varied. In the present embodiment, from this point of view, the drive control unit 33 varies the frequency f3 of the drive clock signal Gck, thereby varying the periods T1 to T4 of the signals GT1 to GT4 included in the sustain light emission timing signal Ty (Tx). The configuration to be adopted was adopted.

  Further, since the sustain pulses IPy and IPx have a large number of pulses to be applied and occupy a large weight as an electromagnetic wave generation factor, the pulse waveform can be varied as shown in the method 2 to suppress the generation of the electromagnetic wave. Necessary. For this waveform adjustment, (1) the rise and fall characteristics of the sustain pulses IPy and IPx are adjusted to prevent the generation of frequency components near the reception frequency f1, and (2) the rise and fall of the sustain pulses IPy and IPx. It is necessary to make the time required for the fall longer than in the conventional method (b) to reduce the radiation amount itself. Therefore, in the present embodiment, the application times t1 to t4 of the signals GT1 to GT4 (GT11 to GT44) are varied to change the pulse waveforms of the sustain pulses IPy and IPx.

Note that the following points need to be taken into account when controlling the waveform.
< Note 1 > Since the light emission amount of the cell CL depends on the energy amount of the sustain pulses IPy and IPx applied to each cell CL, the energy amount of the sustain pulses IPy and IPx is maintained in order to maintain the clearness of the image. (That is, the areas of the sustain pulses IPy and IPx on the timing chart) cannot be changed, and < Note 2 > The longer the rise time and the fall time of the sustain pulses IPy and IPx, The longer the time until the voltage values of both the pulses IPy and IPx are clamped to the supply voltage value of the power supply B1 (B11)), the amount of radiation of the electromagnetic wave can be reduced. In the embodiment, the circumference of each of the signals GT1 (GT11) to GT4 (GT44) Since the configuration in which the periods T1 to T4 are varied according to the reception frequency f1 is adopted, if the rise time of both the pulses IPy and IPx is long, an accurate gradation is caused by the influence of the adjacent pulses. This means that the display may not be possible. Therefore, it is necessary to determine the application times t1 to t4 in consideration of these points to consider.

  In addition, although the change method of application time t1-t4 of signal GT1-GT4 (GT11-GT44) is arbitrary, in this embodiment, it demonstrates as what has employ | adopted the following method. First, the relationship between the pulse waveforms of the sustain pulses IPy and IPx and the frequency component of the electromagnetic wave generated from the PDP 4 is experimentally obtained, and the signals GT1 to GT4 (GT11 to GT11) having the least influence at each reception frequency f1 are obtained according to the experimental results. The pattern of the application times t1 to t4 (hereinafter referred to as “application pattern”) of GT44) is determined in advance. Then, this application pattern is programmed in advance in the drive control unit 33, and the application pattern of the application times t1 to t4 is changed according to the reception frequency f1 detected by the frequency variable unit 5. By adopting this method, the application times t1 to t4 of the signals GT1 to GT4 (GT11 to GT44) are changed in accordance with the reception frequency f1 of the tuner 1, and the sustain waveform has the least influence on the reception frequency f1. It becomes possible to change the pulse waveforms of the pulses IPy and IPx. Note that a specific method for changing the application times t1 to t4 of the signals GT1 to GT4 is arbitrary. For example, a plurality of circuits corresponding to each application pattern may be provided in the drive control unit 33 to switch the circuits to be used. You may make it change like software.

  Next, the frequency variable unit 5 detects the reception frequency f1 in the tuner 1, controls the frequency f2 of the system clock signal Sck and the frequency f3 of the drive clock signal Gck according to the detection result, and controls the drive control unit 33. Thus, the application times t1 to t4 described above are varied. In order to realize such a function, in the present embodiment, the frequency variable unit 5 is provided with a memory (not shown), and in this memory, the frequency f2 of the system clock signal Sck and the frequency f3 of the drive clock signal Gck. Furthermore, a management table TBL for controlling the application times t1 to t4 is recorded.

  An example of the recorded contents of the management table TBL is shown in FIG. As shown in the figure, in this embodiment, the management table TBL includes the frequency setting values of the clock signals Sck and Gck output from the system clock generation circuit 23 and the drive clock generation circuit 32 for each reception frequency f1 in the tuner 1. Is stored. The frequency setting values stored in the management table TBL are set so that both the frequencies f2 and f3 have a relationship of f1 ≠ nf2 and mf3 (n and m are integers) with respect to the reception frequency f1. The frequency variable unit 5 controls the system clock generation circuit 23 and the drive clock generation circuit 32 based on the setting values stored in the management table TBL, thereby changing the frequencies f2 and f3.

  The management table TBL stores application patterns to be set at each reception frequency f1, and the frequency variable unit 5 controls the drive control unit 33 in accordance with the application patterns stored in the management table TBL. It is like that.

[1.2] Operation of Embodiment Next, a specific operation of the display device DIS according to the present embodiment having the above-described configuration will be described. First, when the user performs an input operation to change the reception frequency f1 on an operation unit (not shown) of the display device DIS, the reception frequency f1 of the tuner 1 is changed according to the input operation. Then, the frequency variable unit 5 detects the changed reception frequency f1 and searches the management table TBL based on the frequency f1.

  At this time, the method of detecting the reception frequency f1 in the frequency variable unit 5 is arbitrary. For example, the reception signal in the tuner 1 may be supplied to the frequency variable unit 5, and the frequency variable unit 5 may detect the reception frequency f1 from the reception signal. Further, when adopting a method for allowing the user to specify the reception frequency, the user's input operation may be detected by the frequency variable unit 5 and the reception frequency f1 specified by the user may be detected based on the input operation. Furthermore, the reception frequency f1 and the channel number may be set in advance, and the reception frequency f1 may be detected according to the channel number selected by the user.

Next, the frequency variable unit 5 reads the frequency setting value and the application pattern corresponding to the reception frequency f1 from the management table TBL, and sends a control signal indicating the read frequency setting value to the system clock generation circuit 23 and the drive clock generation circuit 32. And a control signal indicating the application pattern is supplied to the drive controller 33. As a result, in the system clock generation circuit 23 and the drive clock generation circuit 32, the values of the frequency f2 of the system clock signal Sck and the frequency f3 of the drive clock signal Gck are changed. In this way, when the frequencies f2 and f3 are changed, the display data generation unit 24 generates display data Sd corresponding to the video signal Stv using the system clock signal Sck after changing the frequency f2. At the same time, the control signal Sc is generated based on the drive clock signal Gck after the frequency f3 is changed, and the display data Sd is written to and read from the frame memory 31 based on the control signal Sc.

On the other hand, in the drive control unit 33, the data timing signal Td is generated based on the drive clock signal Gck after the change in the frequency f3, and the sustain light emission timing signal Tx, based on the drive clock signal Gck in which the frequency f3 is changed. Ty and reset signal Tr are generated, and the frequency of each signal changes accordingly.

In the drive control unit 33, application patterns of the signals GT1 (GT11) to GT4 (GT44) are set based on the control signal supplied from the frequency variable unit 5, and the sustain light emission is performed according to the newly set application pattern. Timing signals Ty and Tx are generated. As a result, the application times t1 to t4 of the signals GT1 (GT11) to GT4 (GT44) supplied to the sustain pulse generators of both sustain drivers 342 and 343 are changed, and the pulse waveforms of the sustain pulses IPy and IPx change, The PDP 4 is driven using the sustain pulses IPy and IPx after the waveform change.

  Specific operations of the drive control unit 33 and the drive unit 34 at this time will be described with reference to FIG. FIG. 5 is a diagram illustrating a driving sequence in the driving unit 34.

  At this time, the drive control unit 33 first generates a reset signal Tr at the arrival timing of the reset period, and supplies the reset signal Tr to the first and second sustain drivers 342 and 343 of the drive unit 34. As a result, the signals GT5 and GT55 corresponding to the reset signal Tr are applied to the transistors Q5 and Q55 of the reset pulse generator provided in both the sustain drivers 342 and 343, and both the transistors Q5 and Q55 are turned on. When the transistors Q5 and Q55 are turned on, reset pulses Rpy and Rpx are applied to all the cells CL, a predetermined amount of wall charges are accumulated in all the cells CL, and the light emission is enabled.

Thereafter, when an address period comes after a predetermined time has elapsed, the drive control unit 33 generates the data timing signal Td in synchronization with the system clock signal Sck after the frequency f2 is changed, and drives the data timing signal Td. To the address driver 341 and the first sustain driver 342 of the unit 34. As a result, in the address driver 341, the pixel data pulse DPj is generated based on the display data Sd, and the pixel data pulse DPj is synchronized with the data timing signal Td supplied from the drive control unit 33. Applied to Dk. As a result, the cycle TD of the pixel data pulse DPj is varied with the frequency f3 of the drive clock signal Gck.

  Further, during this address period, the scan pulse generator of the first sustain driver 342 generates the scan pulse SP by applying the signals GT6 to GT8 corresponding to the data timing signal Td, and the generated scan pulse SP. Are sequentially applied to the row electrode Yl at a timing synchronized with the pixel data pulse DPj. As a result, in the cell CL belonging to the row electrode Yl to which the scan pulse SP is applied, discharge occurs only when the pixel data pulse DPj is applied at the same time, and the wall charges are erased to enter a non-light emitting state. At this time, since no discharge occurs in the cell CL to which the pixel data pulse is not applied at the same time, the wall charges remain and the light emission enabled state is maintained.

Next, when the sustain period arrives, the drive control unit 33 generates the sustain light emission timing signals Ty and Tx based on the drive clock signal Gck after the frequency f3 is changed, and corresponds to both signals Ty and Tx. The periods T1 to T4 of the signals GT1 (GT11) to GT4 (GT44) change as the frequency f3 is changed.

  In addition, the drive control unit 33 generates the sustain light emission timing signals Ty and Tx according to the newly set application pattern and supplies the sustain light emission timing signals Ty and Tx to the drive unit 34. On the other hand, in the first and second sustain drivers 342 and 343, signals GT1 to GT4 and GT11 to GT44 corresponding to the sustain light emission timing signals Ty and Tx are applied to the transistors Q1 to Q4 and Q11 to Q44 to generate a sustain pulse. The sustain pulses IPy and IPx are sequentially generated in the unit, and as a result, the cycles TS and waveforms of the sustain pulses IPy and IPx are changed.

  At this time, in the sustain pulse generation unit, the transistor Q3 (Q33) is turned on by the signal GT3 (GT33) and stored in the capacitor C1 (C11) when the transistors Q1 and Q2 (Q11 and Q22) are off. Charge is supplied to the row electrode Yl (Xl), and the sustain pulses IPy and IPx rise. The transistor Q3 (Q33) is turned off after a lapse of time t3 from the start of application of the signal GT3 (GT33). Conversely, the transistor Q1 (Q11) is turned on by the signal GT1 (GT1) (Q2 is kept off). ) State. As a result, the voltage value of the sustain pulse IPy (IPx) shifts to the supply voltage value of the power supply B1 (B11).

  This state lasts for a time t1, and after t1, the transistor Q1 (Q11) is turned off based on the signal GT1 (GT11), and the transistor Q2 is turned on by the signal GT2 (GT22), and Q3 (Q33 ) Goes off. As a result, the capacitor C1 (C11) is charged based on the electric charge stored in the cell CL, and the sustain pulse IPy (IPx) gradually falls.

  Thereafter, the series of operations described above is repeated, and various videos are displayed on the PDP 4.

  As described above, the display device DIS according to the present embodiment includes a matrix type PDP 4 in which cells CL corresponding to a plurality of pixels are arranged on a matrix, and a tuner 1 that receives a video signal broadcast at a reception frequency f1. A frequency variable unit 5 for detecting the value of the reception frequency f1, a system clock generation circuit 23 and a drive clock generation circuit 32 for generating a system clock signal Sck as a reference for signal processing on the video signal at the frequency f2, and a system A display data generation unit 24 that performs signal processing on the video signal according to the clock signal Sck; and a panel drive circuit 3 that generates a drive signal at a frequency f4 based on the display data Sd and supplies the drive signal to the PDP 4. The frequency variable circuit 5 determines at least the frequency f2 and the frequency f4 according to the detection result of the reception frequency f1. And it has a configuration to change either.

  With this configuration, at least one of the system clock signal Sck and the frequencies f2 and f4 of the drive signal is changed based on the reception frequency f1. For this reason, the influence on the image quality based on (a) electromagnetic waves generated due to the system clock generation circuit 23 and the drive clock generation circuit 32 at the time of generating the clock signal and (b) electromagnetic waves generated due to the PDP 4 is suppressed. As a result, the video quality can be dramatically improved.

  Further, according to the display device DIS according to the present embodiment, at least one of the frequencies f2 and f4 is changed to a frequency that does not affect the reception of the broadcast wave, and a harmonic component (an integer of the frequencies f2 and f3) is further changed. (Double frequency) is also changed so as to be different from the reception frequency f1, so that it is possible to further improve the video quality.

  Furthermore, according to the display device DIS according to the present embodiment, since the configuration of varying the waveforms of the sustain pulses IPy and IPx is adopted as a countermeasure against unwanted radiation generated from the PDP 4, the generation of electromagnetic waves itself is suppressed. In addition, it is possible to theoretically completely remove the deterioration of the image quality due to the predetermined frequency component included in the electromagnetic wave generated from the PDP 4.

  In the above embodiment, the method of reducing the influence of electromagnetic waves due to unnecessary radiation in the display device DIS on which the PDP 4 is mounted has been described as an example. For example, a matrix type display panel such as a liquid crystal panel or an organic EL panel is used. By adopting a similar method even in a display device equipped with, it is possible to reduce the influence of electromagnetic waves due to unnecessary radiation.

  In the above-described embodiment, (1) the configuration in which (2) the frequency f4 of the drive signal is also changed in addition to (1) the change in the frequency f2 of the system clock signal Sck and the frequency f3 of the drive clock signal Gck is employed. However, only one of the methods may be applied.

  Furthermore, in the above-described embodiment, the configuration in which the frequency of the drive clock signal Gck is made variable together with the frequency of the system clock signal Sck is adopted, but only one of them may be made variable.

  Furthermore, in the above-described embodiment, the method using the method 1 and the method 2 together is adopted. However, the method 1 is sufficient for the influence on the image quality caused by the electromagnetic wave generated in the PDP 4. Since it can be reduced, it is also possible to adopt only the above method 1.

  Furthermore, in the above embodiment, a method of fixing the frequencies f2 and f3 to a frequency different from the reception frequency f1 is adopted. However, as described above, these frequencies f2 and f3 are changed over time at predetermined time intervals. The frequency f2 may be sequentially changed (that is, the frequency f2 may be varied for each predetermined number of clocks). In this case, it is possible to input a predetermined random number to the modulation circuit and vary the modulation frequency in the modulation circuit (however, this random number is varied by a control signal from the frequency variable circuit 5, It is assumed that the modulation frequency is set so as to exclude the relationship of frequency f2≈f1). Since this method is the same as the method disclosed in Japanese Patent Laid-Open No. 2000-338932 described above, details are omitted.

  In the above embodiment, in the above embodiment, an application pattern is stored for each reception frequency f1 in the management table TBL, and the application time t1 of the signals GT1 to GT4 (GT11 to GT44) using the application pattern. The structure which sets -t4 was employ | adopted. However, when the installation area of the display device DIS is specified, the reception frequency f1 of the channel that can be received in the area can be grasped in advance, so that all these reception frequencies f1 and frequency tf4 do not coincide with each other. An application pattern may be set in advance.

  Furthermore, in the above embodiment, the method of previously programming the application pattern in the drive control unit 33 has been described. However, a circuit corresponding to each application pattern is provided in the drive control unit 33, and according to the reception frequency f1, The circuit may be switched.

  Furthermore, in the above-described embodiment, the configuration in which only the pulse waveforms of the sustain pulses IPy and IPx are changed, but the waveform of the scan pulse SP and the pixel data pulse DPj may be changed.

It is a block diagram which shows the structure of the display apparatus DIS in 1st Embodiment. It is a figure which shows the circuit structure of the drive part 34 in the embodiment. It is a figure which shows an example of the recording content of the management table TBL in the same embodiment. (A) is a timing chart showing the relationship between a sustain pulse used in the display device DIS according to the present embodiment and the signals GT1 to GT4 necessary for generating the sustain pulse, and (b) It is the timing chart which showed the relationship between the sustain pulse used in the conventional display apparatus, and the signals GT01-GT04 used in order to produce | generate the said sustain pulse. It is a timing chart which shows the drive sequence performed in the drive part 34 of the embodiment.

Explanation of symbols

DIS ... Display device 1 ... Tuner 2 ... Video processing circuit 3 ... Panel drive circuit 4 ... PDP
5 ... Frequency variable part

Claims (5)

A display control device for displaying various images on a matrix type display panel in which a plurality of pixels are arranged on a matrix,
Receiving means for receiving the broadcast video signal;
Detecting means for detecting the frequency of the received video signal as a first frequency;
Reference clock generation means for generating a reference clock signal as a reference for signal processing at the second frequency;
Processing means for performing signal processing on the video signal according to the reference clock signal;
Display panel driving means for generating a driving signal for driving the display panel using the video signal after the signal processing at a third frequency, and supplying the driving signal to the display panel;
Control means for changing at least one of the second frequency and the third frequency according to a detection result of the first frequency in the detection means ,
The display control device, wherein the display panel driving unit changes a waveform of the drive signal supplied to the display panel based on the first frequency . The display panel driving means includes
Control signal generating means for generating a control signal composed of a plurality of signal components;
Drive signal generation means for generating the drive signal based on the control signal,
The control signal generation means varies the output time of each signal component included in the control signal based on the detected first frequency,
The drive signal generation unit varies the rise time and fall time of the voltage value of the drive signal according to the input time of the signal component included in the control signal . Display control device. The display control apparatus according to claim 1, wherein the display panel driving unit changes a waveform of the driving signal without changing an energy value of the driving signal . A display control device according to any one of claims 1 to 3,
A matrix type display panel in which a plurality of pixels are arranged on a matrix;
Table 示装 location, characterized in that it comprises a. A display control method in a display control device for displaying various videos corresponding to a broadcast video signal on a matrix type display panel in which a plurality of pixels are arranged on a matrix,
A first step of detecting the frequency of the video signal received by the receiving means mounted on the display control device as a first frequency;
At least one of a second frequency for generating a reference clock signal serving as a reference for the signal processing and a third frequency for generating a drive signal for driving the display panel using the video signal, A second step for changing based on the detected first frequency;
A third step of generating the reference clock signal at the changed second frequency;
A fourth step of performing signal processing on the video signal according to the reference clock signal;
Generating a drive signal for driving the display panel using the video signal after the signal processing at the changed third frequency, and changing a waveform of the drive signal based on the first frequency; A fifth step of supplying the drive signal to the display panel;
Display control method, characterized in that it comprises a.

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