JP2001134233A - Driving circuit and display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a driving circuit and a display device capable of suppressing the unwanted radiation of electromagnetic waves to be generated from a part which does not contribute to discharge of a driving pulse. SOLUTION: A current limiting element IL is connected to the gate of a transistor Q2 and the current of a control signal S2 which is to be inputted to the gate of the transistor Q2 is limited by the element IL. At this time, electric charges for forming the channel of the transistor are gradually charged via the gate and the opening speed of the channel of the transistor becomes slow and a sustainging pulse Psu falls down gradually to the ground potential.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit for outputting a driving pulse for discharging a discharge cell, and a display device using the driving circuit.

[0002]

2. Description of the Related Art As a conventional driving circuit for driving a discharge cell, for example, a sustain driver for driving a sustain electrode of a plasma display panel is known.

FIG. 5 is a circuit diagram showing a configuration of a conventional sustain driver. As shown in FIG. 5, the sustain driver 400 includes a recovery capacitor C11, a recovery coil L
11, switches SW11, SW12, SW21, SW2
2 and diodes D11 and D12.

The switch SW11 is connected between the power supply terminal V4 and the node N11, and the switch SW12 is connected between the node N11 and the ground terminal. The voltage Vsus is applied to the power supply terminal V4. Node N11
Is connected to, for example, 480 sustain electrodes, and FIG.
Shows a panel capacitance Cp corresponding to the total capacitance between the plurality of sustain electrodes and the ground terminal.

[0005] The recovery capacitor C11 is connected between the node N13 and a ground terminal. Switch SW21 and diode D are connected between nodes N13 and N12.
11 are connected in series, and a diode D12 and a switch SW22 are connected in series between the node N12 and the node N13. The recovery coil L11 is connected to the node N12.
And the node N11.

FIG. 6 shows the sustain driver 400 of FIG.
FIG. 9 is a timing chart showing an operation in a sustain period of FIG. FIG. 6 shows the voltage of the node N11 and the switch SW2 in FIG.
1, the operations of SW11, SW22, and SW12 are shown.

First, in the period Ta, the switch SW2
1 turns on and the switch SW12 turns off. At this time,
Switches SW11 and SW22 are off. Thereby, the LC by the recovery coil L11 and the panel capacity Cp
Due to the resonance, the voltage of the node N11 gradually rises.
Next, in a period Tb, the switch SW21 is turned off,
The switch SW11 turns on. Thereby, the node N1
1, the voltage of the node N11 is fixed at Vsus during the period Tc, and a sustain discharge occurs.

Next, in a period Td, the switch SW11 turns off and the switch SW22 turns on. As a result, the voltage of the node N11 gradually drops due to LC resonance caused by the recovery coil L11 and the panel capacitance Cp. Thereafter, in the period Te, the switch SW22 is turned off and the switch SW12 is turned on. Thereby, the node N11
Voltage drops sharply and is fixed at the ground potential. By repeating the above operation in the sustain period, a periodic sustain pulse Psu is applied to the plurality of sustain electrodes, and the discharge cells are discharged when the sustain pulse Psu rises, so that sustain discharge is performed.

[0009]

As described above, the rising portion and the falling portion of the sustain pulse Psu are
It is composed of an LC resonance section in the periods Ta and Td by the operation of the switch SW21 or the switch SW22, and edge portions e1 and e2 in the periods Tb and Te by the on operation of the switch SW11 or the switch SW12.

[0010] Of the above-mentioned edge portions, the edge portion e1 needs to cause a sustain discharge in the discharge cell during this period, and therefore needs to rise to some extent steeply. However, the edge portion e2 is directly involved in the discharge phenomenon. No need to steeply fall. However, in the conventional sustain pulse,
Since the edge portion e2 is also changed steeply, unnecessary electromagnetic wave radiation is generated by the edge portion e2.
Since the radiation of such unnecessary electromagnetic waves may adversely affect other electronic devices, it is desired to suppress the radiation of the unnecessary electromagnetic waves.

An object of the present invention is to provide a drive circuit capable of suppressing unnecessary electromagnetic wave radiation generated from a portion that does not contribute to discharge of a drive pulse, and a display device using the drive circuit. .

[0012]

Means for Solving the Problems (1) First invention A drive circuit according to a first invention is a drive circuit which alternately alternates between a first potential and a second potential to discharge a discharge cell. A drive circuit for outputting a pulse, wherein the first drive circuit changes a drive pulse to a first potential in order to discharge a discharge cell.
And a second transition means for transitioning the drive pulse to the second potential more gently than the transition to the first potential by the first transition means.

The drive circuit according to the present invention discharges the discharge cells when the drive pulse transitions to the first potential, and switches to the first potential when the discharge cell transitions to the second potential at which the discharge cells do not discharge. The drive pulse transitions to the second potential more gently than the transition. Therefore, a steep edge portion is not formed at the time of transition to the second potential, so that unnecessary electromagnetic wave radiation generated from a portion that does not contribute to the discharge of the driving pulse can be suppressed.

(2) Second invention In a drive circuit according to a second invention, in the configuration of the drive circuit according to the first invention, the second transition means drives the discharge cell before the next discharge is performed. The pulse changes to the second potential.

In this case, since the drive pulse transitions to the second potential before the discharge cell performs the next discharge, the drive pulse is changed to the second potential without affecting the next discharge of the discharge cell. The transition can be made gently.

(3) Third invention In a driving circuit according to a third invention, in the configuration of the driving circuit according to the first or second invention, the second transition means receives a second potential at one end. The semiconductor device includes a field-effect transistor and a current limiting element that limits a current of a control signal input to a gate of the field-effect transistor.

In this case, when the on / off state of the field-effect transistor is controlled in order to cause the drive pulse to transition to the second potential, the current of the control signal input to its gate is limited. Charge for forming the channel of the field effect transistor is slowly charged and discharged through the gate. Therefore, the opening and closing speed of the channel of the field-effect transistor is reduced, and the drive pulse can be gently shifted to the second potential.

(4) Fourth Invention In a drive circuit according to a fourth invention, in the configuration of the drive circuit according to any one of the first to third inventions, the discharge cell includes a capacitive load, and one end is provided. The inductance element connected to the capacitive load, and the L between the capacitive load and the inductance element
Third transition means for transitioning the drive pulse from the second potential to a third potential between the first potential and the second potential by C resonance, and driving by LC resonance between the capacitive load and the inductance element And a fourth transition unit that transitions the pulse from the first potential to a fourth potential between the first potential and the second potential, wherein the first transition unit converts the drive pulse to a third potential. The transition from the potential to the first potential and the second transition means transition the drive pulse from the fourth potential to the second potential.

In this case, the drive pulse is shifted from the second potential to the third potential by the LC resonance between the capacitive load and the inductance element.
After the transition to the third potential, the transition from the third potential to the first potential to discharge the discharge cells. Thereafter, the driving pulse is applied to the first pulse by LC resonance between the capacitive load and the inductance element.
After the transition from the fourth potential to the fourth potential, the transition from the fourth potential to the second potential is gradual. As described above, since the transition from the second potential to the third potential and the transition from the first potential to the fourth potential are performed by LC resonance,
In this period, charge can be released and collected to the discharge cells, and power consumption can be reduced. In addition, since the transition from the second potential to the third potential and the transition from the first potential to the fourth potential are performed gently by LC resonance, unnecessary radiation of electromagnetic waves is suppressed even during this period. be able to.

(5) Fifth Invention In a drive circuit according to a fifth invention, in the configuration of the drive circuit according to any one of the first to fourth inventions, the discharge cell includes a scan electrode and / or a discharge electrode of a plasma display panel. Alternatively, the driving pulse includes a sustain electrode, and the driving pulse includes a sustain pulse applied to the scan electrode and / or the sustain electrode during the sustain period.

In this case, during the sustain period, a sustain pulse is applied to the sustain electrode and / or the scan electrode of the plasma display panel to suppress unnecessary electromagnetic wave radiation generated from a portion that does not contribute to the discharge of the sustain pulse. it can.

(6) Sixth Invention A display device according to a sixth invention comprises a display panel including a discharge cell having a plurality of electrodes as a capacitive load, and first to first driving a plurality of electrodes of the display panel. And a drive circuit according to any one of the fifth aspects of the invention.

In the display device according to the present invention, even if a plurality of electrodes of the display panel are driven, the radiation of the unnecessary electromagnetic wave generated from the drive circuit is suppressed, so that the unnecessary electromagnetic wave generated from the display device is suppressed. Radiation can be suppressed.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A sustain driver used in a plasma display device will be described below as an example of a drive circuit according to the present invention. The drive circuit of the present invention can be similarly applied to other devices as long as they drive discharge cells. When the driving circuit of the present invention is used for a plasma display panel,
Type, DC type, etc., and can be applied to any of the address electrode, sustain electrode, and scan electrode drive circuits, but is suitably used for the sustain electrode and scan electrode drive circuits. be able to.

FIG. 1 is a block diagram showing a configuration of a plasma display device using a sustain driver according to an embodiment of the present invention.

The plasma display device shown in FIG.
P (plasma display panel) 1, data driver 2, scan driver 3, multiple scan driver ICs
(Circuit) 3a and a sustain driver 4 are included.

The PDP 1 includes a plurality of address electrodes (data electrodes) 11, a plurality of scan electrodes (scan electrodes) 12, and a plurality of sustain electrodes (sustain electrodes) 13. The plurality of address electrodes 11 are arranged in the vertical direction of the screen, and include a plurality of scan electrodes 12 and a plurality of sustain electrodes 13.
Are arranged in the horizontal direction of the screen. The plurality of sustain electrodes 13 are commonly connected. Address electrode 11, scan electrode 12, and sustain electrode 13
Are formed at each intersection, and each discharge cell forms a pixel on the screen.

The data driver 2 is connected to a plurality of address electrodes 11 of the PDP 1. The plurality of scan driver ICs 3a are connected to the scan driver 3. The plurality of scan electrodes 12 of the PDP 1 are connected to each scan driver IC 3a. The sustain driver 4 is connected to a plurality of sustain electrodes 13 of the PDP 1.

The data driver 2 applies a write pulse to a corresponding address electrode 11 of the PDP 1 according to image data during a write period. The plurality of scan driver ICs 3a are driven by the scan driver 3, and shift the shift pulse SH in the vertical scanning direction during the writing period while the plurality of scan electrodes 1 of the PDP 1 are arranged.
2 are sequentially applied with a write pulse. Thereby, an address discharge is performed in the corresponding discharge cell.

Further, a plurality of scan driver ICs 3a
In the sustain period, a periodic sustain pulse is applied to PDP1.
To the plurality of scan electrodes 12. On the other hand, the sustain driver 4 simultaneously applies a sustain pulse 180 ° out of phase with respect to the sustain pulse of the scan electrode 12 to the plurality of sustain electrodes 13 of the PDP 1 during the sustain period. As a result, sustain discharge is performed in the corresponding discharge cell.

FIG. 2 is a timing chart showing an example of the drive voltage of scan electrode 12 and sustain electrode 13 in PDP 1 of FIG.

During the initialization and writing periods, an initial setup pulse Pset is applied to a plurality of scan electrodes 12 simultaneously. Thereafter, the write pulse Pw is sequentially applied to the plurality of scan electrodes 12. Thereby, PD
An address discharge occurs in the discharge cell corresponding to P1.

Next, in the sustain period, the sustain pulse Psc is periodically applied to the plurality of scan electrodes 12, and the sustain pulse Psu is periodically applied to the plurality of sustain electrodes 13. The phase of the sustain pulse Psu is
The phase is shifted by 180 ° with respect to the phase of c. Thus, a sustain discharge occurs following the address discharge.

Next, the sustain driver 4 shown in FIG. 1 will be described. FIG. 3 is a circuit diagram showing a configuration of the sustain driver 4 shown in FIG.

The sustain driver 4 shown in FIG. 3 includes n-channel type FETs (field effect transistors, hereinafter referred to as transistors) Q1 to Q4 as switching elements, a recovery capacitor C1, a recovery coil L, and diodes D1 and D2.
And a current limiting element IL.

One end of the transistor Q1 is connected to the power terminal V1.
, The other end is connected to the node N1, and the control signal S1 is input to the gate. The power supply terminal V1 has a voltage V
sus is applied. Transistor Q2 has one end connected to node N1 and the other end connected to a ground terminal. The current limiting element IL is composed of, for example, a resistor having a predetermined resistance value. One end of the current limiting element IL receives the control signal S2, and the other end is connected to the gate of the transistor Q2.

The recovery capacitor C1 is connected between the node N3 and the ground terminal. Transistor Q3 and diode D1 are connected in series between nodes N3 and N2. Diode D2 and transistor Q4 are connected in series between nodes N2 and N3. The control signal S3 is input to the gate of the transistor Q3, and the control signal S4 is input to the gate of the transistor Q4. The recovery coil L is connected between the node N2 and the node N1.

In this embodiment, the transistor Q1 and the power supply terminal V1 correspond to a first transition means, and the current limiting element IL, the transistor Q2 and the ground terminal correspond to a second transition means. The recovery coil L corresponds to an inductance element, and includes a recovery capacitor C1, a transistor Q3
And the diode D1 correspond to the third transition means, and include the recovery capacitor C1, the transistor Q4, and the diode D1.
2 corresponds to a fourth transition unit.

FIG. 4 shows the sustain driver 4 shown in FIG.
FIG. 9 is a timing chart showing an operation in a sustain period of FIG. FIG. 4 shows the voltage at the node N1 and the transistors Q1 to Q4 in FIG.
Signals S1 to S4 input to the scan driver I
The sustain pulse Psc output from C3a and the current I flowing in the discharge cell are shown.

First, in the period TA, the control signal S2 goes low to turn off the transistor Q2, and the control signal S3 goes high to turn on the transistor Q3.
At this time, the control signal S1 is at a low level and the transistor Q1 is off, and the control signal S4 is at a low level and the transistor Q4 is off. Therefore, the recovery capacitor C1 is connected to the recovery coil L via the transistor Q3 and the diode D1, and the voltage of the node N1 rises smoothly due to LC resonance caused by the recovery coil L and the panel capacitance Cp. At this time, the charge of the recovery capacitor C1 is released to the panel capacitance Cp via the transistor Q3, the diode D1, and the recovery coil L. Therefore, a recovery current as shown flows as the current I of the discharge cell.

Next, in a period TB, the control signal S1 goes high, turning on the transistor Q1, the control signal S3 goes low, and the transistor Q3 turns off.
Therefore, the node N1 is connected to the power supply terminal V1, and the voltage of the node N1 rises rapidly and is fixed at Vsus. At this time, the sustain discharge of the discharge cell is started, and a discharge current D1 as shown flows as the current I of the discharge cell.

Next, in the period TC, the control signal S1 goes low, the transistor Q1 turns off, the control signal S4 goes high, and the transistor Q4 turns on.
Therefore, the recovery capacitor C1 is connected to the recovery coil L via the diode D2 and the transistor Q4,
Due to the LC resonance caused by the recovery coil L and the panel capacitance Cp, the voltage of the node N1 gradually drops. At this time,
The charge stored in panel capacitance Cp is stored in recovery capacitor C1 via recovery coil L, diode D2 and transistor Q4. Therefore, a negative-polarity recovery current as shown flows as the current I of the discharge cell.

Next, in the period TD, the control signal S2 goes high, turning on the transistor Q2, the control signal S4 goes low, and the transistor Q4 turns off.
At this time, the current of the control signal S2 is limited by the current limiting element IL, and the charge for forming the channel of the transistor Q2 is gradually charged via the gate. Accordingly, the opening speed of the channel of the transistor Q2 is reduced, and the voltage of the node N1 gradually drops over a longer period than the rise in the period TB, and reaches the ground potential before the next discharge cell performs the next discharge. Fixed to ground potential.

More specifically, the timing when the sustain pulse Psu becomes the ground potential during the period TD is determined by the scan electrode 1
2, the discharge cell is discharged by the sustain pulse Psc, and as a current I of the discharge cell, as shown in FIG.
2 is set before it starts flowing. Therefore, the next sustain discharge operation by the sustain pulse Psc to the scan electrode 12 is not affected.

The control signal S by the current limiting element IL
For the reason described below, the current limit of the transistor 2 is 2.5 times as long as the fall time (100 → 10%) of the transistor Q2 does not limit the current, that is, the rise time (0 → 90%) of the transistor Q1. It is set to be above.

That is, the drain of the transistor Q1
Assuming that the resistance between the sources is R and the capacitance of the panel capacitance Cp is C, the transistor Q1 is connected to the panel capacitance Cp in the period TB.
Is connected in series to form an RC circuit (integrating circuit), and its gain A is represented by the following equation when the frequency is f.

A = 1 / ｛1+ (2πf · RC) ² ｝ ^1/2 Therefore, when f >> 1 / (2πRC · C), A ≒ 1 / (2πf · RC) .

As described above, the gain A is inversely proportional to the time constant RC, and the gain A can be reduced by increasing the rise time. Further, this gain A is equal to the period T
It is considered that the radiation level becomes substantially equal to the radiation level of the electromagnetic wave generated when the sustain pulse Psu is raised to the voltage Vsus in B. Therefore, by increasing the rise time, the radiation level of the electromagnetic wave generated when the voltage rises to the voltage Vsus can be reduced. This also applies in the period TD,
By increasing the fall time, it is possible to reduce the radiation level of electromagnetic waves generated when falling to the ground potential.

For example, the radiation level of the electromagnetic wave generated at the time of rising to the voltage Vsus in the period TB is set to 40
Assuming that the level is dB, the radiation level of the electromagnetic wave generated when the sustain pulse Psu falls to the ground potential in the period TD in the same time is also 40 dB. The sum of the radiation levels of these electromagnetic waves doubles, and the radiation level of the electromagnetic waves is increased by 6 dB.

Therefore, the combined radiation level is 3d
B, the radiation level of the electromagnetic wave generated at the time of the fall to the ground potential in the period TD is set to 8d.
What is necessary is just to reduce only B. Therefore, by making the fall time (100 → 10%) of the period TD 2.5 times or more the rise time (0 → 90%) in the period TB, the entire radiation level can be reduced by 3 dB. Thus, adverse effects on other electronic devices can be suppressed.

By repeating the above operation in the sustain period, the sustain pulse Psu having the above waveform is applied to the plurality of sustain electrodes 13 periodically. As described above, in the present embodiment, the fall time to the ground potential in the period TD during which the discharge cell does not perform the sustain discharge by the sustain pulse Psu is longer than the rise time to the voltage Vsus in the period TB. Therefore, sustain pulse Psu gradually falls to the ground potential, and no sharp edge portion is formed in period TD.
Unwanted electromagnetic wave radiation generated from a portion that does not contribute to the sustain discharge of u can be suppressed.

The scan driver IC 3a has the same configuration as the sustain driver 4 described above, and the sustain pulse P
A current limiting element similar to the above is connected to the gate of the transistor that lowers sc to the ground potential. As shown in FIG. 4, the sustaining pulse having the same waveform as the sustaining pulse Psu to the sustain electrode and having a 180 ° phase shift is maintained. The pulse Psc is applied to the scan electrode 12 periodically. Accordingly, similarly to the above, the sustain pulse Psc also gradually falls to the ground potential, no sharp edge is formed, and unnecessary electromagnetic wave radiation generated from a portion that does not contribute to the sustain discharge of the sustain pulse Psc is generated. Is also suppressed.

In this embodiment, the case where the discharge cell discharges when the sustain pulse rises has been described. However, when the discharge cell discharges when the sustain pulse falls, the sustain pulse is shifted to the higher potential side. F for transition
In the example shown in FIG. 3, the current limiting element is connected to the gate of the transistor Q1, so that the same effect as described above can be obtained even when discharging is performed at the time of falling.

In this embodiment, the sustain pulse Psu is gradually lowered to the ground potential by limiting the current of the control signal inputted to the gate of the FET.
The fall time to the ground potential may be lengthened by increasing the time constant by increasing the resistance value of the ET itself.

[0055]

According to the present invention, since the drive pulse transitions to the second potential more gently than the transition to the first potential, a sharp edge portion is formed at the time of transition to the second potential. Therefore, the radiation of unnecessary electromagnetic waves generated from the portion that does not contribute to the discharge of the driving pulse can be suppressed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a plasma display device using a sustain driver according to an embodiment of the present invention.

FIG. 2 is a timing chart showing an example of a drive voltage of a scan electrode and a sustain electrode in the PDP shown in FIG.

FIG. 3 is a circuit diagram showing a configuration of the sustain driver shown in FIG. 1 according to one embodiment of the present invention;

FIG. 4 is a timing chart showing an operation of the sustain driver shown in FIG. 3 during a sustain period;

FIG. 5 is a circuit diagram showing a configuration of a conventional sustain driver.

FIG. 6 is a timing chart showing an operation of the sustain driver during a sustain period shown in FIG. 5;

[Explanation of symbols]

 Reference Signs List 1 PDP 2 Data driver 3 Scan driver 3a Scan driver IC 4 Sustain driver 11 Address electrode 12 Scan electrode 13 Sustain electrode C1 Recovery capacitor L Recovery coil Q1-Q4 Field effect transistor IL Current limiting element

Claims (6)

[Claims] 1. A drive circuit for outputting a drive pulse that alternates between a first potential and a second potential in order to discharge a discharge cell, wherein the drive pulse is used to discharge the discharge cell. A first transition means for transiting to the first potential; and a second transition means for transiting the drive pulse to the second potential more gently than the transition to the first potential by the first transition means.
And a transition means. 2. The drive circuit according to claim 1, wherein said second transition means transitions said drive pulse to said second potential before said discharge cell performs a next discharge. 3. The second transition means includes: a field-effect transistor receiving the second potential at one end; a current-limiting element that limits a current of a control signal input to a gate of the field-effect transistor. 3. The driving circuit according to claim 1, further comprising: 4. The discharge cell includes a capacitive load, an inductance element having one end connected to the capacitive load, and the drive pulse being supplied to the second cell by LC resonance between the capacitive load and the inductance element. A third transition means for transitioning from the potential of the first potential to the third potential between the first potential and the second potential, and the driving pulse is generated by LC resonance of the capacitive load and the inductance element. And a fourth transition unit that transitions from a first potential to a fourth potential between the first potential and the second potential, wherein the first transition unit transmits the drive pulse to the first potential. 4. A transition from a third potential to the first potential, and the second transition means transitions the drive pulse from the fourth potential to the second potential. Drive according to any of the above Road. 5. The discharge cell includes a scan electrode and / or a sustain electrode of a plasma display panel, and the driving pulse includes a sustain pulse applied to the scan electrode and / or the sustain electrode during a sustain period. The drive circuit according to any one of claims 1 to 4, wherein: 6. A display panel including a discharge cell having a plurality of electrodes as a capacitive load, and driving the plurality of electrodes of the display panel.
5. A display device comprising: the driving circuit according to any one of 5.