JP4116301B2 - Plasma display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a drive circuit for driving a capacitive load by a drive pulse.Plasma display device usingIt is about.
[0002]
[Prior art]
As a conventional driving circuit for driving a capacitive load, for example, a sustain driver for driving a sustain electrode of a plasma display panel is known.
[0003]
FIG. 13 is a circuit diagram showing a configuration of a conventional sustain driver. As shown in FIG. 13, the sustain driver 400 includes a recovery capacitor C11, a recovery coil L11, switches SW11, SW12, SW21, SW22, and diodes D11, D12.
[0004]
The switch SW11 is connected between the power supply terminal V4 and the node N11, and the switch SW12 is connected between the node N11 and the ground terminal. The voltage Vsus is applied to the power supply terminal V4. The node N11 is connected to, for example, 480 sustain electrodes, and FIG. 13 shows a panel capacitance Cp corresponding to the total capacitance between the plurality of sustain electrodes and the ground terminal.
[0005]
The recovery capacitor C11 is connected between the node N13 and the ground terminal. A switch SW21 and a diode D11 are connected in series between the node N13 and the node N12, and a diode D12 and a switch SW22 are connected in series between the node N12 and the node N13. The recovery coil L11 is connected between the node N12 and the node N11.
[0006]
FIG. 14 is a timing chart showing the operation of the sustain driver 400 of FIG. 13 during the sustain period. FIG. 14 shows the voltage at the node N11 and the operations of the switches SW21, SW11, SW22, and SW12 in FIG.
[0007]
First, in the period Ta, the switch SW21 is turned on and the switch SW12 is turned off. At this time, the switches SW11 and SW22 are off. As a result, the voltage at the node N11 gradually rises due to LC resonance caused by the recovery coil L11 and the panel capacitance Cp. Next, in the period Tb, the switch SW21 is turned off and the switch SW11 is turned on. As a result, the voltage at the node N11 rapidly increases, and the voltage at the node N11 is fixed to Vsus in the period Tc.
[0008]
Next, in the period Td, the switch SW11 is turned off and the switch SW22 is turned on. As a result, the voltage at the node N11 gradually drops due to LC resonance caused by the recovery coil L11 and the panel capacitance Cp. Thereafter, in the period Te, the switch SW22 is turned off and the switch SW12 is turned on. As a result, the voltage at the node N11 drops rapidly and is fixed to the ground potential. By repeating the above operation in the sustain period, the periodic sustain pulse Psu is applied to the plurality of sustain electrodes.
[0009]
As described above, the rising part and the falling part of the sustain pulse Psu are the LC resonance part of the periods Ta and Td due to the operation of the switch SW21 or the switch SW22 and the edge part of the periods Tb and Te due to the ON operation of the switch SW11 or the switch SW12. e1 and e2.
[0010]
[Problems to be solved by the invention]
The switches SW11, SW12, SW21, and SW22 are usually constituted by FETs (field effect transistors) that are switching elements. Each FET has a capacitance between the drain and the source as a parasitic capacitance, and is connected to each FET. This wiring has an inductance component. For this reason, when the switch SW11 and the like change from off to on, LC resonance occurs due to the capacitance between the drain and the source and the inductance component of the wiring, and unnecessary electromagnetic waves are radiated by this LC resonance.
[0011]
Also, each of the diodes D11 and D12 has a capacitance between the anode and the cathode as a parasitic capacitance, and wiring connected to each diode also has an inductance component. For this reason, when the switch SW11 and the like change from OFF to ON, LC resonance occurs due to the capacitance between the anode and the cathode and the inductance component of the wiring, and unnecessary electromagnetic waves are radiated by the LC resonance.
[0012]
Further, since the capacitance between the drain and source of each FET and the capacitance between the anode and cathode of each diode and the inductance component of each wiring are small, the resonance frequency of the LC resonance is increased and the frequency of the generated electromagnetic wave is also increased. On the other hand, in the standard of unnecessary radiation by the Electrical Appliance and Material Control Law, a limit value for high-frequency electromagnetic waves of 30 MHz or more is defined. Therefore, since the radiation of such high frequency electromagnetic waves may adversely affect other electronic devices, it is desired to suppress the radiation of unnecessary high frequency electromagnetic waves.
[0013]
  An object of the present invention is to provide a drive circuit capable of suppressing radiation of unnecessary high-frequency electromagnetic waves.Plasma display device usingIs to provide.
[0014]
[Means for Solving the Problems]
  (1) First invention
  A plasma display apparatus according to a first invention isA recovery capacitor for supplying a charge to the capacitive load of the plasma display panel; first switching means connected to the first voltage source; and wiring means connected between the first switching means and the plasma display. A first capacitive element connected in parallel to the first switching means and connecting the first voltage source and the wiring means; and a second switching means connected to the second voltage source and the wiring means. A second capacitive element connected in parallel to the second switching means, connecting the second voltage source and the wiring means, a third switching means connected to the recovery capacitor, and a third switching And an inductance element connected between the wiring means and the third switching means. By turning on the third switching means, the potential of the wiring means rises and starts to decrease from the peak voltage. After the, by turning on the first switching means, in which the potential of the wiring means is configured to the first voltage source potential.
[0015]
  In the plasma display device according to the present invention, the drive pulse can be raised or lowered by LC resonance between the inductance element and the capacitive load, and the capacitance of the plasma display panel can be obtained via the first switching means and the wiring means. The drive pulse is raised by supplying the potential of the first voltage source to the capacitive load, and the potential of the second voltage source is supplied to the capacitive load of the plasma display panel via the second switching means and the wiring means. As a result, the drive pulse can be lowered. In addition, since the charge can be recovered from the capacitive load by the recovery capacitor, the power consumption of the drive circuit can be reduced.
[0016]
In addition, a first capacitive element is connected to the first switching means, and a second capacitive element is connected to the second switching means. As a result, the capacitance in the LC resonance path is increased, and the resonance frequency of the LC resonance by the first and second switching means and the wiring means can be reduced, so that unnecessary high-frequency electromagnetic radiation can be suppressed. .
[0017]
(2) Second invention
  According to a second aspect of the present invention, there is provided a plasma display device comprising: a recovery capacitor for supplying a charge to a capacitive load of a plasma display panel; first switching means connected to a first voltage source; first switching means; Wiring means connected between the display, second switching means connected to the second voltage source and wiring means, third switching means connected to the recovery capacitor, and third switching means An inductance element connected between the wiring means and the third switching means, and a capacitive element connected in parallel to the recovery capacitor and the inductance element, and turning on the third switching means Thus, after the potential of the wiring means rises and starts to decrease from the peak voltage, the first switching means is turned on. The one in which the potential of the wiring means is configured to the first voltage source potential.
[0018]
In the plasma display device according to the present invention, the drive pulse can be raised or lowered by LC resonance between the inductance element and the capacitive load, and the capacitance of the plasma display panel can be obtained via the first switching means and the wiring means. The drive pulse is raised by supplying the potential of the first voltage source to the capacitive load, and the potential of the second voltage source is supplied to the capacitive load of the plasma display panel via the second switching means and the wiring means. As a result, the drive pulse can be lowered. In addition, since the charge can be recovered from the capacitive load by the recovery capacitor, the power consumption of the drive circuit can be reduced.
[0019]
A capacitive element is connected to the third switching means. As a result, the capacitance in the LC resonance path is increased, and the resonance frequency of the LC resonance by the first and second switching means and the wiring means can be reduced, so that unnecessary high-frequency electromagnetic radiation can be suppressed. .
[0044]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a sustain driver used in a plasma display apparatus will be described as an example of a drive circuit according to the present invention. The driving circuit of the present invention can be applied to other devices as long as it drives a capacitive load. For example, the driving circuit of a display device such as a plasma display panel, a liquid crystal display, or an electroluminescence display can be used. It can be applied to a drive circuit. In addition, when the driving circuit of the present invention is used for a plasma display panel, it can be applied to driving circuits for any plasma display panel such as an AC type or a DC type, and can be used for any driving circuit of address electrodes, sustain electrodes, and scan electrodes. Can also be applied, but it can be suitably used for a drive circuit for a sustain electrode and a scan electrode.
[0045]
FIG. 1 is a block diagram showing a configuration of a plasma display device using a sustain driver according to a first embodiment of the present invention.
[0046]
The plasma display apparatus of FIG. 1 includes a PDP (plasma display panel) 1, a data driver 2, a scan driver 3, a plurality of scan driver ICs (circuits) 3a, and a sustain driver 4.
[0047]
The PDP 1 includes a plurality of address electrodes (data electrodes) 11, a plurality of scan electrodes (scan electrodes) 12, and a plurality of sustain electrodes (sustain electrodes) 13. The plurality of address electrodes 11 are arranged in the vertical direction of the screen, and the plurality of scan electrodes 12 and the plurality of sustain electrodes 13 are arranged in the horizontal direction of the screen. The plurality of sustain electrodes 13 are connected in common. A discharge cell is formed at each intersection of the address electrode 11, the scan electrode 12, and the sustain electrode 13, and each discharge cell constitutes a pixel on the screen.
[0048]
The data driver 2 is connected to a plurality of address electrodes 11 of the PDP 1. The plurality of scan driver ICs 3 a are connected to the scan driver 3. A plurality of scan electrodes 12 of the PDP 1 are connected to each scan driver IC 3a. The sustain driver 4 is connected to the plurality of sustain electrodes 13 of the PDP 1.
[0049]
In the writing period, the data driver 2 applies a writing pulse to the corresponding address electrode 11 of the PDP 1 according to the image data. The plurality of scan driver ICs 3a are driven by the scan driver 3, and sequentially apply the write pulses to the plurality of scan electrodes 12 of the PDP 1 while shifting the shift pulse SH in the vertical scanning direction in the write period. As a result, address discharge is performed in the corresponding discharge cells.
[0050]
Further, the plurality of scan driver ICs 3a apply periodic sustain pulses to the plurality of scan electrodes 12 of the PDP 1 in the sustain period. On the other hand, in the sustain period, the sustain driver 4 simultaneously applies a sustain pulse that is 180 ° out of phase with the sustain pulse of the scan electrode 12 to the plurality of sustain electrodes 13 of the PDP 1. Thereby, a sustain discharge is performed in the corresponding discharge cell.
[0051]
FIG. 2 is a timing chart showing an example of drive voltages for the scan electrode 12 and the sustain electrode 13 in the PDP 1 of FIG.
[0052]
In the initialization and writing period, an initialization pulse (setup pulse) Pset is simultaneously applied to the plurality of scan electrodes 12. Thereafter, the write pulse Pw is sequentially applied to the plurality of scan electrodes 12. As a result, address discharge occurs in the corresponding discharge cell of the PDP 1.
[0053]
Next, in the sustain period, the sustain pulse Psc is periodically applied to the plurality of scan electrodes 12, and the sustain pulse Psu is periodically applied to the plurality of sustain electrodes 13. The phase of sustain pulse Psu is shifted by 180 ° with respect to the phase of sustain pulse Psc. As a result, a sustain discharge occurs following the address discharge.
[0054]
Next, the sustain driver 4 shown in FIG. 1 will be described. FIG. 3 is a circuit diagram showing a configuration of the sustain driver 4 shown in FIG.
[0055]
The sustain driver 4 in FIG. 3 includes n-channel FETs (field effect transistors, hereinafter referred to as transistors) Q1 to Q4 which are switching elements, capacitors C1 and C2, a recovery capacitor Cr, a recovery coil L, and diodes D1 and D2. Including.
[0056]
The transistor Q1 has one end connected to the power supply terminal V1, the other end connected to the node N1 via the wiring L1, and the gate to which the control signal S1 is input. The transistor Q1 has a drain-source capacitance CP1 as a parasitic capacitance, and a capacitor C1 is connected in parallel between the drain and source of the transistor Q1. A voltage Vsus is applied to the power supply terminal V1.
[0057]
The transistor Q2 has one end connected to the node N1 through the wiring L2, the other end connected to the ground terminal, and the gate to which the control signal S2 is input. The transistor Q2 has a drain-source capacitance CP2 as a parasitic capacitance, and a capacitor C2 is connected in parallel between the drain and source of the transistor Q2.
[0058]
The node N1 is connected to, for example, 480 sustain electrodes 13, but FIG. 3 shows a panel capacitance Cp corresponding to the total capacitance between the plurality of sustain electrodes 13 and the ground terminal.
[0059]
The recovery capacitor Cr is connected between the node N3 and the ground terminal. Transistor Q3 and diode D1 are connected in series between nodes N3 and N2. Diode D2 and transistor Q4 are connected in series between nodes N2 and N3. The control signal S3 is input to the gate of the transistor Q3, and the control signal S4 is input to the gate of the transistor Q4. The recovery coil L is connected between the node N2 and the node N1.
[0060]
In the present embodiment, transistors Q1 and Q2 correspond to electrical elements, switching means and sustain pulse switching means, wirings L1 and L2 correspond to wiring means, capacitors C1 and C2 correspond to frequency reduction means, The terminal V1 and the ground terminal correspond to a voltage source. The transistor Q1 corresponds to the first switching means, the transistor Q2 corresponds to the second switching means, the wiring L1 corresponds to the first wiring means, the wiring L2 corresponds to the second wiring means, The capacitor C1 corresponds to the first capacitive element, the capacitor C2 corresponds to the second capacitive element, the power supply terminal V1 corresponds to the first voltage source, and the ground terminal corresponds to the second voltage source. .
[0061]
Next, the operation during the sustain period of the sustain driver 4 configured as described above will be described.
[0062]
First, the control signal S2 goes low and the transistor Q2 turns off, and the control signal S3 goes high and the transistor Q3 turns on. At this time, the control signal S1 is at a low level and the transistor Q1 is turned off, and the control signal S4 is at a low level and the transistor Q4 is turned off. Therefore, the recovery capacitor Cr is connected to the recovery coil L via the transistor Q3 and the diode D1, and the voltage at the node N1 rises smoothly due to LC resonance caused by the recovery coil L and the panel capacitance Cp. At this time, the charge of the recovery capacitor Cr is discharged to the panel capacitor Cp through the transistor Q3, the diode D1, and the recovery coil L.
[0063]
At this time, the current flowing through the transistor Q3, the diode D1, and the recovery coil L not only flows into the panel capacitance Cp, but also flows through the drain-source capacitance CP1 and the capacitor C1 of the transistor Q1 via the wiring L1. While flowing, it also flows to the capacitor CP2 between the drain and source of the transistor Q2 and the capacitor C2 via the wiring L2. Therefore, LC resonance occurs due to the inductance components of the wirings L1 and L2, the capacitances CP1 and CP2 between the drains and sources of the transistors Q1 and Q2, and the capacitors C1 and C2.
[0064]
However, in the present embodiment, the capacitance that contributes to the LC resonance is a capacitance obtained by adding the drain-source capacitances CP1 and CP2 and the capacitors C1 and C2, respectively. The resonance frequency is reduced only by the capacitors CP1 and CP2. Specifically, the capacitances of the capacitors C1 and C2 are set to, for example, about 5 to 10 with respect to the capacitances CP1 and CP2 between the drains and sources of the transistors Q1 and Q2 so that the resonance frequency of the LC resonance is less than 30 MHz. It is set to double.
[0065]
Here, as an example, the relationship between the drain-source capacitance and the drain-source voltage when a 2000 pF capacitor is connected in parallel between the FET drain-source will be described. FIG. 4 is a diagram showing the relationship between the drain-source capacitance Cds (pF) and the drain-source voltage Vds (V) when a 2000 pF capacitor is connected to the FET in parallel and when it is not connected. In FIG. 4, the case where a capacitor is not connected between the drain and source of the FET is indicated by a broken line, and the case where a capacitor of 2000 pF is connected in parallel is indicated by a solid line.
[0066]
As shown in FIG. 4, it can be seen that when a 2000 pF capacitor is connected in parallel between the drain and source of the FET, the capacitance Cds between the drain and source increases as compared to the case where the capacitor is not connected. In the case of this embodiment, since the drain-source voltage Vds of the transistors Q1 and Q2 shown in FIG. 3 is about 200 V, a capacitor of 2000 pF is connected in parallel between the drain and source of the transistors Q1 and Q2. Thus, it can be seen that the drain-source capacitance Cds of each of the transistors Q1 and Q2 increases by about 10 times compared to the case where no capacitor is connected.
[0067]
As described above, by connecting the capacitors C1 and C2 in parallel between the drains and sources of the transistors Q1 and Q2, the inductance component of the wirings L1 and L2 and the transistor generated when the transistor Q3 changes from off to on The resonance frequency of LC resonance by the drain-source capacitances CP1 and CP2 of Q1 and Q2 and the capacitors C1 and C2 is less than 30 MHz, and radiation of unnecessary electromagnetic waves of 30 MHz or more is suppressed.
[0068]
Next, the control signal S1 goes high and the transistor Q1 turns on, and the control signal S3 goes low and the transistor Q3 turns off. Therefore, the node N1 is connected to the power supply terminal V1, and the voltage of the node N1 rapidly rises and is fixed to the voltage Vsus.
[0069]
At this time, the current flowing from the power supply terminal V1 through the transistor Q1 flows not only into the panel capacitance Cp but also into the drain-source capacitance CP2 of the transistor Q2 and the capacitor C2 through the wirings L1 and L2. . Therefore, LC resonance occurs due to the inductance components of the wirings L1 and L2, the capacitance CP2 between the drain and source of the transistor Q2, and the capacitor C2.
[0070]
In this case as well, the capacitance contributing to this LC resonance is the sum of the drain-source capacitance CP2 and the capacitor C2, and thus occurs when the transistor Q1 changes from off to on. The resonance frequency of LC resonance by the inductance component of the wirings L1 and L2, the drain-source capacitance CP2 of the transistor Q2, and the capacitor C2 is less than 30 MHz, and radiation of unnecessary electromagnetic waves of 30 MHz or more is suppressed.
[0071]
Next, the control signal S1 goes low and the transistor Q1 turns off, and the control signal S4 goes high and the transistor Q4 turns on. Therefore, the recovery capacitor Cr is connected to the recovery coil L via the diode D2 and the transistor Q4, and the voltage at the node N1 gradually drops due to LC resonance caused by the recovery coil L and the panel capacitance Cp. At this time, the charge stored in the panel capacitor Cp is stored in the recovery capacitor Cr via the recovery coil L, the diode D2, and the transistor Q4, and the charge is recovered.
[0072]
At this time, the current flowing from the panel capacitor Cp not only flows into the recovery capacitor Cr via the recovery coil L, the diode D2 and the transistor Q4 but also drains / sources of the transistors Q1 and Q2 via the wirings L1 and L2. It also flows to the capacitors CP1 and CP2 between them and the capacitors C1 and C2. Therefore, LC resonance occurs due to the inductance components of the wirings L1 and L2, the capacitances CP1 and CP2 between the drains and sources of the transistors Q1 and Q2, and the capacitors C1 and C2.
[0073]
In this case as well, the capacitance contributing to this LC resonance is the sum of the drain-source capacitances CP1 and CP2 and the capacitors C1 and C2, respectively, so that the transistor Q4 is changed from off to on. The resonance frequency of LC resonance caused by the inductance components of the wirings L1 and L2 and the capacitances CP1 and CP2 between the drains and sources of the transistors Q1 and Q2 and the capacitors C1 and C2 is less than 30 MHz, and unnecessary electromagnetic waves of 30 MHz or more are generated. Radiation is suppressed.
[0074]
Next, the control signal S2 goes high and the transistor Q2 turns on, and the control signal S4 goes low and the transistor Q4 turns off. Therefore, the node N1 is connected to the ground terminal, and the voltage of the node N1 drops rapidly and is fixed to the ground potential.
[0075]
At this time, the current flowing to the ground terminal via the transistor Q2 flows not only from the panel capacitance Cp but also from the drain-source capacitance CP1 of the transistor Q1 and the capacitor C1 via the wirings L1 and L2. Therefore, LC resonance occurs due to the inductance components of the wirings L1 and L2, the drain-source capacitance CP1 of the transistor Q1, and the capacitor C1.
[0076]
Also in this case, as described above, the capacitance contributing to this LC resonance is the sum of the drain-source capacitance CP1 and the capacitor C1, and therefore occurs when the transistor Q2 changes from off to on. The resonance frequency of LC resonance by the inductance component of the wirings L1 and L2, the drain-source capacitance CP1 of the transistor Q1 and the capacitor C1 is also less than 30 MHz, and radiation of unnecessary electromagnetic waves of 30 MHz or more is suppressed.
[0077]
By repeatedly performing the above operation in the sustain period, sustain pulse Psu having a waveform similar to that of conventional sustain pulse Psu shown in FIG. 14 is periodically applied to the plurality of sustain electrodes 13 and unnecessary for 30 MHz or more. Electromagnetic radiation is suppressed.
[0078]
Next, the effect of reducing the radiation level of electromagnetic waves when the capacitors C1 and C2 are connected in parallel to the transistors Q1 and Q2 as described above will be described. FIG. 5 is a diagram showing the relationship between the radiation level of electromagnetic waves emitted from the plasma display device shown in FIG. 1 and the frequency. In FIG. 5, the case where the capacitors C1 and C2 are connected in parallel between the drains and sources of the transistors Q1 and Q2 is indicated by a solid line, and the case where the capacitors C1 and C2 are not connected is indicated by a broken line.
[0079]
As shown in FIG. 5, when the capacitors C1 and C2 are not connected, it can be seen that the radiation level of the electromagnetic wave takes a peak at a frequency f0 higher than 30 MHz, and the radiation level of the electromagnetic wave of 30 MHz or higher is high. On the other hand, when the capacitors C1 and C2 are connected in parallel between the drains and sources of the transistors Q1 and Q2, the resonance frequency is reduced from f0 to f1, and peaks at a frequency f1 lower than 30 MHz. Therefore, it can be seen that the radiation level of electromagnetic waves of 30 MHz or higher is sufficiently reduced, and the radiation of unnecessary electromagnetic waves of 30 MHz or higher can be sufficiently suppressed.
[0080]
As described above, in the present embodiment, since the capacitors C1 and C2 are connected in parallel between the drains and sources of the transistors Q1 and Q2, the LC generated when the transistors Q1 to Q4 change from off to on. The resonance frequency of resonance can be moved to a low frequency of less than 30 MHz. Therefore, radiation of high-frequency electromagnetic waves of 30 MHz or higher can be suppressed.
[0081]
Next, another sustain driver used as the sustain driver 4 shown in FIG. 1 will be described. FIG. 6 is a circuit diagram showing a configuration of a sustain driver according to the second embodiment of the present invention.
[0082]
The difference between the sustain driver 4a shown in FIG. 6 and the sustain driver 4 shown in FIG. 3 is that the capacitors C1 and C2 are omitted and capacitors C3 and C4 connected in parallel to the transistors Q3 and Q4 are added. Since the other points are the same as those of the sustain driver 4 shown in FIG. 3, the same parts are denoted by the same reference numerals, and detailed description thereof will be omitted.
[0083]
As shown in FIG. 6, the capacitor C3 is connected in parallel between the drain and source of the transistor Q3, and the capacitor C4 is connected in parallel between the drain and source of the transistor Q4. One end of the transistor Q3 is connected to the node N3 through the wiring L3, and one end of the transistor Q4 is connected to the node N3 through the wiring L4. Note that the wiring L3 and the wiring L4 indicate the entire wiring between the drain and the source of the transistor Q3 and the transistor Q4. The transistor Q3 has a drain-source capacitance CP3 as a parasitic capacitance, and the transistor Q4 has a drain-source capacitance CP4 as a parasitic capacitance. The diode D1 has an anode-cathode capacitance CP5 as a parasitic capacitance, and the diode D2 has an anode-cathode capacitance CP6 as a parasitic capacitance.
[0084]
In the present embodiment, transistors Q3 and Q4 correspond to electrical elements, switching means, and sustain pulse switching means, wirings L3 and L4 correspond to wiring means, and capacitors C3 and C4 correspond to frequency reduction means, and are recovered. The coil L corresponds to an inductance element, the recovery capacitor Cr corresponds to a recovery capacitive element, the diodes D1 and D2 correspond to unidirectional conducting elements, and the transistors Q3 and Q4 correspond to switching elements.
[0085]
Next, the operation during the sustain period of the sustain driver 4a configured as described above will be described. FIG. 7 is a timing chart for explaining the operation in the sustain period of sustain driver 4a shown in FIG. FIG. 7 shows control signals S1 to S4 and voltages at nodes N1 to N3 input to transistors Q1 to Q4. Since the basic operation of the sustain driver 4a shown in FIG. 6 is the same as that of the sustain driver 4 shown in FIG. 3, only different points such as the LC resonance generation mechanism will be described in detail below.
[0086]
First, LC resonance due to the drain-source capacitance CP4 of the transistor Q4 and the inductance component of the wiring L4 occurs when the transistor Q4 is in an off state and a sudden voltage change occurs between the drain and source of the transistor Q4. To do. Specifically, LC resonance occurs due to the drain-source capacitance CP4 and the inductance component of the wiring L4 at times t1 and t2 shown in FIG.
[0087]
At time t1, the control signal S3 becomes high level, the transistor Q3 is turned on, and LC resonance occurs at the moment when the potential of the node N2 rises from 0V to the potential of the node N3 of about Vsus / 2. At this time, a high-frequency current tends to flow from the node N2 toward the node N3 via the anode-cathode capacitance CP6 of the diode D2, the drain-source capacitance CP4 of the transistor Q4, and the wiring L4. For this reason, high-frequency LC resonance is generated by the drain-source capacitance CP4 of the transistor Q4 and the inductance component of the wiring L4, and is radiated as high-frequency electromagnetic waves.
[0088]
At time t2, when the potential of the node N1 starts to drop from the peak voltage due to LC resonance by the recovery coil L and the panel capacitance Cp, and the direction of the current flowing through the recovery coil L is reversed from the node N1 to the node N2, the diode D1 Becomes non-conductive, the current is cut off, and the potential of the node N2 rapidly rises toward the potential of the node N1. At this time, LC resonance is generated by the stray capacitance connected to the node N2 such as the capacitance CP5 between the anode and the cathode of the diode D1 and the recovery coil L, and at the moment when the potential of the node N2 rises while ringing, LC resonance occurs.
[0089]
At this time, the diode D2 is turned on, and a high-frequency current tends to flow from the node N2 toward the node N3 via the drain-source capacitance CP4 of the transistor Q4 and the wiring L4. For this reason, high-frequency LC resonance is generated by the drain-source capacitance CP4 of the transistor Q4 and the inductance component of the wiring L4, and is radiated as high-frequency electromagnetic waves.
[0090]
However, in this embodiment, since the capacitor C4 is connected in parallel to the transistor Q4, the capacitance contributing to the LC resonance due to the drain-source capacitance CP4 of the transistor Q4 and the inductance component of the wiring L4 is the same as that of the transistor Q4. Since the capacitance is the sum of the drain-source capacitance CP4 and the capacitor C4, the resonance frequency is lower than the resonance frequency due to the drain-source capacitance CP4 alone. Specifically, the capacitance of the capacitor C4 is set so that the resonance frequency of the LC resonance is less than 30 MHz, and the radiation of unnecessary electromagnetic waves of 30 MHz or more is suppressed.
[0091]
Next, the LC resonance due to the drain-source capacitance CP3 of the transistor Q3 and the inductance component of the wiring L3 occurs when the transistor Q3 is in an off state and a sudden voltage change occurs between the drain and source of the transistor Q3. appear. Specifically, LC resonance occurs due to the inductance component of the drain-source capacitance CP3 and the wiring L3 at times t3 and t4 shown in FIG.
[0092]
At time t3, from the state where the power recovery period at the rise of the sustain pulse Psu ends, the control signal S1 becomes high level, the transistor Q1 is turned on, and the voltage Vsus of the power supply terminal V1 is applied to the node N2. The LC resonance occurs at the moment when the control signal S4 becomes high level, the transistor Q4 is turned on, and the potential of the node N2 falls from Vsus to the potential of the node N3 of about Vsus / 2.
[0093]
At this time, a high-frequency current tends to flow from the node N3 toward the node N2 via the wiring L3, the capacitance CP3 between the drain and source of the transistor Q3, and the capacitance CP5 between the anode and cathode of the diode D1. For this reason, high-frequency LC resonance is generated by the drain-source capacitance CP3 of the transistor Q3 and the inductance component of the wiring L3, and is radiated as high-frequency electromagnetic waves.
[0094]
Further, at time t4, when the power recovery period at the fall of the sustain pulse Psu ends and the direction of the current flowing through the recovery coil L is reversed from the node N2 to the node N1, the diode D2 becomes non-conductive. The current is cut off, and the potential of the node N2 suddenly drops toward the potential of the node N1. At this time, the LC resonance is generated by the stray capacitance connected to the node N2 such as the capacitance CP6 between the anode and the cathode of the diode D2 and the recovery coil L, and at the moment when the potential of the node N2 falls while ringing, the high frequency LC resonance occurs.
[0095]
At this time, the diode D1 is turned on, and a high-frequency current tends to flow from the node N3 toward the node N2 via the wiring L3 and the drain-source capacitance CP3 of the transistor Q3. For this reason, high-frequency LC resonance is generated by the drain-source capacitance CP3 of the transistor Q3 and the inductance component of the wiring L3, and is radiated as high-frequency electromagnetic waves.
[0096]
However, since the capacitor C3 is connected in parallel with the transistor Q3 in this embodiment, the capacitance contributing to the LC resonance due to the drain-source capacitance CP3 of the transistor Q3 and the inductance component of the wiring L3 is the same as that of the transistor Q3. Since the capacitance is the sum of the drain-source capacitance CP3 and the capacitor C3, the resonance frequency is lower than the resonance frequency due to the drain-source capacitance CP3 alone. Specifically, the capacitance of the capacitor C3 is set so that the resonance frequency of this LC resonance is less than 30 MHz, and the radiation of unnecessary electromagnetic waves of 30 MHz or more is suppressed.
[0097]
As described above, also in this embodiment, the capacitors C3 and C4 are connected in parallel between the drains and sources of the transistors Q3 and Q4. Therefore, the inductance components of the wirings L3 and L4 and the drains and sources of the transistors Q3 and Q4 The resonance frequency of the LC resonance generated by the capacitors CP3 and CP4 between them can be moved to a low frequency of less than 30 MHz. Therefore, radiation of high-frequency electromagnetic waves of 30 MHz or higher can be suppressed.
[0098]
FIG. 8 is a circuit diagram showing a configuration of a sustain driver according to the third embodiment of the present invention.
[0099]
The difference between the sustain driver 4b shown in FIG. 8 and the sustain driver 4 shown in FIG. 3 is that the capacitors C1 and C2 are omitted, and capacitors C5 and C6 connected in parallel to the diodes D1 and D2 are added. Since the other points are the same as those of the sustain driver 4 shown in FIG. 3, the same parts are denoted by the same reference numerals, and detailed description thereof will be omitted.
[0100]
As shown in FIG. 8, the capacitor C5 is connected in parallel between the anode and the cathode of the diode D1, and the capacitor C6 is connected in parallel between the anode and the cathode of the diode D2. The cathode of the diode D1 is connected to the node N2 via the wiring L5, and the anode of the diode D2 is connected to the node N2 via the wiring L6. The diode D1 has an anode-cathode capacitance CP5 as a parasitic capacitance, and the diode D2 has an anode-cathode capacitance CP6 as a parasitic capacitance. The transistors Q3 and Q4 also have parasitic capacitances CP3 and CP4 as in the second embodiment.
[0101]
In the present embodiment, the diodes D1 and D2 correspond to electrical elements, switching means, and sustain pulse switching means, the wirings L5 and L6 correspond to wiring means, and the capacitors C5 and C6 correspond to frequency reduction means, and are recovered. The coil L corresponds to an inductance element, the recovery capacitor Cr corresponds to a recovery capacitive element, the diodes D1 and D2 correspond to unidirectional conducting elements, and the transistors Q3 and Q4 correspond to switching elements.
[0102]
Next, the operation during the sustain period of the sustain driver 4b configured as described above will be described. Since the basic operation of the sustain driver 4b shown in FIG. 8 is the same as that of the sustain drivers 4 and 4a shown in FIGS. 3 and 6, only different points such as the LC resonance generation mechanism will be described in detail below. .
[0103]
First, LC resonance due to the anode-cathode capacitance CP5 of the diode D1 and the inductance component of the wiring L5 occurs when the diode D1 is in an off state and a sudden voltage change occurs between the anode and cathode of the diode D1. To do. Specifically, LC resonance occurs due to the inductance component of the anode-cathode capacitor CP5 and the wiring L5 at times t2 and t3 shown in FIG.
[0104]
At time t2, since the control signal S3 becomes high level, the transistor Q3 is turned on, and the potential of the node N2 is the same as the potential of the node N3, ie, about Vsus / 2, the potential of the node N1 is recovered from the recovery coil L. When the direction of the current flowing through the recovery coil L is reversed from the node N1 to the node N2 due to the LC resonance due to the LC resonance due to the panel capacitance Cp, the diode D1 becomes non-conductive and the current is cut off from the path. The potential of the node N2 increases rapidly toward the potential of the node N1. At this time, LC resonance is generated by the stray capacitance connected to the node N2 such as the capacitance CP5 between the anode and the cathode of the diode D1 and the recovery coil L, and at the moment when the potential of the node N2 rises while ringing, LC resonance occurs.
[0105]
At this time, the diode D1 is in a reverse bias state and is turned off, but the transistor Q3 is turned on, so that a high-frequency current flows from the node N2 via the wiring L5 and the capacitance CP5 between the anode and cathode of the diode D1. It tries to flow toward the node N3. For this reason, high-frequency LC resonance occurs due to the anode-cathode capacitance CP5 of the diode D1 and the inductance component of the wiring L5, and is radiated as high-frequency electromagnetic waves.
[0106]
At time t3, the power recovery period at the rise of the sustain pulse Psu ends, the control signal S1 becomes high level, the transistor Q1 is turned on, and the voltage Vsus of the power supply terminal V1 is applied to the node N2. Therefore, the LC resonance occurs at the moment when the control signal S4 becomes high level, the transistor Q4 is turned on, and the potential of the node N2 falls from Vsus to the potential of the node N3 of about Vsus / 2.
[0107]
At this time, a high-frequency current tends to flow from the node N3 to the node N2 via the drain-source capacitance CP3 of the transistor Q3, the anode-cathode capacitance CP5 of the diode D1, and the wiring L5. For this reason, high-frequency LC resonance occurs due to the anode-cathode capacitance CP5 of the diode D1 and the inductance component of the wiring L5, and is radiated as high-frequency electromagnetic waves.
[0108]
However, in the present embodiment, since the capacitor C5 is connected in parallel to the diode D1, the capacitance CP5 between the anode and the cathode of the diode D1 and the capacitance contributing to the LC resonance due to the inductance component of the wiring L5 is the capacitance of the diode D1. Since the capacitance CP5 between the anode and the cathode and the capacitor C5 are added, the resonance frequency is lower than the resonance frequency due to only the capacitance CP5 between the anode and the cathode. Specifically, the capacitance of the capacitor C5 is set so that the resonance frequency of the LC resonance is less than 30 MHz, and radiation of unnecessary electromagnetic waves of 30 MHz or more is suppressed.
[0109]
Next, the LC resonance due to the anode-cathode capacitance CP6 of the diode D2 and the inductance component of the wiring L6 occurs when the diode D2 is in an off state and a sudden voltage change occurs between the anode and the cathode of the diode D2. appear. Specifically, LC resonance occurs due to the inductance component of the anode-cathode capacitor CP6 and the wiring L6 at times t1 and t4 shown in FIG.
[0110]
At time t1, the control signal S3 becomes high level, the transistor Q3 is turned on, and LC resonance occurs at the moment when the potential of the node N2 rises from 0V to the potential of the node N3 of about Vsus / 2. At this time, a high-frequency current tends to flow from the node N2 toward the node N3 via the wiring L6, the capacitance CP6 between the anode and cathode of the diode D2, and the capacitance CP4 between the drain and source of the transistor Q4. For this reason, high-frequency LC resonance occurs due to the anode-cathode capacitance CP6 of the diode D2 and the inductance component of the wiring L6, and is radiated as high-frequency electromagnetic waves.
[0111]
Further, at time t4, when the power recovery period at the fall of the sustain pulse Psu ends and the direction of the current flowing through the recovery coil L is reversed from the node N2 to the node N1, the diode D2 becomes non-conductive. The current is cut off, and the potential of the node N2 suddenly drops toward the potential of the node N1. At this time, the LC resonance is generated by the stray capacitance connected to the node N2 such as the capacitance CP6 between the anode and the cathode of the diode D2 and the recovery coil L, and at the moment when the potential of the node N2 falls while ringing, the high frequency LC resonance occurs.
[0112]
At this time, the diode D2 is in a reverse bias state and is turned off, but the transistor Q4 is turned on, so that a high-frequency current flows from the node N3 through the anode CP and the cathode CP6 of the diode D2 and the wiring L6. It tries to flow toward the node N2. For this reason, high-frequency LC resonance occurs due to the anode-cathode capacitance CP6 of the diode D2 and the inductance component of the wiring L6, and is radiated as high-frequency electromagnetic waves.
[0113]
However, in the present embodiment, since the capacitor C6 is connected in parallel to the diode D2, the capacitance CP6 between the anode and the cathode of the diode D2 and the capacitance contributing to the LC resonance due to the inductance component of the wiring L6 is the capacitance of the diode D2. Since the capacitance CP6 between the anode and the cathode and the capacitor C6 are added, the resonance frequency is lower than the resonance frequency due to only the capacitance CP6 between the anode and the cathode. Specifically, the capacitance of the capacitor C6 is set so that the resonance frequency of the LC resonance is less than 30 MHz, and the radiation of unnecessary electromagnetic waves of 30 MHz or more is suppressed.
[0114]
As described above, also in this embodiment, the capacitors C5 and C6 are connected in parallel between the anodes and cathodes of the diodes D1 and D2, so that the inductance components of the wirings L5 and L6 and the anodes and cathodes of the diodes D1 and D2 The resonance frequency of the LC resonance generated by the capacitors CP5 and CP6 between them can be moved to a low frequency of less than 30 MHz. Therefore, radiation of high-frequency electromagnetic waves of 30 MHz or higher can be suppressed.
[0115]
FIG. 9 is a circuit diagram showing a configuration of a sustain driver according to the fourth embodiment of the present invention.
[0116]
The difference between the sustain driver 4c shown in FIG. 9 and the sustain driver 4 shown in FIG. 3 is that the capacitors C1 and C2 are omitted, a diode D3 and a capacitor C7 are added between the power supply terminal V1 and the node N2, and the node N2 The diode D4 and the capacitor C8 are added between the first and second terminals, and the other points are the same as those of the sustain driver 4 shown in FIG. Description is omitted.
[0117]
As shown in FIG. 9, the diode D3 has a cathode connected to the power supply terminal V1, and an anode connected to the node N2 via the wiring L7. The diode D3 has a capacitance CP7 between the anode and the cathode as a parasitic capacitance, and a capacitor C7 is connected in parallel between the anode and the cathode of the diode D3.
[0118]
The diode D4 has a cathode connected to the node N2 via the wiring L8 and an anode connected to the ground terminal. The diode D4 has a capacitance CP8 between the anode and the cathode as a parasitic capacitance, and a capacitor C8 is connected in parallel between the anode and the cathode of the diode D4.
[0119]
The diodes D3 and D4 are added for the purpose of current clipping, and protect the transistors Q3 and Q4 from being applied with a voltage higher than the withstand voltage when the withstand voltages of the transistors Q3 and Q4 are low. Therefore, diode D3 is normally in an off state and is turned on only when the potential of node N2 exceeds Vsus, and diode D4 is normally in an off state and is turned on only when the potential of node N2 is lower than 0V. Therefore, the potential of the node N2 is clipped in the range of 0V to Vsus.
[0120]
In the present embodiment, the diodes D3 and D4 correspond to electrical elements and protection means, the wirings L7 and L8 correspond to wiring means, the capacitors C7 and C8 correspond to frequency reduction means, and the power supply terminal V1 and the ground terminal are It corresponds to a voltage source, the recovery coil L corresponds to an inductance element, the recovery capacitor Cr corresponds to a capacitive element for recovery, the transistors Q3 and Q4 and the diodes D1 and D2 correspond to connection means, and the diodes D3 and D4 Unidirectional conducting elements and capacitors C7 and C8 correspond to capacitive elements.
[0121]
Next, the operation during the sustain period of the sustain driver 4c configured as described above will be described. FIG. 10 is a timing chart for explaining the operation during the sustain period of sustain driver 4c shown in FIG. FIG. 10 shows control signals S1 to S4 and voltages at nodes N1 to N3 input to transistors Q1 to Q4. Since the basic operation of the sustain driver 4c shown in FIG. 9 is the same as that of the sustain drivers 4 and 4a shown in FIGS. 3 and 6, only different points such as the generation mechanism of LC resonance will be described in detail below. .
[0122]
First, LC resonance due to the anode-cathode capacitance CP7 of the diode D3 and the inductance component of the wiring L7 occurs when the diode D3 is in an OFF state and a sudden voltage change occurs between the anode and cathode of the diode D3. To do. Here, since the potential on the cathode side of the diode D3 is fixed to Vsus by the power supply terminal V1, the voltage between the anode and the cathode of the diode D3 changes at every timing when the potential of the node N2 changes.
[0123]
Specifically, as shown in FIG. 10, at the instant when the transistor Q3 is turned on and the potential of the node N2 rises from 0V toward about Vsus / 2, that is, at the time t1, the power recovery period at the end of the rise ends and the node The moment when the potential of N2 rises toward Vsus, that is, time t2, the moment when transistor Q4 is turned on and the potential of node N2 falls from Vsus toward about Vsus / 2, that is, time t3, and the power recovery period at the time of falling At the instant when the potential of the node N2 drops toward 0V, that is, at each timing of time t4, the voltage between the anode and the cathode of the diode D3 changes. At this time, a high-frequency current flows through the anode-cathode capacitor CP7, high-frequency LC resonance is generated by the anode-cathode capacitor CP7 of the diode D3 and the inductance component of the wiring L7, and is radiated as a high-frequency electromagnetic wave.
[0124]
However, in the present embodiment, since the capacitor C7 is connected in parallel to the diode D3, the capacitance contributing to the LC resonance due to the anode-cathode capacitance CP7 of the diode D3 and the inductance component of the wiring L7 is the capacitance of the diode D3. Since the capacitance CP7 between the anode and the cathode and the capacitor C7 are added, the resonance frequency is lower than the resonance frequency due to only the capacitance CP7 between the anode and the cathode. Specifically, the capacitance of the capacitor C7 is set so that the resonance frequency of the LC resonance is less than 30 MHz, and the radiation of unnecessary electromagnetic waves of 30 MHz or more is suppressed.
[0125]
Next, the LC resonance due to the anode-cathode capacitance CP8 of the diode D4 and the inductance component of the wiring L8 is when the diode D4 is in an OFF state and a sudden voltage change occurs between the anode and the cathode of the diode D4. appear. Here, since the potential on the anode side of the diode D4 is fixed to 0 V by the ground terminal, the voltage between the anode and the cathode of the diode D3 changes at every timing when the potential of the node N2 changes.
[0126]
Therefore, similarly to the diode D3, the voltage between the anode and the cathode of the diode D4 changes at each timing from the time t1 to t4. At this time, a high-frequency current flows through the anode-cathode capacitor CP8, high-frequency LC resonance occurs due to the anode-cathode capacitor CP8 of the diode D4 and the inductance component of the wiring L8, and the high-frequency electromagnetic wave is radiated.
[0127]
However, in the present embodiment, since the capacitor C8 is connected in parallel to the diode D4, the capacitance CP8 between the anode and the cathode of the diode D4 and the capacitance contributing to the LC resonance due to the inductance component of the wiring L8 is the capacitance of the diode D4. Since the capacitance CP8 between the anode and cathode and the capacitor C8 are added, the resonance frequency is lower than the resonance frequency due to only the capacitance CP8 between the anode and cathode. Specifically, the capacitance of the capacitor C8 is set so that the resonance frequency of the LC resonance is less than 30 MHz, and the radiation of unnecessary electromagnetic waves of 30 MHz or more is suppressed.
[0128]
As described above, also in this embodiment, the capacitors C7 and C8 are connected in parallel between the anode and cathode of the diodes D3 and D4. Therefore, the inductance components of the wirings L7 and L8 and the anode and cathode of the diodes D3 and D4 are used. The resonance frequency of the LC resonance generated by the capacitors CP7 and CP8 between them can be moved to a low frequency of less than 30 MHz. Therefore, radiation of high-frequency electromagnetic waves of 30 MHz or higher can be suppressed.
[0129]
FIG. 11 is a circuit diagram showing a configuration of a sustain driver according to the fifth embodiment of the present invention.
[0130]
The sustain driver 4d shown in FIG. 11 is different from the sustain driver 4 shown in FIG. 3 in that diodes D3 and D4 and capacitors C5 to C8 are added similarly to the sustain drivers 4b and 4c shown in FIGS. Since the other points are the same as those of the sustain driver 4 shown in FIG. 3, the same parts are denoted by the same reference numerals, and detailed description thereof will be omitted.
[0131]
In the present embodiment, the capacitors C1, C2, C5 to C8 are connected in parallel to the transistors Q1 and Q2 and the diodes D1 to D4 as in the first, third and fourth embodiments. The effects of the third and fourth embodiments can be obtained, the resonance frequency of each LC resonance can be moved to a lower frequency of less than 30 MHz, and radiation of high-frequency electromagnetic waves of 30 MHz or more can be further suppressed. . In addition, the combination of each embodiment is not specifically limited to said example, It can combine variously and can acquire the effect of each embodiment combined similarly.
[0132]
In each of the above descriptions, the sustain driver has been described as an example of the drive circuit. However, the present invention can be applied to the scan driver in the same manner as described above, and in that case, the same effect can be obtained. For example, when the present invention is applied to the scan driver 3 shown in FIG.
[0133]
FIG. 12 is a circuit diagram showing a configuration of a scan driver according to the sixth embodiment of the present invention.
[0134]
The difference between the scan driver 3 shown in FIG. 12 and the sustain driver 4 shown in FIG. 3 is that transistors Q31 to Q36, capacitors C31 to C34, resistors R31 and R32, power supply for generating the initialization pulse Pset in the initialization period. An initialization circuit composed of Vc1, Vc2 and a power supply terminal V31 is added, and protective diodes D3 to D5 are added. The other points are the same as those of the sustain driver 4 shown in FIG. The same parts are denoted by the same reference numerals, and detailed description thereof will be omitted below.
[0135]
As shown in FIG. 12, one end of the transistor Q31 is connected to the power supply terminal V31, the other end is connected to the node N1 via the wiring L31, and its gate is connected to the node N31. The transistor Q31 has a drain-source capacitance CP31 as a parasitic capacitance, and a capacitor C31 is connected in parallel between the drain and source of the transistor Q31. Capacitor C33 is connected between power supply terminal V31 and node N31. A setup voltage Vset is applied to the power supply terminal V31.
[0136]
One end of the transistor Q33 is connected to the node N1 via the power supply Vc1, the other end is connected to one end of the resistor R31, and the control signal S31 is input to the gate thereof. The other end of resistor R31 is connected to node N31. One end of the transistor Q35 is connected to the node N31, the other end is connected to the node N1, and a control signal S31 is input to the gate thereof.
[0137]
One end of transistor Q32 is connected to the ground terminal, the other end is connected to node N1 via line L32, and its gate is connected to node N32. Transistor Q32 has a drain-source capacitance CP32 as a parasitic capacitance, and a capacitor C32 is connected in parallel between the drain and source of transistor Q32. Capacitor C34 is connected between nodes N1 and N32.
[0138]
One end of the transistor Q34 is connected to the ground terminal via the power source Vc2, the other end is connected to one end of the resistor R32, and the control signal S32 is input to the gate thereof. The other end of the resistor R32 is connected to the node N32. One end of the transistor Q36 is connected to the node N32, the other end is connected to the ground terminal, and the control signal S32 is input to the gate thereof. Further, protective diodes D3 to D5 are connected between a connection point between the diode D5 and the transistor Q1 and the node N2, between the node N2 and the ground terminal, and between the power supply terminal V1 and the transistor Q1.
[0139]
In the present embodiment, the transistors Q31 and Q32 correspond to electrical elements, switching means and initialization pulse switching means, the wirings L31 and L32 correspond to wiring means, and the capacitors C31 and C32 correspond to frequency reduction means. The power supply terminal V31 and the ground terminal correspond to a voltage source. The transistor Q31 corresponds to the first switching means, the transistor Q32 corresponds to the second switching means, the wiring L31 corresponds to the first wiring means, the wiring L32 corresponds to the second wiring means, The capacitor C31 corresponds to the first capacitive element, the capacitor C32 corresponds to the second capacitive element, the power supply terminal V31 corresponds to the first voltage source, and the ground terminal corresponds to the second voltage source. .
[0140]
Next, the operation of the initialization circuit configured as described above will be described. Note that the operation of the scan driver 3 during the sustain period is the same as that shown in FIG.
[0141]
First, when the potential of the initialization pulse Pset is 0V, the transistors Q31 and Q32 are both in the off state. That is, the control signals S31 and S32 both become high level, the transistors Q35 and Q36 are turned on, the gate-source voltage of the transistors Q31 and Q32 becomes 0 V, and both the transistors Q31 and Q32 are turned off.
[0142]
Next, when the control signal S31 becomes low level, the transistor Q35 is turned off, and the gate of the transistor Q31 is disconnected from the node N1. At this time, the transistor Q33 is turned on, a current flows from the power supply terminal V31 to the gate of the transistor Q31 with a time constant determined by the capacitor C33 and the resistor R31, and the potential of the gate of the transistor Q31 starts to rise.
[0143]
When the voltage of the node N31 reaches a level at which the transistor Q31 can be turned on in this state, the transistor Q31 is turned on, and the source potential of the transistor Q31, that is, the potential of the node N1 starts to gradually increase. When the potential of the node N1 rises, the potential of the power supply Vc1 also rises with the rise, and the transistor Q33 continues to be on. As a result, the potential of the node N1 becomes equal to the setup voltage Vset of the power supply terminal V31 and is saturated.
[0144]
Next, when the control signal S31 is returned to a high level, the transistor Q35 is turned on, the potential of the gate of the transistor Q31 becomes equal to the source potential at once, and the transistor Q31 is turned off. Immediately after this operation, when the control signal S32 is set to the low level, the transistor Q36 is turned off and the transistor Q34 is turned on, and the potential of the gate of the transistor Q32 starts to rise at a time constant determined by the resistor R32 and the capacitor C32.
[0145]
In this state, when the potential of the gate of the transistor Q32 rises to a predetermined potential, the transistor Q32 starts to be turned on. Therefore, the charge stored in the node N1 is gradually discharged through the transistor Q32, and the voltage at the node N1 Finally drops to 0V.
[0146]
With the above operation, as shown in FIG. 2, the initialization pulse Pset having a triangular waveform that rises from 0 V to the voltage Vset by the ramp waveform and falls from Vset to 0 V by the ramp waveform is output in the initialization period.
[0147]
Thus, the transistors Q31 and Q32 are used to generate the initialization pulse Pset in the initialization period, but are connected to the node N1 of the current supply path through which the current for charging and discharging the panel capacitance Cp flows. In the period other than the initialization period, it is always in the off state. Therefore, the capacitors CP31 and CP32 between the drains and sources of the transistors Q31 and Q32 are connected to the node N1 as loads.
[0148]
Here, since the potential at one end of the transistors Q31 and Q32 is a fixed potential, that is, the voltage Vset or the ground potential, a high-frequency current flows through the drain-source capacitors CP31 and CP32 when the potential of the node N1 changes. . In particular, the moment when sustain pulse Psc is clamped to Vsus from the power recovery period when rising, that is, immediately after time t2, and the moment when sustain pulse Psc is clamped to the ground potential from the power recovery period when falling, that is, immediately after time t4. In addition, a high-frequency current flows. For this reason, high frequency LC resonance is generated by the drain-source capacitances CP31 and CP32 of the transistors Q31 and Q32 and the wirings L31 and L32, and is radiated as high frequency electromagnetic waves.
[0149]
However, in this embodiment, the capacitors C31 and C32 are connected in parallel to the transistors Q31 and Q32, respectively, so that the capacitances CP31 and CP32 between the drains and sources of the transistors Q31 and Q32 and the inductance components of the wirings L31 and L32 are used. The capacitance contributing to the LC resonance is a capacitance obtained by adding the capacitances CP31 and CP32 between the drains and sources of the transistors Q31 and Q32 and the capacitors C31 and C32, respectively. It is reduced from the resonance frequency by only. Specifically, the capacities of the capacitors C31 and C32 are set so that the resonance frequency of these LC resonances is less than 30 MHz, and the radiation of unnecessary electromagnetic waves of 30 MHz or more is suppressed.
[0150]
As described above, also in this embodiment, the capacitors C31 and C32 are connected in parallel between the drains and sources of the transistors Q31 and Q32, so that the inductance components of the wirings L31 and L32 and the drains and sources of the transistors Q31 and Q32 The resonance frequency of the LC resonance generated by the capacitors CP31 and CP32 between them can be moved to a low frequency of less than 30 MHz. Therefore, radiation of high-frequency electromagnetic waves of 30 MHz or higher can be suppressed.
[0151]
【The invention's effect】
According to the present invention, the resonance frequency of the LC resonance between the parasitic capacitance of the electric element connected to the pulse supply path for supplying the drive pulse to the capacitive load and the inductance component of the wiring means is reduced. The frequency of electromagnetic waves generated by resonance can be reduced, and radiation of unnecessary high-frequency electromagnetic waves can be suppressed.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a plasma display device using a sustain driver according to a first embodiment of the present invention.
2 is a timing chart showing an example of drive voltages of scan electrodes and sustain voltages in the PDP shown in FIG.
3 is a circuit diagram showing a configuration of the sustain driver shown in FIG. 1 according to the first embodiment of the present invention.
FIG. 4 is a diagram showing a relationship between a drain-source voltage and a capacitance when a capacitor is connected between the drain and source of an FET and when the capacitor is not connected;
5 is a diagram showing the relationship between the radiation level and frequency of electromagnetic waves emitted from the plasma display device shown in FIG.
FIG. 6 is a circuit diagram showing a configuration of a sustain driver according to a second embodiment of the present invention;
7 is a timing chart for explaining the operation in the sustain period of the sustain driver shown in FIG.
FIG. 8 is a circuit diagram showing a configuration of a sustain driver according to a third embodiment of the present invention;
FIG. 9 is a circuit diagram showing a configuration of a sustain driver according to a fourth embodiment of the present invention;
10 is a timing chart for explaining the operation in the sustain period of the sustain driver shown in FIG. 9;
FIG. 11 is a circuit diagram showing a configuration of a sustain driver according to a fifth embodiment of the present invention;
FIG. 12 is a circuit diagram showing a configuration of a scan driver according to a sixth embodiment of the present invention.
FIG. 13 is a circuit diagram showing a configuration of a conventional sustain driver.
14 is a timing chart showing an operation during the sustain period of the sustain driver shown in FIG.
[Explanation of symbols]
1 PDP
2 Data driver
3 Scan driver
3a Scan driver IC
4, 4a-4d Sustain driver
11 Address electrode
12 Scan electrodes
13 Sustain electrode
C1-C8, C31-C34 capacitors
Q1-Q4, Q31-Q36 Field effect transistor
D1-D5 diode

Claims (2)

A recovery capacitor that supplies charge to the capacitive load of the plasma display panel;
  First switching means connected to a first voltage source;
  Wiring means connected between the first switching means and the plasma display;
  A first capacitive element connected in parallel to the first switching means and connecting the first voltage source and the wiring means;
  A second switching means connected to a second voltage source and the wiring means;
  A second capacitive element connected in parallel to the second switching means and connecting the second voltage source and the wiring means;
  Third switching means connected to the recovery capacitor;
  An inductance element connected between the third switching means and the wiring means;
  By turning on the third switching means, the potential of the wiring means rises and starts to decrease from the peak voltage, and then the first switching means is turned on to change the potential of the wiring means to the first voltage. A plasma display device configured to have a source potential. A recovery capacitor that supplies charge to the capacitive load of the plasma display panel;
First switching means connected to a first voltage source;
Wiring means connected between the first switching means and the plasma display;
A second switching means connected to a second voltage source and the wiring means;
Third switching means connected to the recovery capacitor;
An inductance element connected between the third switching means and the wiring means;
A capacitive element connected in parallel to the third switching means and connecting the recovery capacitor and the inductance element;
By turning on the third switching means, the potential of the wiring means rises and starts to decrease from the peak voltage, and then the first switching means is turned on to change the potential of the wiring means to the first voltage. A plasma display device configured to have a source potential.

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