JPH0563955B2 - - Google Patents

Info

Publication number
JPH0563955B2
JPH0563955B2 JP59146035A JP14603584A JPH0563955B2 JP H0563955 B2 JPH0563955 B2 JP H0563955B2 JP 59146035 A JP59146035 A JP 59146035A JP 14603584 A JP14603584 A JP 14603584A JP H0563955 B2 JPH0563955 B2 JP H0563955B2
Authority
JP
Japan
Prior art keywords
thin film
film layer
wiring board
thickness
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59146035A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6126282A (ja
Inventor
Koji Kanehara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP14603584A priority Critical patent/JPS6126282A/ja
Priority to FR858510660A priority patent/FR2567709B1/fr
Publication of JPS6126282A publication Critical patent/JPS6126282A/ja
Priority to FR8615585A priority patent/FR2590105A1/fr
Priority to US07/115,565 priority patent/US4840924A/en
Publication of JPH0563955B2 publication Critical patent/JPH0563955B2/ja
Granted legal-status Critical Current

Links

JP14603584A 1984-07-11 1984-07-16 多層配線基板 Granted JPS6126282A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP14603584A JPS6126282A (ja) 1984-07-16 1984-07-16 多層配線基板
FR858510660A FR2567709B1 (fr) 1984-07-11 1985-07-11 Ensemble a paillette comprenant un substrat de cablage multi-couche
FR8615585A FR2590105A1 (fr) 1984-07-11 1986-11-07 Ensemble a paillette comprenant un substrat de cablage multicouche
US07/115,565 US4840924A (en) 1984-07-11 1987-10-29 Method of fabricating a multichip package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14603584A JPS6126282A (ja) 1984-07-16 1984-07-16 多層配線基板

Publications (2)

Publication Number Publication Date
JPS6126282A JPS6126282A (ja) 1986-02-05
JPH0563955B2 true JPH0563955B2 (fr) 1993-09-13

Family

ID=15398632

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14603584A Granted JPS6126282A (ja) 1984-07-11 1984-07-16 多層配線基板

Country Status (1)

Country Link
JP (1) JPS6126282A (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62239596A (ja) * 1986-04-11 1987-10-20 株式会社日立製作所 配線基板
JP2552159B2 (ja) * 1987-02-02 1996-11-06 セイコーエプソン株式会社 半導体装置及びその製造方法
JP4890983B2 (ja) * 2006-07-18 2012-03-07 矢崎総業株式会社 コネクタ及びコネクタユニット
JP5439900B2 (ja) * 2009-03-30 2014-03-12 株式会社村田製作所 ランド構造

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5427956A (en) * 1977-08-01 1979-03-02 Nippon Electric Co Method of making thick film integrated circuit
JPS5759473B2 (fr) * 1973-07-25 1982-12-15 Bosch Gmbh Robert

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS593588Y2 (ja) * 1980-01-10 1984-01-31 株式会社精工舎 回路基板
JPS5930551Y2 (ja) * 1980-09-26 1984-08-31 株式会社日立製作所 配線補修用ラインを持った配線板

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5759473B2 (fr) * 1973-07-25 1982-12-15 Bosch Gmbh Robert
JPS5427956A (en) * 1977-08-01 1979-03-02 Nippon Electric Co Method of making thick film integrated circuit

Also Published As

Publication number Publication date
JPS6126282A (ja) 1986-02-05

Similar Documents

Publication Publication Date Title
US4840924A (en) Method of fabricating a multichip package
US4710592A (en) Multilayer wiring substrate with engineering change pads
US4463059A (en) Layered metal film structures for LSI chip carriers adapted for solder bonding and wire bonding
US7089652B2 (en) Method of manufacturing flip chip resistor
US6144100A (en) Integrated circuit with bonding layer over active circuitry
US5384204A (en) Tape automated bonding in semiconductor technique
JP2528617B2 (ja) 多層相互接続金属構造体およびその形成方法
US6614113B2 (en) Semiconductor device and method for producing the same
US6555763B1 (en) Multilayered circuit board for semiconductor chip module, and method of manufacturing the same
JPS62199043A (ja) 薄膜回路及びその製造法
JPH0563955B2 (fr)
EP0468787A2 (fr) Transport automatique sur bande pour la technique des semi-conducteurs
JP3153115B2 (ja) 回路基板
JPH02168640A (ja) 異なる基板間の接続構造
JP3170429B2 (ja) 配線基板
JPH03268385A (ja) はんだバンプとその製造方法
JPH0789574B2 (ja) ペレット取付基板の製造方法
JP3622160B2 (ja) セラミック基板およびその製造方法
JPS61102095A (ja) 多層配線基板
JPS6196754A (ja) ピン付き基板
JPH01238132A (ja) 半田接続用電極及び半田接続用電極の製造方法
JPS592329A (ja) 半導体集積回路基板の製造方法
JPH0312988A (ja) 金導体厚膜印刷配線基板
JPS6035597A (ja) 多層配線構造
JPH08162458A (ja) 電子部品の接続構造及び接続方法

Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term