JPH0563112B2 - - Google Patents
Info
- Publication number
- JPH0563112B2 JPH0563112B2 JP1134180A JP13418089A JPH0563112B2 JP H0563112 B2 JPH0563112 B2 JP H0563112B2 JP 1134180 A JP1134180 A JP 1134180A JP 13418089 A JP13418089 A JP 13418089A JP H0563112 B2 JPH0563112 B2 JP H0563112B2
- Authority
- JP
- Japan
- Prior art keywords
- component
- circuit pattern
- solder
- components
- embedding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 229910000679 solder Inorganic materials 0.000 claims description 28
- 239000000758 substrate Substances 0.000 claims description 23
- 229920005989 resin Polymers 0.000 claims description 13
- 239000011347 resin Substances 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 239000004696 Poly ether ether ketone Substances 0.000 claims description 2
- 229920002530 polyetherether ketone Polymers 0.000 claims description 2
- 238000005553 drilling Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
- 230000035939 shock Effects 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 239000006071 cream Substances 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/368—Assembling printed circuits with other printed circuits parallel to each other
Landscapes
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は、半田バンプによりチツプ部品を基板
へ内蔵した高密度実装モジユールの製造方法に関
する。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method for manufacturing a high-density mounting module in which chip components are built into a board using solder bumps.
(従来の技術)
配線パターンを有する樹脂基板を複数積層し、
その積層基板に、例えば、セラミツクチツプコン
デンサやチツプ抵抗等の部品を埋込むための孔部
を設け、その孔部に部品を挿入し、半田バンプに
より部品を半田接合した小型化を目的とした、通
信機用高密度実装モジユールがある。(Conventional technology) Multiple resin substrates with wiring patterns are laminated,
For the purpose of miniaturization, holes are provided in the multilayer substrate for embedding components such as ceramic chip capacitors and chip resistors, and the components are inserted into the holes and soldered together using solder bumps. There are high-density mounting modules for communication equipment.
(発明が解決しようとする課題)
従来、この種の装置で使用するチツプ部品は小
型化のため、例えば、外形寸法が、幅0.5mm、長
さ1.0mmと小さい部品を使用するが、これら部品
面に半田バンプを形成する場合、半田バンプの半
田量が不均一となり、部品を内蔵して積層化する
際、過剰な半田により回路パターン間および部品
の異極間の短絡が生じ易く、多数の部品を埋込む
ことが困難である。また、接合部分の半田量が不
均一となるため、多数の基板を貼り合わせ、熱衝
撃を加えた場合、接合部分に剥離が生じ易いとい
う不具合がある。この対策として、部品を取付側
の回路パターンに予め半田を印刷して昇温し、半
田バンプを形成する方法があるが、取付ランドバ
ンプ面と埋込む部品を衝合する際、位置合わせが
難しく、多数の部品を実装することが困難である
という不具合を有していた。(Problem to be Solved by the Invention) Conventionally, chip parts used in this type of device are small in size, for example, with external dimensions of 0.5 mm in width and 1.0 mm in length. When forming solder bumps on a surface, the amount of solder on the solder bumps becomes uneven, and when stacking components with built-in components, excessive solder tends to cause short circuits between circuit patterns and between different poles of components, resulting in a large number of short circuits. It is difficult to embed parts. Furthermore, since the amount of solder at the bonded portion is non-uniform, there is a problem in that when a large number of substrates are bonded together and a thermal shock is applied, the bonded portion is likely to peel off. As a countermeasure for this, there is a method of printing solder in advance on the circuit pattern on the mounting side of the component and raising the temperature to form solder bumps, but it is difficult to align the mounting land bump surface and the component to be embedded. However, the problem was that it was difficult to mount a large number of components.
(課題を解決するための手段)
本発明は、これら不具合を解決するために、回
路パターンを有する基板に部品埋込み用の孔部を
設け、予め部品を挿入して、余剰領域および挿入
部品の固定のために樹脂を充填して硬化し、回路
パターン面と同一平面上に部品の取付ランドを構
成し、部品取付部分に半田バンプを構成すること
を特徴とし、その目的は、均一な量の半田バンプ
により短絡のない、熱衝撃に対しても強固で多数
の部品を埋込んだ高密度実装モジユールの提供に
ある。(Means for Solving the Problem) In order to solve these problems, the present invention provides a hole for embedding components in a board having a circuit pattern, inserts the component in advance, and fixes the surplus area and the inserted component. It is characterized by filling a resin and curing it, configuring a component mounting land on the same plane as the circuit pattern surface, and configuring solder bumps on the component mounting area.The purpose is to distribute a uniform amount of solder. The purpose of the present invention is to provide a high-density mounting module that does not cause short circuits due to bumps, is strong against thermal shock, and has a large number of components embedded therein.
以下に図面を用いて詳細に説明する。 This will be explained in detail below using the drawings.
(実施例)
第1図は、本発明の実施例の説明図で、部品を
基板に固定化するための工程説明図、第2図は、
部品を基板に固定化し、回路パターンと同一平面
上に部品の取付ランドを構成した工程説明図、第
3図は、本発明の実施例の説明図で、半田バンプ
を介して基板を多層化した基板の断面図である。
図において、1は部品を埋込み、回路パターンを
有する第1層基板、2は部品を埋込むための孔
部、3は第1層基板1の回路パターン、4は回路
パターンと埋込み用部品の取付部分を同一平面化
するために簡易的に使用する位置出し用フイル
ム、5はチツプコンデンアなどの埋込み用部品、
6は埋込み部品を第1層基板に固定するために充
填する樹脂、7は埋込み部品の取付ランド、8は
埋込み部品の取付ランドに形成した半田バンプ、
9は第2層基板の回路パターンと接合のために第
1層の回路パターン上に構成した半田バンプ、1
1は空隙充填用の樹脂である。(Example) Fig. 1 is an explanatory diagram of an embodiment of the present invention, and is an explanatory diagram of a process for fixing components to a substrate, and Fig. 2 is an explanatory diagram of an embodiment of the present invention.
Fig. 3 is an explanatory diagram of the process of fixing components to a board and configuring a mounting land for the components on the same plane as the circuit pattern. FIG. 3 is a cross-sectional view of the substrate.
In the figure, 1 is a first layer board on which components are embedded and has a circuit pattern, 2 is a hole for embedding components, 3 is a circuit pattern on the first layer board 1, and 4 is a mounting of the circuit pattern and the embedding components. A positioning film that is simply used to make the parts on the same plane, 5 is a part for embedding such as a chip condenser,
6 is a resin filled to fix the embedded component to the first layer board; 7 is a mounting land for the embedded component; 8 is a solder bump formed on the mounting land for the embedded component;
9 is a solder bump formed on the circuit pattern of the first layer for bonding with the circuit pattern of the second layer board; 1
1 is a resin for filling voids.
本発明の実施にあたつては、ガラスエポキシ樹
脂材料などからなる第1層基板1に設けた埋込み
用の孔部2へセラミツクチツプコンデンサなど外
部回路と取付用電極を有する埋込み用部品5を予
め第2層基板10と衝合する両側へ、例えば、接
着性を有するポリエーテルエーテルケトンフイル
ムを押圧、昇温接合した位置出し用フイルム4に
接合して、第1図の構成を得る。その後、エポキ
シ樹脂など接合性を有する液状樹脂を孔部2へ注
入し、固化して充填樹脂6で部品を第1層基板1
の孔部2に固定する。さらに、位置出し用フイル
ム4を基板接合面から剥離すると、回路パターン
3面と同一面上に埋込み用部品5の取付ランドを
位置づける。第2層基板10と回路パターン3を
接合する部分および埋込み用部品5の取付ランド
7へ、例えば、325メツシユのスクリーンを使用
して、半田クリームを印刷し、昇温して半田を溶
融し、半田バンブ8,9を形成し、第2図の構成
を得る。第2層基板10との積層時の介合面にフ
ラツクス成分が存在しないように有機溶剤により
洗浄してから、第2層基板10とピンガイド等を
介して位置精度を出し衝合する。さらに、治具等
を使用して基板全面に均一な荷重がかかるように
押圧を加えながら昇温し、第2層基板10の回路
パターン11と半田バンプ8を介して接合する。
同様の方法、構成を第3層、第4層基板と貼り合
わせた後、基板相互間の空隙部品に液状樹脂12
を真空注入し、部品を内蔵した基板の多層構成の
高密度実装モジユールを得る。 In carrying out the present invention, an embedding component 5 having an external circuit such as a ceramic chip capacitor and a mounting electrode is placed in advance into a embedding hole 2 provided in a first layer substrate 1 made of a glass epoxy resin material or the like. For example, a polyether ether ketone film having adhesive properties is bonded to the positioning film 4 which is pressed and bonded at elevated temperatures to both sides that abut the second layer substrate 10 to obtain the structure shown in FIG. After that, a liquid resin having bonding properties such as epoxy resin is injected into the hole 2, solidified, and the parts are filled with the filling resin 6 into the first layer substrate 1.
Fix it in the hole 2 of. Furthermore, when the positioning film 4 is peeled off from the substrate bonding surface, the mounting land of the embedding component 5 is positioned on the same surface as the circuit pattern 3 surface. For example, a 325 mesh screen is used to print solder cream on the part where the second layer board 10 and the circuit pattern 3 are joined and on the mounting land 7 of the embedded component 5, and the temperature is increased to melt the solder. Solder bumps 8 and 9 are formed to obtain the configuration shown in FIG. After cleaning with an organic solvent so that no flux components are present on the interface surface when laminating with the second layer substrate 10, the second layer substrate 10 and the second layer substrate 10 are brought into contact with each other to achieve positional accuracy via a pin guide or the like. Furthermore, the temperature is increased while applying pressure using a jig or the like so that a uniform load is applied to the entire surface of the substrate, and the circuit pattern 11 of the second layer substrate 10 is bonded to the circuit pattern 11 of the second layer substrate 10 via the solder bumps 8.
After laminating the third and fourth layer substrates using the same method and structure, liquid resin 12 is applied to the gap between the substrates.
is vacuum-injected to obtain a high-density mounting module with a multilayer structure of a board with built-in components.
さらに付け加えて説明すると、この種の部品を
基板に埋込み用半田バンプを介して多層化を構成
する場合、半田接合面は平面に衝合し、僅少量で
接合することが多層化に伴う熱衝撃により接合面
の剥離などの不具合を防止する。併せて、基板の
貼り合わせ部分に空隙の無い基板相互の貼り合わ
せ時に同一平面上の均一な厚さを得ることが同種
不具合防止策として有効であるが、本発明によれ
ば、半田バンプの量を正確に構成することが出来
るため、基板の回路パターンを構成する銅箔など
の導体を真空蒸着あるいはスパツタ法で被着し5
ミクロン以下とし、半田バンプの厚さを僅少量と
して基板貼り合わせ部分に充填する樹脂を介する
ことなく半田バンプの接合のみで空隙のない多層
化を行なうことが出来る。 To further explain, when configuring multi-layers of this type of component via solder bumps for embedding on the board, the solder joint surfaces are flat, and it is difficult to bond with a small amount due to the thermal shock caused by multi-layering. This prevents problems such as peeling of the bonded surface. In addition, it is effective to obtain a uniform thickness on the same plane when bonding substrates without any gaps in the bonded portion of the substrates, as a measure to prevent similar defects.According to the present invention, the amount of solder bumps Because it is possible to accurately configure the circuit pattern, the conductor such as copper foil that makes up the circuit pattern on the board is deposited by vacuum evaporation or sputtering.
By setting the thickness of the solder bumps to a micrometer or less and making the thickness of the solder bumps a very small amount, it is possible to form a multilayer structure without voids only by joining the solder bumps without intervening a resin filled in the bonded portion of the substrates.
(発明の効果)
以上説明したように、回路パターンを有し、部
品埋込み用孔部を有する基板に部品を挿入し、回
路パターンと同一平面に部品を保持し、半他クリ
ームを印刷して半田バンプを形成して、異なる基
板と貼り合わせ、均一な半田量と僅少量の半田で
多層化を行なうことが出来るから、回路間の短絡
のない、熱衝撃に対しても破損のない、部品を内
蔵した高密度実装モジユールを提供出来る利点が
ある。(Effect of the invention) As explained above, a component is inserted into a board having a circuit pattern and a hole for embedding the component, the component is held on the same plane as the circuit pattern, and a half-tone cream is printed and soldered. By forming bumps and bonding them to different boards, it is possible to create multiple layers with a uniform amount of solder and a very small amount of solder, so parts can be created without shorting between circuits and without being damaged by thermal shock. It has the advantage of providing a built-in high-density mounting module.
第1図、第2図は、本発明の実施例の工程説明
図、第3図は本発明の実施例の断面図を示す。
1……第1層基板、2……孔部、3……第1層
基板の回路パターン、4……位置出し用フイル
ム、5……埋込み用部品、6……充填する樹脂、
7……埋込み用部品の取付ランド、8……埋込み
用部品の半田バンプ、9……回路パターン接合用
半田バンプ、10……第2層基板、11……空隙
充填樹脂。
1 and 2 are process explanatory diagrams of an embodiment of the present invention, and FIG. 3 is a sectional view of the embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... First layer board, 2... Hole, 3... Circuit pattern of first layer board, 4... Positioning film, 5... Parts for embedding, 6... Resin to be filled.
7... Mounting land for embedding parts, 8... Solder bumps for embedding parts, 9... Solder bumps for circuit pattern bonding, 10... Second layer board, 11... Gap filling resin.
Claims (1)
樹脂基板に部品埋込み用の孔部を穿つ手段と、該
孔部に位置出し用フイルムに装着した部品を回路
パターンと同一平面上に位置するように内装する
手段と、前記孔部に前記部品固定用の樹脂を充填
する手段と、前記部品に設けた半田バンプを介し
て複数の基板を貼り合わせる手段を有することを
特徴とする高密度実装モジユールの製造方法。 2 特許請求の範囲第1項記載の位置出し用フイ
ルムをポリエーテルエーテルケトンとしたことを
特徴とする高密度実装モジユールの製造方法。[Scope of Claims] 1. A resin substrate having a circuit pattern, a means for drilling a hole in the resin substrate for embedding a component, and a means for placing the component mounted on a positioning film in the hole on the same plane as the circuit pattern. 1. A high riser characterized by comprising: means for filling the hole with resin for fixing the component; and means for bonding a plurality of substrates together via solder bumps provided on the component. A method for manufacturing a density-mounted module. 2. A method for producing a high-density mounting module, characterized in that the positioning film according to claim 1 is made of polyetheretherketone.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1134180A JPH02312296A (en) | 1989-05-26 | 1989-05-26 | Manufacture of high density mounting module |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1134180A JPH02312296A (en) | 1989-05-26 | 1989-05-26 | Manufacture of high density mounting module |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH02312296A JPH02312296A (en) | 1990-12-27 |
JPH0563112B2 true JPH0563112B2 (en) | 1993-09-09 |
Family
ID=15122313
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1134180A Granted JPH02312296A (en) | 1989-05-26 | 1989-05-26 | Manufacture of high density mounting module |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02312296A (en) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1174648A (en) * | 1997-08-27 | 1999-03-16 | Kyocera Corp | Wiring board |
FR2783354B1 (en) * | 1998-08-25 | 2002-07-12 | Commissariat Energie Atomique | COLLECTIVE PROCESS FOR CONDITIONING A PLURALITY OF COMPONENTS FORMED INITIALLY IN THE SAME SUBSTRATE |
US6909054B2 (en) | 2000-02-25 | 2005-06-21 | Ibiden Co., Ltd. | Multilayer printed wiring board and method for producing multilayer printed wiring board |
JP4695289B2 (en) * | 2000-07-31 | 2011-06-08 | 日本特殊陶業株式会社 | Wiring board manufacturing method |
WO2002027786A1 (en) | 2000-09-25 | 2002-04-04 | Ibiden Co., Ltd. | Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board |
JP2003152317A (en) * | 2000-12-25 | 2003-05-23 | Ngk Spark Plug Co Ltd | Wiring board |
JP2002237683A (en) * | 2001-02-08 | 2002-08-23 | Ngk Spark Plug Co Ltd | Method for manufacturing circuit board |
JP4714510B2 (en) * | 2005-06-15 | 2011-06-29 | 日本特殊陶業株式会社 | Wiring board manufacturing method |
JP4648230B2 (en) * | 2006-03-24 | 2011-03-09 | 日本特殊陶業株式会社 | Wiring board manufacturing method |
KR100986829B1 (en) * | 2007-11-07 | 2010-10-12 | 삼성전기주식회사 | manufacturing method of PCB |
JP2014072279A (en) * | 2012-09-28 | 2014-04-21 | Dainippon Printing Co Ltd | Manufacturing method of wiring board with components incorporated therein |
-
1989
- 1989-05-26 JP JP1134180A patent/JPH02312296A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPH02312296A (en) | 1990-12-27 |
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